@@ -92,6 +92,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = true,
.tx_mac_seq_by_fw = false,
.dynamic_sar_support = false,
+ .tx_credit_limit = false,
},
{
.id = QCA988X_HW_2_0_VERSION,
@@ -128,6 +129,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = true,
.tx_mac_seq_by_fw = false,
.dynamic_sar_support = false,
+ .tx_credit_limit = false,
},
{
.id = QCA9887_HW_1_0_VERSION,
@@ -165,6 +167,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = false,
.tx_mac_seq_by_fw = false,
.dynamic_sar_support = false,
+ .tx_credit_limit = false,
},
{
.id = QCA6174_HW_3_2_VERSION,
@@ -196,6 +199,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_mac_seq_by_fw = false,
.bmi_large_size_download = true,
.dynamic_sar_support = true,
+ .tx_credit_limit = false,
},
{
.id = QCA6174_HW_2_1_VERSION,
@@ -232,6 +236,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = false,
.tx_mac_seq_by_fw = false,
.dynamic_sar_support = false,
+ .tx_credit_limit = false,
},
{
.id = QCA6174_HW_2_1_VERSION,
@@ -268,6 +273,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = false,
.tx_mac_seq_by_fw = false,
.dynamic_sar_support = false,
+ .tx_credit_limit = false,
},
{
.id = QCA6174_HW_3_0_VERSION,
@@ -304,6 +310,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = false,
.tx_mac_seq_by_fw = false,
.dynamic_sar_support = false,
+ .tx_credit_limit = false,
},
{
.id = QCA6174_HW_3_2_VERSION,
@@ -343,6 +350,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = false,
.tx_mac_seq_by_fw = false,
.dynamic_sar_support = true,
+ .tx_credit_limit = false,
},
{
.id = QCA99X0_HW_2_0_DEV_VERSION,
@@ -385,6 +393,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = false,
.tx_mac_seq_by_fw = false,
.dynamic_sar_support = false,
+ .tx_credit_limit = false,
},
{
.id = QCA9984_HW_1_0_DEV_VERSION,
@@ -434,6 +443,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = false,
.tx_mac_seq_by_fw = false,
.dynamic_sar_support = false,
+ .tx_credit_limit = false,
},
{
.id = QCA9888_HW_2_0_DEV_VERSION,
@@ -480,6 +490,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = false,
.tx_mac_seq_by_fw = false,
.dynamic_sar_support = false,
+ .tx_credit_limit = false,
},
{
.id = QCA9377_HW_1_0_DEV_VERSION,
@@ -516,6 +527,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = false,
.tx_mac_seq_by_fw = false,
.dynamic_sar_support = false,
+ .tx_credit_limit = false,
},
{
.id = QCA9377_HW_1_1_DEV_VERSION,
@@ -554,6 +566,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = false,
.tx_mac_seq_by_fw = false,
.dynamic_sar_support = false,
+ .tx_credit_limit = false,
},
{
.id = QCA9377_HW_1_1_DEV_VERSION,
@@ -625,6 +638,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = false,
.tx_mac_seq_by_fw = false,
.dynamic_sar_support = false,
+ .tx_credit_limit = false,
},
{
.id = WCN3990_HW_1_0_DEV_VERSION,
@@ -654,6 +668,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = false,
.tx_mac_seq_by_fw = true,
.dynamic_sar_support = true,
+ .tx_credit_limit = true,
},
};
@@ -630,13 +630,20 @@ int ath10k_htc_wait_target(struct ath10k_htc *htc)
return -ECOMM;
}
- htc->total_transmit_credits = __le16_to_cpu(msg->ready.credit_count);
+ if (ar->hw_params.tx_credit_limit)
+ htc->total_transmit_credits =
+ __le16_to_cpu(HTC_HOST_MAX_CREDIT_COUNT);
+ else
+ htc->total_transmit_credits =
+ __le16_to_cpu(msg->ready.credit_count);
+
htc->target_credit_size = __le16_to_cpu(msg->ready.credit_size);
ath10k_dbg(ar, ATH10K_DBG_HTC,
- "Target ready! transmit resources: %d size:%d\n",
+ "Target ready! transmit resources: %d size:%d actual credits:%d\n",
htc->total_transmit_credits,
- htc->target_credit_size);
+ htc->target_credit_size,
+ msg->ready.credit_count);
if ((htc->total_transmit_credits == 0) ||
(htc->target_credit_size == 0)) {
@@ -41,6 +41,7 @@ struct ath10k;
*/
#define HTC_HOST_MAX_MSG_PER_RX_BUNDLE 32
+#define HTC_HOST_MAX_CREDIT_COUNT 1
enum ath10k_htc_tx_flags {
ATH10K_HTC_FLAG_NEED_CREDIT_UPDATE = 0x01,
@@ -625,6 +625,9 @@ struct ath10k_hw_params {
bool tx_mac_seq_by_fw;
bool dynamic_sar_support;
+
+ /* limit tx credit */
+ bool tx_credit_limit;
};
struct htt_rx_desc;
Currently for WCN3990, the host driver can send two wmi commands at once, now it is limiting to one because if HOST wants to initiate 2 DMA transfers, it is possible when copy complete interrupt for first DMA reaches HOST, CE has already updated SRRI for both DMA transfers and is in the middle of 2nd DMA.HOST uses SRRI to interpret how many DMA’s have been completed and tries to unmap/free both the DMA entries, but CE is still in the middle of 2nd DMA which can cause SMMU issues or corruption. Tested-on: WLAN.HL.3.2.2.c10-00757-QCAHLSWMTPL-1 Signed-off-by: Youghandhar Chintala <quic_youghand@quicinc.com> --- drivers/net/wireless/ath/ath10k/core.c | 15 +++++++++++++++ drivers/net/wireless/ath/ath10k/htc.c | 13 ++++++++++--- drivers/net/wireless/ath/ath10k/htc.h | 1 + drivers/net/wireless/ath/ath10k/hw.h | 3 +++ 4 files changed, 29 insertions(+), 3 deletions(-)