| Message ID | 20220407202836.1211268-1-robdclark@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm: Fix range size vs end confusion | expand |
On Thu, 7 Apr 2022 at 23:27, Rob Clark <robdclark@gmail.com> wrote: > > From: Rob Clark <robdclark@chromium.org> > > The fourth param is size, rather than range_end. > > Note that we could increase the address space size if we had a way to > prevent buffers from spanning a 4G split, mostly just to avoid fw bugs > with 64b math. > > Fixes: 84c31ee16f90 ("drm/msm/a6xx: Add support for per-instance pagetables") > Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 17de46fc4bf2..80d57608b34a 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1742,7 +1742,7 @@ a6xx_create_private_address_space(struct msm_gpu *gpu) > return ERR_CAST(mmu); > > return msm_gem_address_space_create(mmu, > - "gpu", 0x100000000ULL, 0x1ffffffffULL); > + "gpu", 0x100000000ULL, SZ_4G); > } > > static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) > -- > 2.35.1 >
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 17de46fc4bf2..80d57608b34a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1742,7 +1742,7 @@ a6xx_create_private_address_space(struct msm_gpu *gpu) return ERR_CAST(mmu); return msm_gem_address_space_create(mmu, - "gpu", 0x100000000ULL, 0x1ffffffffULL); + "gpu", 0x100000000ULL, SZ_4G); } static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)