Message ID | 20220513171617.504430-6-angelogioacchino.delregno@collabora.com |
---|---|
State | New |
Headers | show |
Series | MediaTek Helio X10 MT6795 - Devicetree, part 1 | expand |
On 13/05/2022 19:16, AngeloGioacchino Del Regno wrote: > Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to > provide a good initial clock spec, since this SoC features two always I don't understand that part with actual patch. You claim here you add clocks, but in DTS they were already before. Additionally, these clocks do not belong to DTSI because, AFAIU, these are properties of boards. At least their frequencies should be moved to the board DTS. Best regards, Krzysztof
Il 16/05/22 09:10, Krzysztof Kozlowski ha scritto: > On 13/05/2022 19:16, AngeloGioacchino Del Regno wrote: >> Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to >> provide a good initial clock spec, since this SoC features two always > > I don't understand that part with actual patch. You claim here you add > clocks, but in DTS they were already before. > > Additionally, these clocks do not belong to DTSI because, AFAIU, these > are properties of boards. At least their frequencies should be moved to > the board DTS. > > I should reword the commit description to be clearer, sorry about that: I went with "exactly what I've done", but looking at the actual diff, it is just a rename. What my brain was ticking on here was about removing clocks that didn't really exist (uart_clk is not a fixed clock, etc), and adding the ones that do exist.... but then again, the result, casually, is a rename. In any case... no, these clocks are not board-specific for two reasons: 1. AFAIK, these fixed clock outputs are from the SoC itself, not from external components placed on the board, and 2. Even if these were from external components, the SoC *needs* these ones to work and any board that doesn't have these fixed XOs simply wouldn't be able to work. Cheers, Angelo
On 16/05/2022 10:51, AngeloGioacchino Del Regno wrote: >> >> > > I should reword the commit description to be clearer, sorry about that: I > went with "exactly what I've done", but looking at the actual diff, it is > just a rename. What my brain was ticking on here was about removing clocks > that didn't really exist (uart_clk is not a fixed clock, etc), and adding > the ones that do exist.... but then again, the result, casually, is a rename. Yes, some better explanation would help. > > In any case... no, these clocks are not board-specific for two reasons: > 1. AFAIK, these fixed clock outputs are from the SoC itself, not from > external components placed on the board, and This would be fine. > 2. Even if these were from external components, the SoC *needs* these > ones to work and any board that doesn't have these fixed XOs simply > wouldn't be able to work. This is common pattern and Mediatek is not different here. In all cases these are needed by SoC and in (almost?) all cases these should be provided by board DTS. The DTS describes here the hardware, the board has the clock thus the board DTS should define it. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 363fa25b4edc..b6f7681cc151 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -142,21 +142,23 @@ l2_1: l2-cache1 { }; }; - system_clk: dummy13m { + clk26m: oscillator-26m { compatible = "fixed-clock"; - clock-frequency = <13000000>; #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; }; - rtc_clk: dummy32k { + clk32k: oscillator-32k { compatible = "fixed-clock"; - clock-frequency = <32000>; #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "clk32k"; }; - uart_clk: dummy26m { + system_clk: dummy13m { compatible = "fixed-clock"; - clock-frequency = <26000000>; + clock-frequency = <13000000>; #clock-cells = <0>; }; @@ -221,7 +223,7 @@ uart0: serial@11002000 { "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; @@ -230,7 +232,7 @@ uart1: serial@11003000 { "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; @@ -239,7 +241,7 @@ uart2: serial@11004000 { "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; @@ -248,7 +250,7 @@ uart3: serial@11005000 { "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; };
Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to provide a good initial clock spec, since this SoC features two always on oscillators running at the aforementioned frequencies. While at it, since the UART clock is actually referring to the 26MHz oscillator, remove it and assign clk26m as "baud" clock for the UARTs. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-)