| Message ID | 20220513175339.2981959-4-dmitry.baryshkov@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: qcom: Rework pipe_clk/pipe_clk_src handling | expand |
On Fri, May 13, 2022 at 08:53:37PM +0300, Dmitry Baryshkov wrote: > Use newly defined clk_regmap_pipe_src_ops for PCIe pipe clocks to let clk_regmap_phy_mux > the clock framework automatically park the clock when the clock is > switched off and restore the parent when the clock is switched on. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Looks good otherwise: Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Quoting Dmitry Baryshkov (2022-05-13 10:53:37) > diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c > index 593a195467ff..a140a89b73b4 100644 > --- a/drivers/clk/qcom/gcc-sm8450.c > +++ b/drivers/clk/qcom/gcc-sm8450.c > @@ -239,17 +218,21 @@ static const struct clk_parent_data gcc_parent_data_11[] = { > { .fw_name = "bi_tcxo" }, > }; > > -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { > +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { > .reg = 0x7b060, > .shift = 0, > .width = 2, > - .parent_map = gcc_parent_map_4, > + .phy_src_val = 0, /* pipe_clk */ Make a define? PCIE0_PIPE_CLK_SRC_VAL and drop the comment? > + .ref_src_val = 2, /* bi_tcxo */ > .clkr = { > .hw.init = &(struct clk_init_data){ > .name = "gcc_pcie_0_pipe_clk_src", > - .parent_data = gcc_parent_data_4, > - .num_parents = ARRAY_SIZE(gcc_parent_data_4), > - .ops = &clk_regmap_mux_closest_ops, > + .parent_data = &(const struct clk_parent_data){ > + .fw_name = "pcie_0_pipe_clk", > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_regmap_phy_mux_ops, > }, > }, > };
On 18/05/2022 20:59, Stephen Boyd wrote: > Quoting Dmitry Baryshkov (2022-05-13 10:53:37) >> diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c >> index 593a195467ff..a140a89b73b4 100644 >> --- a/drivers/clk/qcom/gcc-sm8450.c >> +++ b/drivers/clk/qcom/gcc-sm8450.c >> @@ -239,17 +218,21 @@ static const struct clk_parent_data gcc_parent_data_11[] = { >> { .fw_name = "bi_tcxo" }, >> }; >> >> -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { >> +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { >> .reg = 0x7b060, >> .shift = 0, >> .width = 2, >> - .parent_map = gcc_parent_map_4, >> + .phy_src_val = 0, /* pipe_clk */ > > Make a define? PCIE0_PIPE_CLK_SRC_VAL and drop the comment? This value can change between the muxes. Thus I'd prefer not to do this. Compare it with the parent_maps, where we do not use defines for the 'val' part. > >> + .ref_src_val = 2, /* bi_tcxo */ >> .clkr = { >> .hw.init = &(struct clk_init_data){ >> .name = "gcc_pcie_0_pipe_clk_src", >> - .parent_data = gcc_parent_data_4, >> - .num_parents = ARRAY_SIZE(gcc_parent_data_4), >> - .ops = &clk_regmap_mux_closest_ops, >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "pcie_0_pipe_clk", >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_regmap_phy_mux_ops, >> }, >> }, >> };
- bouncing Prasad Quoting Dmitry Baryshkov (2022-05-18 11:26:16) > On 18/05/2022 20:59, Stephen Boyd wrote: > > Quoting Dmitry Baryshkov (2022-05-13 10:53:37) > >> diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c > >> index 593a195467ff..a140a89b73b4 100644 > >> --- a/drivers/clk/qcom/gcc-sm8450.c > >> +++ b/drivers/clk/qcom/gcc-sm8450.c > >> @@ -239,17 +218,21 @@ static const struct clk_parent_data gcc_parent_data_11[] = { > >> { .fw_name = "bi_tcxo" }, > >> }; > >> > >> -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { > >> +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { > >> .reg = 0x7b060, > >> .shift = 0, > >> .width = 2, > >> - .parent_map = gcc_parent_map_4, > >> + .phy_src_val = 0, /* pipe_clk */ > > > > Make a define? PCIE0_PIPE_CLK_SRC_VAL and drop the comment? > > This value can change between the muxes. Thus I'd prefer not to do this. > Compare it with the parent_maps, where we do not use defines for the > 'val' part. > We don't have defines for the parent maps because they have defines for the other side.
diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 593a195467ff..a140a89b73b4 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -17,6 +17,7 @@ #include "clk-regmap.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" #include "gdsc.h" #include "reset.h" @@ -26,9 +27,7 @@ enum { P_GCC_GPLL0_OUT_MAIN, P_GCC_GPLL4_OUT_MAIN, P_GCC_GPLL9_OUT_MAIN, - P_PCIE_0_PIPE_CLK, P_PCIE_1_PHY_AUX_CLK, - P_PCIE_1_PIPE_CLK, P_SLEEP_CLK, P_UFS_PHY_RX_SYMBOL_0_CLK, P_UFS_PHY_RX_SYMBOL_1_CLK, @@ -153,16 +152,6 @@ static const struct clk_parent_data gcc_parent_data_3[] = { { .fw_name = "bi_tcxo" }, }; -static const struct parent_map gcc_parent_map_4[] = { - { P_PCIE_0_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_4[] = { - { .fw_name = "pcie_0_pipe_clk", }, - { .fw_name = "bi_tcxo", }, -}; - static const struct parent_map gcc_parent_map_5[] = { { P_PCIE_1_PHY_AUX_CLK, 0 }, { P_BI_TCXO, 2 }, @@ -173,16 +162,6 @@ static const struct clk_parent_data gcc_parent_data_5[] = { { .fw_name = "bi_tcxo" }, }; -static const struct parent_map gcc_parent_map_6[] = { - { P_PCIE_1_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_6[] = { - { .fw_name = "pcie_1_pipe_clk" }, - { .fw_name = "bi_tcxo" }, -}; - static const struct parent_map gcc_parent_map_7[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -239,17 +218,21 @@ static const struct clk_parent_data gcc_parent_data_11[] = { { .fw_name = "bi_tcxo" }, }; -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x7b060, .shift = 0, .width = 2, - .parent_map = gcc_parent_map_4, + .phy_src_val = 0, /* pipe_clk */ + .ref_src_val = 2, /* bi_tcxo */ .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk_src", - .parent_data = gcc_parent_data_4, - .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_0_pipe_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_phy_mux_ops, }, }, }; @@ -269,17 +252,21 @@ static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { }, }; -static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { .reg = 0x9d064, .shift = 0, .width = 2, - .parent_map = gcc_parent_map_6, + .phy_src_val = 0, /* pipe_clk */ + .ref_src_val = 2, /* bi_tcxo */ .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk_src", - .parent_data = gcc_parent_data_6, - .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_1_pipe_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_phy_mux_ops, }, }, };
Use newly defined clk_regmap_pipe_src_ops for PCIe pipe clocks to let the clock framework automatically park the clock when the clock is switched off and restore the parent when the clock is switched on. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-sm8450.c | 51 +++++++++++++---------------------- 1 file changed, 19 insertions(+), 32 deletions(-)