| Message ID | 20220711082940.39539-6-krzysztof.kozlowski@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | dt-bindings: mmc: / ARM: qcom: correct reg-names and clock entries | expand |
On 11.07.2022 10:29, Krzysztof Kozlowski wrote: > The DT schema expects clocks iface-core order. No functional change. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Reviewed-by: Douglas Anderson <dianders@chromium.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > arch/arm/boot/dts/qcom-apq8084.dtsi | 12 ++++++------ > arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++-- > arch/arm/boot/dts/qcom-msm8226.dtsi | 18 +++++++++--------- > arch/arm/boot/dts/qcom-msm8974.dtsi | 18 +++++++++--------- > arch/arm/boot/dts/qcom-msm8974pro.dtsi | 6 +++--- > 5 files changed, 29 insertions(+), 29 deletions(-) > > diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi > index 45f3cbcf6238..c887ac5cdd7d 100644 > --- a/arch/arm/boot/dts/qcom-apq8084.dtsi > +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi > @@ -425,10 +425,10 @@ mmc@f9824900 { > reg-names = "hc", "core"; > interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "hc_irq", "pwr_irq"; > - clocks = <&gcc GCC_SDCC1_APPS_CLK>, > - <&gcc GCC_SDCC1_AHB_CLK>, > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > + <&gcc GCC_SDCC1_APPS_CLK>, > <&xo_board>; > - clock-names = "core", "iface", "xo"; > + clock-names = "iface", "core", "xo"; > status = "disabled"; > }; > > @@ -438,10 +438,10 @@ mmc@f98a4900 { > reg-names = "hc", "core"; > interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "hc_irq", "pwr_irq"; > - clocks = <&gcc GCC_SDCC2_APPS_CLK>, > - <&gcc GCC_SDCC2_AHB_CLK>, > + clocks = <&gcc GCC_SDCC2_AHB_CLK>, > + <&gcc GCC_SDCC2_APPS_CLK>, > <&xo_board>; > - clock-names = "core", "iface", "xo"; > + clock-names = "iface", "core", "xo"; > status = "disabled"; > }; > > diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi > index 1b98764bab7a..a8a32a5e7e5d 100644 > --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi > +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi > @@ -228,9 +228,9 @@ sdhci: mmc@7824900 { > interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "hc_irq", "pwr_irq"; > bus-width = <8>; > - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, > <&gcc GCC_DCD_XO_CLK>; > - clock-names = "core", "iface", "xo"; > + clock-names = "iface", "core", "xo"; > status = "disabled"; > }; > > diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi > index f711463d22dc..9d4223bf8fc1 100644 > --- a/arch/arm/boot/dts/qcom-msm8226.dtsi > +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi > @@ -141,10 +141,10 @@ sdhc_1: mmc@f9824900 { > interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "hc_irq", "pwr_irq"; > - clocks = <&gcc GCC_SDCC1_APPS_CLK>, > - <&gcc GCC_SDCC1_AHB_CLK>, > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > + <&gcc GCC_SDCC1_APPS_CLK>, > <&xo_board>; > - clock-names = "core", "iface", "xo"; > + clock-names = "iface", "core", "xo"; > pinctrl-names = "default"; > pinctrl-0 = <&sdhc1_default_state>; > status = "disabled"; > @@ -157,10 +157,10 @@ sdhc_2: mmc@f98a4900 { > interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "hc_irq", "pwr_irq"; > - clocks = <&gcc GCC_SDCC2_APPS_CLK>, > - <&gcc GCC_SDCC2_AHB_CLK>, > + clocks = <&gcc GCC_SDCC2_AHB_CLK>, > + <&gcc GCC_SDCC2_APPS_CLK>, > <&xo_board>; > - clock-names = "core", "iface", "xo"; > + clock-names = "iface", "core", "xo"; > pinctrl-names = "default"; > pinctrl-0 = <&sdhc2_default_state>; > status = "disabled"; > @@ -173,10 +173,10 @@ sdhc_3: mmc@f9864900 { > interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "hc_irq", "pwr_irq"; > - clocks = <&gcc GCC_SDCC3_APPS_CLK>, > - <&gcc GCC_SDCC3_AHB_CLK>, > + clocks = <&gcc GCC_SDCC3_AHB_CLK>, > + <&gcc GCC_SDCC3_APPS_CLK>, > <&xo_board>; > - clock-names = "core", "iface", "xo"; > + clock-names = "iface", "core", "xo"; > pinctrl-names = "default"; > pinctrl-0 = <&sdhc3_default_state>; > status = "disabled"; > diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi > index 971eceaef3d1..1f4baa6ac64d 100644 > --- a/arch/arm/boot/dts/qcom-msm8974.dtsi > +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi > @@ -443,10 +443,10 @@ sdhc_1: mmc@f9824900 { > interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "hc_irq", "pwr_irq"; > - clocks = <&gcc GCC_SDCC1_APPS_CLK>, > - <&gcc GCC_SDCC1_AHB_CLK>, > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > + <&gcc GCC_SDCC1_APPS_CLK>, > <&xo_board>; > - clock-names = "core", "iface", "xo"; > + clock-names = "iface", "core", "xo"; > bus-width = <8>; > non-removable; > > @@ -460,10 +460,10 @@ sdhc_3: mmc@f9864900 { > interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "hc_irq", "pwr_irq"; > - clocks = <&gcc GCC_SDCC3_APPS_CLK>, > - <&gcc GCC_SDCC3_AHB_CLK>, > + clocks = <&gcc GCC_SDCC3_AHB_CLK>, > + <&gcc GCC_SDCC3_APPS_CLK>, > <&xo_board>; > - clock-names = "core", "iface", "xo"; > + clock-names = "iface", "core", "xo"; > bus-width = <4>; > > #address-cells = <1>; > @@ -479,10 +479,10 @@ sdhc_2: mmc@f98a4900 { > interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "hc_irq", "pwr_irq"; > - clocks = <&gcc GCC_SDCC2_APPS_CLK>, > - <&gcc GCC_SDCC2_AHB_CLK>, > + clocks = <&gcc GCC_SDCC2_AHB_CLK>, > + <&gcc GCC_SDCC2_APPS_CLK>, > <&xo_board>; > - clock-names = "core", "iface", "xo"; > + clock-names = "iface", "core", "xo"; > bus-width = <4>; > > #address-cells = <1>; > diff --git a/arch/arm/boot/dts/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qcom-msm8974pro.dtsi > index 1e882e16a221..58df6e75ab6d 100644 > --- a/arch/arm/boot/dts/qcom-msm8974pro.dtsi > +++ b/arch/arm/boot/dts/qcom-msm8974pro.dtsi > @@ -10,10 +10,10 @@ &gpu { > }; > > &sdhc_1 { > - clocks = <&gcc GCC_SDCC1_APPS_CLK>, > - <&gcc GCC_SDCC1_AHB_CLK>, > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > + <&gcc GCC_SDCC1_APPS_CLK>, > <&xo_board>, > <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, > <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; > - clock-names = "core", "iface", "xo", "cal", "sleep"; > + clock-names = "iface", "core", "xo", "cal", "sleep"; > };
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 45f3cbcf6238..c887ac5cdd7d 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -425,10 +425,10 @@ mmc@f9824900 { reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; status = "disabled"; }; @@ -438,10 +438,10 @@ mmc@f98a4900 { reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 1b98764bab7a..a8a32a5e7e5d 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -228,9 +228,9 @@ sdhci: mmc@7824900 { interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; bus-width = <8>; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_DCD_XO_CLK>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index f711463d22dc..9d4223bf8fc1 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -141,10 +141,10 @@ sdhc_1: mmc@f9824900 { interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc1_default_state>; status = "disabled"; @@ -157,10 +157,10 @@ sdhc_2: mmc@f98a4900 { interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc2_default_state>; status = "disabled"; @@ -173,10 +173,10 @@ sdhc_3: mmc@f9864900 { interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC3_APPS_CLK>, - <&gcc GCC_SDCC3_AHB_CLK>, + clocks = <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc3_default_state>; status = "disabled"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 971eceaef3d1..1f4baa6ac64d 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -443,10 +443,10 @@ sdhc_1: mmc@f9824900 { interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; bus-width = <8>; non-removable; @@ -460,10 +460,10 @@ sdhc_3: mmc@f9864900 { interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC3_APPS_CLK>, - <&gcc GCC_SDCC3_AHB_CLK>, + clocks = <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; bus-width = <4>; #address-cells = <1>; @@ -479,10 +479,10 @@ sdhc_2: mmc@f98a4900 { interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; bus-width = <4>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qcom-msm8974pro.dtsi index 1e882e16a221..58df6e75ab6d 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974pro.dtsi @@ -10,10 +10,10 @@ &gpu { }; &sdhc_1 { - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>, <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; - clock-names = "core", "iface", "xo", "cal", "sleep"; + clock-names = "iface", "core", "xo", "cal", "sleep"; };