| Message ID | 20220715123323.1550983-1-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Don't set syndrome ISS for loads and stores with writeback | expand |
On 7/15/22 18:03, Peter Maydell wrote: > The architecture requires that for faults on loads and stores which > do writeback, the syndrome information does not have the ISS > instruction syndrome information (i.e. ISV is 0). We got this wrong > for the load and store instructions covered by disas_ldst_reg_imm9(). > Calculate iss_valid correctly so that if the insn is a writeback one > it is false. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1057 > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > Tested with RTH's test case attached to the bug report. > --- > target/arm/translate-a64.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index b7b64f73584..163df8c6157 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -3138,7 +3138,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, > bool is_store = false; > bool is_extended = false; > bool is_unpriv = (idx == 2); > - bool iss_valid = !is_vector; > + bool iss_valid; > bool post_index; > bool writeback; > int memidx; > @@ -3191,6 +3191,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, > g_assert_not_reached(); > } > > + iss_valid = !is_vector && !writeback; > + > if (rn == 31) { > gen_check_sp_alignment(s); > }
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b7b64f73584..163df8c6157 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3138,7 +3138,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, bool is_store = false; bool is_extended = false; bool is_unpriv = (idx == 2); - bool iss_valid = !is_vector; + bool iss_valid; bool post_index; bool writeback; int memidx; @@ -3191,6 +3191,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, g_assert_not_reached(); } + iss_valid = !is_vector && !writeback; + if (rn == 31) { gen_check_sp_alignment(s); }
The architecture requires that for faults on loads and stores which do writeback, the syndrome information does not have the ISS instruction syndrome information (i.e. ISV is 0). We got this wrong for the load and store instructions covered by disas_ldst_reg_imm9(). Calculate iss_valid correctly so that if the insn is a writeback one it is false. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1057 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- Tested with RTH's test case attached to the bug report. --- target/arm/translate-a64.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)