| Message ID | 20220812060602.7672-2-manivannan.sadhasivam@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Fix crash when using Qcom LLCC/EDAC drivers | expand |
Hi Mani, On 8/12/2022 11:36 AM, Manivannan Sadhasivam wrote: > The LLCC EDAC register offsets varies between each SoCs. Until now, the > EDAC driver used the hardcoded register offsets. But this caused crash > on SM8450 SoC where the register offsets has been changed. > > So to avoid this crash and also to make it easy to accomodate changes for > new SoCs, let's pass the SoC specific register offsets to the EDAC driver. > > Currently, two set of offsets are used. One is SM8450 specific and another > one is common to all SoCs. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> <snip> ... > static const struct qcom_llcc_config sm8350_cfg = { > @@ -309,6 +370,7 @@ static const struct qcom_llcc_config sm8350_cfg = { > .size = ARRAY_SIZE(sm8350_data), > .need_llcc_cfg = true, > .reg_offset = llcc_v1_2_reg_offset, > + .edac_reg = &common_edac_reg, > }; > > static const struct qcom_llcc_config sm8450_cfg = { > @@ -316,6 +378,7 @@ static const struct qcom_llcc_config sm8450_cfg = { > .size = ARRAY_SIZE(sm8450_data), > .need_llcc_cfg = true, > .reg_offset = llcc_v21_reg_offset, > + .edac_reg = &sm8450_edac_reg, > }; > Can we have LLCC version specific register offsets instead of SoC specific similar to reg_offset callbacks? For SM8450, it would be llcc_v21_edac_reg and for others llcc_v1_2_edac_reg instead of common_edac_reg. common_edac_reg is very general and is not exactly common for all, its just common for SoCs with same LLCC. Version based is more applicable as multiple SoCs might use same LLCC versions and would reduce SoC specific data which would be needed for every SoC in case some newer LLCC comes out. I know you could just call sm8450_edac_reg for lets say sm8550 or so on to reduce duplication but that won't look good. Thanks, Sai
On Mon, Aug 22, 2022 at 05:29:13PM +0530, Sai Prakash Ranjan wrote: > Hi Mani, > > On 8/12/2022 11:36 AM, Manivannan Sadhasivam wrote: > > The LLCC EDAC register offsets varies between each SoCs. Until now, the > > EDAC driver used the hardcoded register offsets. But this caused crash > > on SM8450 SoC where the register offsets has been changed. > > > > So to avoid this crash and also to make it easy to accomodate changes for > > new SoCs, let's pass the SoC specific register offsets to the EDAC driver. > > > > Currently, two set of offsets are used. One is SM8450 specific and another > > one is common to all SoCs. > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > <snip> ... > > > static const struct qcom_llcc_config sm8350_cfg = { > > @@ -309,6 +370,7 @@ static const struct qcom_llcc_config sm8350_cfg = { > > .size = ARRAY_SIZE(sm8350_data), > > .need_llcc_cfg = true, > > .reg_offset = llcc_v1_2_reg_offset, > > + .edac_reg = &common_edac_reg, > > }; > > static const struct qcom_llcc_config sm8450_cfg = { > > @@ -316,6 +378,7 @@ static const struct qcom_llcc_config sm8450_cfg = { > > .size = ARRAY_SIZE(sm8450_data), > > .need_llcc_cfg = true, > > .reg_offset = llcc_v21_reg_offset, > > + .edac_reg = &sm8450_edac_reg, > > }; > > > > Can we have LLCC version specific register offsets instead of SoC specific similar to reg_offset callbacks? > For SM8450, it would be llcc_v21_edac_reg and for others llcc_v1_2_edac_reg instead of common_edac_reg. > common_edac_reg is very general and is not exactly common for all, its just common for SoCs with same LLCC. > I thought about it but I was not sure if rest of the SoCs are using version v1.2. I know that reg_offset uses v1.2 but I was skeptical and hence used the SoC specific offsets. Can you confirm if rest of the SoCs are using v1.2? Thanks, Mani > Version based is more applicable as multiple SoCs might use same LLCC versions and would reduce SoC specific data > which would be needed for every SoC in case some newer LLCC comes out. I know you could just call sm8450_edac_reg > for lets say sm8550 or so on to reduce duplication but that won't look good. > > > Thanks, > Sai
On 8/23/2022 9:01 PM, Manivannan Sadhasivam wrote: > On Mon, Aug 22, 2022 at 05:29:13PM +0530, Sai Prakash Ranjan wrote: >> Hi Mani, >> >> On 8/12/2022 11:36 AM, Manivannan Sadhasivam wrote: >>> The LLCC EDAC register offsets varies between each SoCs. Until now, the >>> EDAC driver used the hardcoded register offsets. But this caused crash >>> on SM8450 SoC where the register offsets has been changed. >>> >>> So to avoid this crash and also to make it easy to accomodate changes for >>> new SoCs, let's pass the SoC specific register offsets to the EDAC driver. >>> >>> Currently, two set of offsets are used. One is SM8450 specific and another >>> one is common to all SoCs. >>> >>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> >> <snip> ... >> >>> static const struct qcom_llcc_config sm8350_cfg = { >>> @@ -309,6 +370,7 @@ static const struct qcom_llcc_config sm8350_cfg = { >>> .size = ARRAY_SIZE(sm8350_data), >>> .need_llcc_cfg = true, >>> .reg_offset = llcc_v1_2_reg_offset, >>> + .edac_reg = &common_edac_reg, >>> }; >>> static const struct qcom_llcc_config sm8450_cfg = { >>> @@ -316,6 +378,7 @@ static const struct qcom_llcc_config sm8450_cfg = { >>> .size = ARRAY_SIZE(sm8450_data), >>> .need_llcc_cfg = true, >>> .reg_offset = llcc_v21_reg_offset, >>> + .edac_reg = &sm8450_edac_reg, >>> }; >>> >> Can we have LLCC version specific register offsets instead of SoC specific similar to reg_offset callbacks? >> For SM8450, it would be llcc_v21_edac_reg and for others llcc_v1_2_edac_reg instead of common_edac_reg. >> common_edac_reg is very general and is not exactly common for all, its just common for SoCs with same LLCC. >> > I thought about it but I was not sure if rest of the SoCs are using version > v1.2. I know that reg_offset uses v1.2 but I was skeptical and hence used the > SoC specific offsets. > > Can you confirm if rest of the SoCs are using v1.2? LLCC versioning follows w.x.y.z format and w and y are major and minor versions based on which the naming for reg_offsets is chosen. Now in above reg_offsets, llcc_v1_2 is not v1.2, it means v1.0 or v2.0 where 1, 2 is a major version and 0 is a minor version. llcc_v21 is actually v2.1 where 2 is a major and 1 is a minor version. I know the naming is pretty bad, should probably replace llcc_v1_2 with llcc_v1_0_v2_0 and llcc_v21 with llcc_v2_1? Note here minor version is important because SM8350 is v2.0 and uses old reg offsets. So coming to your query now, all other SoCs except SM8450(which uses v2.1) are using LLCC v1.0 or v2.0, so it is valid to use the same logic as reg_offsets for edac_reg. Thanks, Sai > Thanks, > Mani > >> Version based is more applicable as multiple SoCs might use same LLCC versions and would reduce SoC specific data >> which would be needed for every SoC in case some newer LLCC comes out. I know you could just call sm8450_edac_reg >> for lets say sm8550 or so on to reduce duplication but that won't look good. >> >> >> Thanks, >> Sai
On Wed, Aug 24, 2022 at 10:43:51AM +0530, Sai Prakash Ranjan wrote: > On 8/23/2022 9:01 PM, Manivannan Sadhasivam wrote: > > On Mon, Aug 22, 2022 at 05:29:13PM +0530, Sai Prakash Ranjan wrote: > > > Hi Mani, > > > > > > On 8/12/2022 11:36 AM, Manivannan Sadhasivam wrote: > > > > The LLCC EDAC register offsets varies between each SoCs. Until now, the > > > > EDAC driver used the hardcoded register offsets. But this caused crash > > > > on SM8450 SoC where the register offsets has been changed. > > > > > > > > So to avoid this crash and also to make it easy to accomodate changes for > > > > new SoCs, let's pass the SoC specific register offsets to the EDAC driver. > > > > > > > > Currently, two set of offsets are used. One is SM8450 specific and another > > > > one is common to all SoCs. > > > > > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > <snip> ... > > > > > > > static const struct qcom_llcc_config sm8350_cfg = { > > > > @@ -309,6 +370,7 @@ static const struct qcom_llcc_config sm8350_cfg = { > > > > .size = ARRAY_SIZE(sm8350_data), > > > > .need_llcc_cfg = true, > > > > .reg_offset = llcc_v1_2_reg_offset, > > > > + .edac_reg = &common_edac_reg, > > > > }; > > > > static const struct qcom_llcc_config sm8450_cfg = { > > > > @@ -316,6 +378,7 @@ static const struct qcom_llcc_config sm8450_cfg = { > > > > .size = ARRAY_SIZE(sm8450_data), > > > > .need_llcc_cfg = true, > > > > .reg_offset = llcc_v21_reg_offset, > > > > + .edac_reg = &sm8450_edac_reg, > > > > }; > > > > > > > Can we have LLCC version specific register offsets instead of SoC specific similar to reg_offset callbacks? > > > For SM8450, it would be llcc_v21_edac_reg and for others llcc_v1_2_edac_reg instead of common_edac_reg. > > > common_edac_reg is very general and is not exactly common for all, its just common for SoCs with same LLCC. > > > > > I thought about it but I was not sure if rest of the SoCs are using version > > v1.2. I know that reg_offset uses v1.2 but I was skeptical and hence used the > > SoC specific offsets. > > > > Can you confirm if rest of the SoCs are using v1.2? > > LLCC versioning follows w.x.y.z format and w and y are major and minor versions based > on which the naming for reg_offsets is chosen. > > Now in above reg_offsets, llcc_v1_2 is not v1.2, it means v1.0 or v2.0 where 1, 2 is a major version > and 0 is a minor version. llcc_v21 is actually v2.1 where 2 is a major and 1 is a minor version. > I know the naming is pretty bad, should probably replace llcc_v1_2 with llcc_v1_0_v2_0 and > llcc_v21 with llcc_v2_1? Note here minor version is important because SM8350 is v2.0 and uses > old reg offsets. > Yeah it is confusing. I think we should just use the base LLCC version that got changed with the previous one and add a comment on top of the definition. For instance, all of the SoCs before SM8450 should use llcc_v1_reg_offset since the LLCC version starts from v1.0.0 and SM8450 should use llcc_v2_1_reg_offset since it supports the LLCC reg offset that got changed since v2.1.0. Thoughts? Thanks, Mani > So coming to your query now, all other SoCs except SM8450(which uses v2.1) are using LLCC v1.0 > or v2.0, so it is valid to use the same logic as reg_offsets for edac_reg. > > Thanks, > Sai > > > Thanks, > > Mani > > > > > Version based is more applicable as multiple SoCs might use same LLCC versions and would reduce SoC specific data > > > which would be needed for every SoC in case some newer LLCC comes out. I know you could just call sm8450_edac_reg > > > for lets say sm8550 or so on to reduce duplication but that won't look good. > > > > > > > > > Thanks, > > > Sai >
On 8/24/2022 6:27 PM, Manivannan Sadhasivam wrote: > On Wed, Aug 24, 2022 at 10:43:51AM +0530, Sai Prakash Ranjan wrote: >> On 8/23/2022 9:01 PM, Manivannan Sadhasivam wrote: >>> On Mon, Aug 22, 2022 at 05:29:13PM +0530, Sai Prakash Ranjan wrote: >>>> Hi Mani, >>>> >>>> On 8/12/2022 11:36 AM, Manivannan Sadhasivam wrote: >>>>> The LLCC EDAC register offsets varies between each SoCs. Until now, the >>>>> EDAC driver used the hardcoded register offsets. But this caused crash >>>>> on SM8450 SoC where the register offsets has been changed. >>>>> >>>>> So to avoid this crash and also to make it easy to accomodate changes for >>>>> new SoCs, let's pass the SoC specific register offsets to the EDAC driver. >>>>> >>>>> Currently, two set of offsets are used. One is SM8450 specific and another >>>>> one is common to all SoCs. >>>>> >>>>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> >>>> <snip> ... >>>> >>>>> static const struct qcom_llcc_config sm8350_cfg = { >>>>> @@ -309,6 +370,7 @@ static const struct qcom_llcc_config sm8350_cfg = { >>>>> .size = ARRAY_SIZE(sm8350_data), >>>>> .need_llcc_cfg = true, >>>>> .reg_offset = llcc_v1_2_reg_offset, >>>>> + .edac_reg = &common_edac_reg, >>>>> }; >>>>> static const struct qcom_llcc_config sm8450_cfg = { >>>>> @@ -316,6 +378,7 @@ static const struct qcom_llcc_config sm8450_cfg = { >>>>> .size = ARRAY_SIZE(sm8450_data), >>>>> .need_llcc_cfg = true, >>>>> .reg_offset = llcc_v21_reg_offset, >>>>> + .edac_reg = &sm8450_edac_reg, >>>>> }; >>>>> >>>> Can we have LLCC version specific register offsets instead of SoC specific similar to reg_offset callbacks? >>>> For SM8450, it would be llcc_v21_edac_reg and for others llcc_v1_2_edac_reg instead of common_edac_reg. >>>> common_edac_reg is very general and is not exactly common for all, its just common for SoCs with same LLCC. >>>> >>> I thought about it but I was not sure if rest of the SoCs are using version >>> v1.2. I know that reg_offset uses v1.2 but I was skeptical and hence used the >>> SoC specific offsets. >>> >>> Can you confirm if rest of the SoCs are using v1.2? >> LLCC versioning follows w.x.y.z format and w and y are major and minor versions based >> on which the naming for reg_offsets is chosen. >> >> Now in above reg_offsets, llcc_v1_2 is not v1.2, it means v1.0 or v2.0 where 1, 2 is a major version >> and 0 is a minor version. llcc_v21 is actually v2.1 where 2 is a major and 1 is a minor version. >> I know the naming is pretty bad, should probably replace llcc_v1_2 with llcc_v1_0_v2_0 and >> llcc_v21 with llcc_v2_1? Note here minor version is important because SM8350 is v2.0 and uses >> old reg offsets. >> > Yeah it is confusing. I think we should just use the base LLCC version > that got changed with the previous one and add a comment on top of the > definition. For instance, all of the SoCs before SM8450 should use > llcc_v1_reg_offset since the LLCC version starts from v1.0.0 and SM8450 should > use llcc_v2_1_reg_offset since it supports the LLCC reg offset that got changed > since v2.1.0. Thoughts? Ya sounds good, only exception is SM8350 which is v2.0 but will be using v1 in naming but I guess its OK. Thanks, Sai > Thanks, > Mani > >> So coming to your query now, all other SoCs except SM8450(which uses v2.1) are using LLCC v1.0 >> or v2.0, so it is valid to use the same logic as reg_offsets for edac_reg. >> >> Thanks, >> Sai >> >>> Thanks, >>> Mani >>> >>>> Version based is more applicable as multiple SoCs might use same LLCC versions and would reduce SoC specific data >>>> which would be needed for every SoC in case some newer LLCC comes out. I know you could just call sm8450_edac_reg >>>> for lets say sm8550 or so on to reduce duplication but that won't look good. >>>> >>>> >>>> Thanks, >>>> Sai
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index eecafeded56f..1aedbbb8e96f 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -104,6 +104,7 @@ struct qcom_llcc_config { int size; bool need_llcc_cfg; const u32 *reg_offset; + const struct llcc_edac_reg *edac_reg; }; enum llcc_reg_offset { @@ -252,6 +253,60 @@ static const struct llcc_slice_config sm8450_data[] = { {LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, }; +static const struct llcc_edac_reg common_edac_reg = { + .trp_ecc_error_status0 = 0x20344, + .trp_ecc_error_status1 = 0x20348, + .trp_ecc_sb_err_syn0 = 0x2304c, + .trp_ecc_db_err_syn0 = 0x20370, + .trp_ecc_error_cntr_clear = 0x20440, + .trp_interrupt_0_status = 0x20480, + .trp_interrupt_0_clear = 0x20484, + .trp_interrupt_0_enable = 0x20488, + + /* LLCC Common registers */ + .cmn_status0 = 0x3000c, + .cmn_interrupt_0_enable = 0x3001c, + .cmn_interrupt_2_enable = 0x3003c, + + /* LLCC DRP registers */ + .drp_ecc_error_cfg = 0x40000, + .drp_ecc_error_cntr_clear = 0x40004, + .drp_interrupt_status = 0x41000, + .drp_interrupt_clear = 0x41008, + .drp_interrupt_enable = 0x4100c, + .drp_ecc_error_status0 = 0x42044, + .drp_ecc_error_status1 = 0x42048, + .drp_ecc_sb_err_syn0 = 0x4204c, + .drp_ecc_db_err_syn0 = 0x42070, +}; + +static const struct llcc_edac_reg sm8450_edac_reg = { + .trp_ecc_error_status0 = 0x20344, + .trp_ecc_error_status1 = 0x20348, + .trp_ecc_sb_err_syn0 = 0x2034c, + .trp_ecc_db_err_syn0 = 0x20370, + .trp_ecc_error_cntr_clear = 0x20440, + .trp_interrupt_0_status = 0x20480, + .trp_interrupt_0_clear = 0x20484, + .trp_interrupt_0_enable = 0x20488, + + /* LLCC Common registers */ + .cmn_status0 = 0x3400c, + .cmn_interrupt_0_enable = 0x3401c, + .cmn_interrupt_2_enable = 0x3403c, + + /* LLCC DRP registers */ + .drp_ecc_error_cfg = 0x50000, + .drp_ecc_error_cntr_clear = 0x50004, + .drp_interrupt_status = 0x50020, + .drp_interrupt_clear = 0x50028, + .drp_interrupt_enable = 0x5002c, + .drp_ecc_error_status0 = 0x520f4, + .drp_ecc_error_status1 = 0x520f8, + .drp_ecc_sb_err_syn0 = 0x520fc, + .drp_ecc_db_err_syn0 = 0x52120, +}; + static const u32 llcc_v1_2_reg_offset[] = { [LLCC_COMMON_HW_INFO] = 0x00030000, [LLCC_COMMON_STATUS0] = 0x0003000c, @@ -267,6 +322,7 @@ static const struct qcom_llcc_config sc7180_cfg = { .size = ARRAY_SIZE(sc7180_data), .need_llcc_cfg = true, .reg_offset = llcc_v1_2_reg_offset, + .edac_reg = &common_edac_reg, }; static const struct qcom_llcc_config sc7280_cfg = { @@ -274,6 +330,7 @@ static const struct qcom_llcc_config sc7280_cfg = { .size = ARRAY_SIZE(sc7280_data), .need_llcc_cfg = true, .reg_offset = llcc_v1_2_reg_offset, + .edac_reg = &common_edac_reg, }; static const struct qcom_llcc_config sdm845_cfg = { @@ -281,6 +338,7 @@ static const struct qcom_llcc_config sdm845_cfg = { .size = ARRAY_SIZE(sdm845_data), .need_llcc_cfg = false, .reg_offset = llcc_v1_2_reg_offset, + .edac_reg = &common_edac_reg, }; static const struct qcom_llcc_config sm6350_cfg = { @@ -288,6 +346,7 @@ static const struct qcom_llcc_config sm6350_cfg = { .size = ARRAY_SIZE(sm6350_data), .need_llcc_cfg = true, .reg_offset = llcc_v1_2_reg_offset, + .edac_reg = &common_edac_reg, }; static const struct qcom_llcc_config sm8150_cfg = { @@ -295,6 +354,7 @@ static const struct qcom_llcc_config sm8150_cfg = { .size = ARRAY_SIZE(sm8150_data), .need_llcc_cfg = true, .reg_offset = llcc_v1_2_reg_offset, + .edac_reg = &common_edac_reg, }; static const struct qcom_llcc_config sm8250_cfg = { @@ -302,6 +362,7 @@ static const struct qcom_llcc_config sm8250_cfg = { .size = ARRAY_SIZE(sm8250_data), .need_llcc_cfg = true, .reg_offset = llcc_v1_2_reg_offset, + .edac_reg = &common_edac_reg, }; static const struct qcom_llcc_config sm8350_cfg = { @@ -309,6 +370,7 @@ static const struct qcom_llcc_config sm8350_cfg = { .size = ARRAY_SIZE(sm8350_data), .need_llcc_cfg = true, .reg_offset = llcc_v1_2_reg_offset, + .edac_reg = &common_edac_reg, }; static const struct qcom_llcc_config sm8450_cfg = { @@ -316,6 +378,7 @@ static const struct qcom_llcc_config sm8450_cfg = { .size = ARRAY_SIZE(sm8450_data), .need_llcc_cfg = true, .reg_offset = llcc_v21_reg_offset, + .edac_reg = &sm8450_edac_reg, }; static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; @@ -716,6 +779,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->cfg = llcc_cfg; drv_data->cfg_size = sz; + drv_data->edac_reg = cfg->edac_reg; mutex_init(&drv_data->lock); platform_set_drvdata(pdev, drv_data);
The LLCC EDAC register offsets varies between each SoCs. Until now, the EDAC driver used the hardcoded register offsets. But this caused crash on SM8450 SoC where the register offsets has been changed. So to avoid this crash and also to make it easy to accomodate changes for new SoCs, let's pass the SoC specific register offsets to the EDAC driver. Currently, two set of offsets are used. One is SM8450 specific and another one is common to all SoCs. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/soc/qcom/llcc-qcom.c | 64 ++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+)