diff mbox

[v7,0/4] PCI EP driver support MSI doorbell from host

Message ID 20220822155130.2491006-1-Frank.Li@nxp.com
State Superseded
Headers show

Commit Message

Frank Li Aug. 22, 2022, 3:51 p.m. UTC 
┌───────┐          ┌──────────┐
                  │       │          │          │
┌─────────────┐   │       │          │ PCI Host │
│ MSI         │◄┐ │       │          │          │
│ Controller  │ │ │       │          │          │
└─────────────┘ └─┼───────┼──────────┼─Bar0     │
                  │ PCI   │          │ Bar1     │
                  │ Func  │          │ Bar2     │
                  │       │          │ Bar3     │
                  │       │          │ Bar4     │
                  │       ├─────────►│          │
                  └───────┘          └──────────┘

Many PCI controllers provided Endpoint functions.
Generally PCI endpoint is hardware, which is not running a rich OS,
like linux.

But Linux also supports endpoint functions.  PCI Host write BAR<n> space
like write to memory. The EP side can't know memory changed by the Host
driver. 

PCI Spec has not defined a standard method to do that.  Only define
MSI(x) to let EP notified RC status change. 

The basic idea is to trigger an IRQ when PCI RC writes to a memory
address. That's what MSI controller provided.  EP drivers just need to
request a platform MSI interrupt, struct MSI_msg *msg will pass down a
memory address and data.  EP driver will map such memory address to
one of PCI BAR<n>.  Host just writes such an address to trigger EP side
IRQ.

If system have gic-its, only need update PCI EP side driver. But i.MX
have not chip support gic-its yet. So we have to use MU to simulate a
MSI controller. Although only 4 MSI IRQs are simulated, it matched
vntb(pci-epf-vntb) network requirement.

After enable MSI, ping delay reduce < 1ms from ~8ms

IRQchip: imx mu worked as MSI controller: 
     let imx mu worked as MSI controllers. Although IP is not design
as MSI controller, we still can use it if limited IRQ number to 4.

pcie: endpoint: pci-epf-vntb: add endpoint MSI support
	 Based on ntb-next branch. https://github.com/jonmason/ntb/commits/ntb-next
	 Using MSI as door bell registers
	 This patch is totally independent on previous on. It can be
applied to ntb-next seperately.

i.MX EP function driver is upstreaming by Richard Zhu.
Some dts change missed at this patches. below is reference dts change

  Fine tuning commit message
  Fixed issues, reviewed by Bjorn Helgaas

- Change from v5 to v6
  Fixed build error found by kernel test robot

- Change from v4 to v5
  Fixed dt-binding document
        add msi-cell
        add interrupt max number
	update naming reg-names and power-domain-names.
  Fixed irqchip-Add-IMX-MU-MSI-controller-driver.patch
        rework commit message
        remove some field in struct imx_mu_dcfg
	error handle when link power domain failure.
	add irq_domain_update_bus_token

- Change from v3 to v4
  Fixed dt-binding document according to Krzysztof Kozlowski's feedback
  Fixed irqchip-imx-mu-worked-as-msi-controller according to Marc Zyngier's
        comments.

	There are still two important points, which I am not sure.
	1. clean irq_set_affinity after platform_msi_create_irq_domain.
	   Some function, like platform_msi_write_msg() is static.
	   so I have to set MSI_FLAG_USE_DEF_CHIP_OPS flags, which will
	   set irq_set_affinity to default one.
	2. about comments

	> +	msi_data->msi_domain = platform_msi_create_irq_domain(
	> +				of_node_to_fwnode(msi_data->pdev->dev.of_node),
	> +				&imx_mu_msi_domain_info,
	> +				msi_data->parent);

	"And you don't get an error due to the fact that you use the same
	fwnode for both domains without overriding the domain bus token?"

 	I did not understand yet. 

  Fixed static check warning, reported by Dan Carpenter
	pcie: endpoint: pci-epf-vntb: add endpoint MSI support

- Change from v2 to v3
  Fixed dt-binding docment check failure
  Fixed typo a cover letter.
  Change according Bjorn's comments at patch 
	pcie: endpoint: pci-epf-vntb: add endpoint MSI support
	 

- from V1 to V2
  Fixed fsl,mu-msi.yaml's problem
  Fixed irq-imx-mu-msi.c problem according Marc Zyngier's feeback 
  Added a new patch to allow pass down .pm by IRQCHIP_PLATFORM_DRIVER_END

Comments

Frank Li Aug. 25, 2022, 9:42 p.m. UTC | #1 
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Thursday, August 25, 2022 4:22 PM
> To: Frank Li <frank.li@nxp.com>
> Cc: maz@kernel.org; tglx@linutronix.de; krzysztof.kozlowski+dt@linaro.org;
> shawnguo@kernel.org; s.hauer@pengutronix.de; kw@linux.com;
> bhelgaas@google.com; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> pci@vger.kernel.org; Peng Fan <peng.fan@nxp.com>; Aisheng Dong
> <aisheng.dong@nxp.com>; jdmason@kudzu.us; kernel@pengutronix.de;
> festevam@gmail.com; dl-linux-imx <linux-imx@nxp.com>; kishon@ti.com;
> lorenzo.pieralisi@arm.com; ntb@lists.linux.dev; lznuaa@gmail.com
> Subject: [EXT] Re: [PATCH v7 3/4] dt-bindings: irqchip: imx mu work as msi
> controller
> 
> Caution: EXT Email
> 
> On Mon, Aug 22, 2022 at 10:51:29AM -0500, Frank Li wrote:
> > I.MX mu support generate irq by write a register. Provide msi controller
> > support so other driver such as PCI EP can use it by standard msi
> > interface as doorbell.
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  .../interrupt-controller/fsl,mu-msi.yaml      | 98 +++++++++++++++++++
> >  1 file changed, 98 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/interrupt-
> controller/fsl,mu-msi.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-
> msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-
> msi.yaml
> > new file mode 100644
> > index 0000000000000..ac07b138e24c0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-
> msi.yaml
> > @@ -0,0 +1,98 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicet
> ree.org%2Fschemas%2Finterrupt-controller%2Ffsl%2Cmu-
> msi.yaml%23&amp;data=05%7C01%7CFrank.Li%40nxp.com%7Cbff8f186128d
> 44209f4108da86dfc975%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> %7C637970592959950791%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLj
> AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%
> 7C%7C&amp;sdata=DHCOhmaJAhwb8Gl%2FEbPj32B6lR2zcIvyMY%2BTuPACb
> zI%3D&amp;reserved=0
> > +$schema:
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicet
> ree.org%2Fmeta-
> schemas%2Fcore.yaml%23&amp;data=05%7C01%7CFrank.Li%40nxp.com%7
> Cbff8f186128d44209f4108da86dfc975%7C686ea1d3bc2b4c6fa92cd99c5c3016
> 35%7C0%7C0%7C637970592959950791%7CUnknown%7CTWFpbGZsb3d8eyJ
> WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> 7C3000%7C%7C%7C&amp;sdata=J4znEXyHnMyQOssSUsoxE2Mlhe2qCDC%2F
> 9WN6SKv69aM%3D&amp;reserved=0
> > +
> > +title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
> > +
> > +maintainers:
> > +  - Frank Li <Frank.Li@nxp.com>
> > +
> > +description: |
> > +  The Messaging Unit module enables two processors within the SoC to
> > +  communicate and coordinate by passing messages (e.g. data, status
> > +  and control) through the MU interface. The MU also provides the ability
> > +  for one processor (A side) to signal the other processor (B side) using
> > +  interrupts.
> > +
> > +  Because the MU manages the messaging between processors, the MU
> uses
> > +  different clocks (from each side of the different peripheral buses).
> > +  Therefore, the MU must synchronize the accesses from one side to the
> > +  other. The MU accomplishes synchronization using two sets of matching
> > +  registers (Processor A-facing, Processor B-facing).
> > +
> > +  MU can work as msi interrupt controller to do doorbell
> > +
> > +allOf:
> > +  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - fsl,imx6sx-mu-msi
> > +      - fsl,imx7ulp-mu-msi
> > +      - fsl,imx8ulp-mu-msi
> > +      - fsl,imx8ulp-mu-msi-s4
> > +
> > +  reg:
> > +    items:
> > +      - description: a side register base address
> > +      - description: b side register base address
> > +
> > +  reg-names:
> > +    items:
> > +      - const: processor a-facing
> > +      - const: processor b-facing
> 
> Isn't 'a' and 'b' sufficient to distinguish? Personally, doesn't really
> look like a case that benefits from -names at all.
> 
> In any case, -names shouldn't have spaces.

I like "a" and "b".

But Marc Zyngier suggested use above name.
https://www.spinics.net/lists/linux-pci/msg128783.html

@Marc Zyngier

best regards
Frank Li

> 
> > +
> > +  interrupts:
> > +    description: a side interrupt number.
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    items:
> > +      - description: a side power domain
> > +      - description: b side power domain
> > +
> > +  power-domain-names:
> > +    items:
> > +      - const: processor a-facing
> > +      - const: processor b-facing
> 
> Same here.
> 
> > +
> > +  interrupt-controller: true
> > +
> > +  msi-controller: true
> > +
> > +  "#msi-cells":
> > +    const: 0
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - interrupt-controller
> > +  - msi-controller
> 
> #msi-cells should be required.
> 
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/firmware/imx/rsrc.h>
> > +
> > +    msi-controller@5d270000 {
> > +        compatible = "fsl,imx6sx-mu-msi";
> > +        msi-controller;
> > +        #msi-cells = <0>;
> > +        interrupt-controller;
> > +        reg = <0x5d270000 0x10000>,     /* A side */
> > +              <0x5d300000 0x10000>;     /* B side */
> > +        reg-names = "processor a-facing", "processor b-facing";
> > +        interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
> > +        power-domains = <&pd IMX_SC_R_MU_12A>,
> > +                        <&pd IMX_SC_R_MU_12B>;
> > +        power-domain-names = "processor a-facing", "processor b-facing";
> > +    };
> > --
> > 2.35.1
> >
> >
Frank Li Aug. 26, 2022, 6:59 p.m. UTC | #2 
> -----Original Message-----
> From: Marc Zyngier <maz@kernel.org>
> Sent: Friday, August 26, 2022 1:35 PM
> To: Frank Li <frank.li@nxp.com>
> Cc: Rob Herring <robh@kernel.org>; tglx@linutronix.de;
> krzysztof.kozlowski+dt@linaro.org; shawnguo@kernel.org;
> s.hauer@pengutronix.de; kw@linux.com; bhelgaas@google.com; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-pci@vger.kernel.org; Peng Fan
> <peng.fan@nxp.com>; Aisheng Dong <aisheng.dong@nxp.com>;
> jdmason@kudzu.us; kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx
> <linux-imx@nxp.com>; kishon@ti.com; lorenzo.pieralisi@arm.com;
> ntb@lists.linux.dev; lznuaa@gmail.com
> Subject: Re: [EXT] Re: [PATCH v7 3/4] dt-bindings: irqchip: imx mu work as msi
> controller
> 
> Caution: EXT Email
> 
> On Thu, 25 Aug 2022 22:42:38 +0100,
> Frank Li <frank.li@nxp.com> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Rob Herring <robh@kernel.org>
> > > Sent: Thursday, August 25, 2022 4:22 PM
> > > To: Frank Li <frank.li@nxp.com>
> > > Cc: maz@kernel.org; tglx@linutronix.de; krzysztof.kozlowski+dt@linaro.org;
> > > shawnguo@kernel.org; s.hauer@pengutronix.de; kw@linux.com;
> > > bhelgaas@google.com; linux-kernel@vger.kernel.org;
> > > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> > > pci@vger.kernel.org; Peng Fan <peng.fan@nxp.com>; Aisheng Dong
> > > <aisheng.dong@nxp.com>; jdmason@kudzu.us; kernel@pengutronix.de;
> > > festevam@gmail.com; dl-linux-imx <linux-imx@nxp.com>; kishon@ti.com;
> > > lorenzo.pieralisi@arm.com; ntb@lists.linux.dev; lznuaa@gmail.com
> > > Subject: [EXT] Re: [PATCH v7 3/4] dt-bindings: irqchip: imx mu work as msi
> > > controller
> > >
> > > Caution: EXT Email
> > >
> > > On Mon, Aug 22, 2022 at 10:51:29AM -0500, Frank Li wrote:
> > > > I.MX mu support generate irq by write a register. Provide msi controller
> > > > support so other driver such as PCI EP can use it by standard msi
> > > > interface as doorbell.
> > > >
> > > > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > > > ---
> > > >  .../interrupt-controller/fsl,mu-msi.yaml      | 98 +++++++++++++++++++
> > > >  1 file changed, 98 insertions(+)
> > > >  create mode 100644 Documentation/devicetree/bindings/interrupt-
> > > controller/fsl,mu-msi.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/interrupt-
> controller/fsl,mu-
> > > msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-
> > > msi.yaml
> > > > new file mode 100644
> > > > index 0000000000000..ac07b138e24c0
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-
> > > msi.yaml
> > > > @@ -0,0 +1,98 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id:
> > >
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicet
> > > ree.org%2Fschemas%2Finterrupt-controller%2Ffsl%2Cmu-
> > > msi.yaml%23&amp;data=05%7C01%7CFrank.Li%40nxp.com%7Cbff8f186128d
> > > 44209f4108da86dfc975%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> > > %7C637970592959950791%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLj
> > > AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%
> > > 7C%7C&amp;sdata=DHCOhmaJAhwb8Gl%2FEbPj32B6lR2zcIvyMY%2BTuPACb
> > > zI%3D&amp;reserved=0
> > > > +$schema:
> > >
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicet
> > > ree.org%2Fmeta-
> > > schemas%2Fcore.yaml%23&amp;data=05%7C01%7CFrank.Li%40nxp.com%7
> > > Cbff8f186128d44209f4108da86dfc975%7C686ea1d3bc2b4c6fa92cd99c5c3016
> > > 35%7C0%7C0%7C637970592959950791%7CUnknown%7CTWFpbGZsb3d8eyJ
> > > WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> > > 7C3000%7C%7C%7C&amp;sdata=J4znEXyHnMyQOssSUsoxE2Mlhe2qCDC%2F
> > > 9WN6SKv69aM%3D&amp;reserved=0
> > > > +
> > > > +title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
> > > > +
> > > > +maintainers:
> > > > +  - Frank Li <Frank.Li@nxp.com>
> > > > +
> > > > +description: |
> > > > +  The Messaging Unit module enables two processors within the SoC to
> > > > +  communicate and coordinate by passing messages (e.g. data, status
> > > > +  and control) through the MU interface. The MU also provides the ability
> > > > +  for one processor (A side) to signal the other processor (B side) using
> > > > +  interrupts.
> > > > +
> > > > +  Because the MU manages the messaging between processors, the MU
> > > uses
> > > > +  different clocks (from each side of the different peripheral buses).
> > > > +  Therefore, the MU must synchronize the accesses from one side to the
> > > > +  other. The MU accomplishes synchronization using two sets of matching
> > > > +  registers (Processor A-facing, Processor B-facing).
> > > > +
> > > > +  MU can work as msi interrupt controller to do doorbell
> > > > +
> > > > +allOf:
> > > > +  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
> > > > +
> > > > +properties:
> > > > +  compatible:
> > > > +    enum:
> > > > +      - fsl,imx6sx-mu-msi
> > > > +      - fsl,imx7ulp-mu-msi
> > > > +      - fsl,imx8ulp-mu-msi
> > > > +      - fsl,imx8ulp-mu-msi-s4
> > > > +
> > > > +  reg:
> > > > +    items:
> > > > +      - description: a side register base address
> > > > +      - description: b side register base address
> > > > +
> > > > +  reg-names:
> > > > +    items:
> > > > +      - const: processor a-facing
> > > > +      - const: processor b-facing
> > >
> > > Isn't 'a' and 'b' sufficient to distinguish? Personally, doesn't really
> > > look like a case that benefits from -names at all.
> > >
> > > In any case, -names shouldn't have spaces.
> >
> > I like "a" and "b".
> >
> > But Marc Zyngier suggested use above name.
> >
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.spi
> nics.net%2Flists%2Flinux-
> pci%2Fmsg128783.html&amp;data=05%7C01%7Cfrank.li%40nxp.com%7Cadd154d
> 4aeda4059c93408da8791ba1b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> %7C637971357205475355%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwM
> DAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&a
> mp;sdata=vuaoWvu8BYcJ5NjOoUfFhlykBsW8vC2%2FbsrBmfx%2Bfz8%3D&amp;r
> eserved=0
> >
> > @Marc Zyngier
> 
> And I stand by my initial request. "a" doesn't convey any sort of
> useful information. Why not "I" and "II", while we're at it? Or
> something even funkier?

MU spec use term "a" and "b",  user have to map "I" an "II" to 
"a" and "b" when read MU spec and code. it is not straightforward.

I quote a part of spec. 
" The MU is connected as a peripheral under the Peripheral bus on both sides-on
the Processor A-side, the Processor A Peripheral Bus, and on the Processor B side,
the Processor B Peripheral Bus."

Rob Herring and Marc Zynginer:
I can change to any name, which you agree both. 

Some options:
1. "a", "b"
2. "a-side", "b-side"
3. "a-facing", "b-facing"
4. "I", "II"

> 
>         M.
> 
> --
> Without deviation from the norm, progress is not possible.
Frank Li Aug. 29, 2022, 2:47 p.m. UTC | #3 
> -----Original Message-----
> From: Marc Zyngier <maz@kernel.org>
> Sent: Friday, August 26, 2022 4:45 PM
> To: Frank Li <frank.li@nxp.com>
> Cc: Rob Herring <robh@kernel.org>; tglx@linutronix.de;
> krzysztof.kozlowski+dt@linaro.org; shawnguo@kernel.org;
> s.hauer@pengutronix.de; kw@linux.com; bhelgaas@google.com; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-pci@vger.kernel.org; Peng Fan
> <peng.fan@nxp.com>; Aisheng Dong <aisheng.dong@nxp.com>;
> jdmason@kudzu.us; kernel@pengutronix.de; festevam@gmail.com; dl-linux-
> imx <linux-imx@nxp.com>; kishon@ti.com; lorenzo.pieralisi@arm.com;
> ntb@lists.linux.dev; lznuaa@gmail.com
> Subject: Re: [EXT] Re: [PATCH v7 3/4] dt-bindings: irqchip: imx mu work as
> msi controller
> 
> Caution: EXT Email
> 
> On Fri, 26 Aug 2022 19:59:44 +0100,
> Frank Li <frank.li@nxp.com> wrote:
> >
> > > And I stand by my initial request. "a" doesn't convey any sort of
> > > useful information. Why not "I" and "II", while we're at it? Or
> > > something even funkier?
> >
> > MU spec use term "a" and "b",  user have to map "I" an "II" to
> > "a" and "b" when read MU spec and code. it is not straightforward.
> >
> > I quote a part of spec.
> > " The MU is connected as a peripheral under the Peripheral bus on both
> sides-on
> > the Processor A-side, the Processor A Peripheral Bus, and on the Processor
> B side,
> > the Processor B Peripheral Bus."
> >
> > Rob Herring and Marc Zynginer:
> > I can change to any name, which you agree both.
> >
> > Some options:
> > 1. "a", "b"
> > 2. "a-side", "b-side"
> > 3. "a-facing", "b-facing"
> > 4. "I", "II"
> 
> Use the wording indicated in the spec: "processor-a-side", and
> "processor-b-side". This is what I asked the first place.

@Rob Herring:  Do you agree this name?

[Frank Li] 

> 
>         M.
> 
> --
> Without deviation from the norm, progress is not possible.
diff mbox

Patch

--- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
@@ -160,5 +160,6 @@  pcieb_ep: pcie_ep@5f010000 {
                num-ib-windows = <6>;
                num-ob-windows = <6>;
                status = "disabled";
+               MSI-parent = <&lsio_mu12>;
        };

--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -172,6 +172,19 @@  lsio_mu6: mailbox@5d210000 {
                status = "disabled";
        };

+       lsio_mu12: mailbox@5d270000 {
+               compatible = "fsl,imx6sx-mu-MSI";
+               msi-controller;
+               interrupt-controller;
+               reg = <0x5d270000 0x10000>,     /* A side */
+                     <0x5d300000 0x10000>;     /* B side */
+               reg-names = "a", "b";
+               interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&pd IMX_SC_R_MU_12A>,
+                               <&pd IMX_SC_R_MU_12B>;
+               power-domain-names = "a", "b";
+       };
+

Change Log
- Change from v6 to v7
  pcie: endpoint: add endpoint MSI support