Message ID | 20220825103216.4948-1-lucas.segarra.fernandez@intel.com |
---|---|
State | Accepted |
Commit | cc40b04c08400d86d2d6ea0159e0617e717f729c |
Headers | show |
Series | crypto: qat - fix default value of WDT timer | expand |
On Thu, Aug 25, 2022 at 12:32:16PM +0200, Lucas Segarra Fernandez wrote: > The QAT HW supports an hardware mechanism to detect an accelerator hang. > The reporting of a hang occurs after a watchdog timer (WDT) expires. > > The value of the WDT set previously was too small and was causing false > positives. > Change the default value of the WDT to 0x7000000ULL to avoid this. > > Fixes: 1c4d9d5bbb5a ("crypto: qat - enable detection of accelerators hang") > Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> > Signed-off-by: Lucas Segarra Fernandez <lucas.segarra.fernandez@intel.com> > --- > drivers/crypto/qat/qat_common/adf_gen4_hw_data.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Patch applied. Thanks.
diff --git a/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h b/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h index 43b8f864806b..4fb4b3df5a18 100644 --- a/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h +++ b/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h @@ -107,7 +107,7 @@ do { \ * Timeout is in cycles. Clock speed may vary across products but this * value should be a few milli-seconds. */ -#define ADF_SSM_WDT_DEFAULT_VALUE 0x200000 +#define ADF_SSM_WDT_DEFAULT_VALUE 0x7000000ULL #define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x8000000 #define ADF_SSMWDTL_OFFSET 0x54 #define ADF_SSMWDTH_OFFSET 0x5C