| Message ID | 20220910195659.11843-3-Sergey.Semin@baikalelectronics.ru |
|---|---|
| State | Accepted |
| Commit | 5514acb0dd030356e628cdd88b266efaa0a22315 |
| Headers | show |
| Series | EDAC/synopsys: Add generic resources and Baikal-T1 support | expand |
On Sat, Sep 10, 2022 at 10:56:46PM +0300, Serge Semin wrote: > First of all the DW uMCTL2 DDRC IP-core supports the individual IRQ lines > for each standard event: ECC Corrected Error, ECC Uncorrected Error, ECC > Address Protection, Scrubber-Done signal, DFI Parity/CRC Error. It's > possible that the platform engineers merge them up in the IRQ controller > level. So let's add both configuration support to the DT-schema. > > Secondly the DW uMCTL2 DDRC IP-core can have clock sources like APB > reference clock, AXI-ports clock, main DDRC core reference clock and > Scrubber low-power clock. In addition to that each clock domain can have a > dedicated reset signal. Let's add the properties for at least the denoted > clock sources and the corresponding reset controls. > > Note the IRQs and the phandles order is deliberately not fixed since some > of the sources may be absent depending on the IP-core synthesize > parameters and the particular platform setups. > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > > --- > > Changelog v2: > - Replace "snps,ddrc-3.80a" compatible string with "snps,dw-umctl2-ddrc" > in the example. > - Move unrelated changes in to the dedicated patches. (@Krzysztof) > - Use the IRQ macros in the example. (@Krzysztof) > --- > .../snps,dw-umctl2-ddrc.yaml | 61 ++++++++++++++++++- > 1 file changed, 60 insertions(+), 1 deletion(-) Reviewed-by: Rob Herring <robh@kernel.org>
On Sat, 10 Sep 2022 22:56:46 +0300, Serge Semin wrote: > First of all the DW uMCTL2 DDRC IP-core supports the individual IRQ lines > for each standard event: ECC Corrected Error, ECC Uncorrected Error, ECC > Address Protection, Scrubber-Done signal, DFI Parity/CRC Error. It's > possible that the platform engineers merge them up in the IRQ controller > level. So let's add both configuration support to the DT-schema. > > Secondly the DW uMCTL2 DDRC IP-core can have clock sources like APB > reference clock, AXI-ports clock, main DDRC core reference clock and > Scrubber low-power clock. In addition to that each clock domain can have a > dedicated reset signal. Let's add the properties for at least the denoted > clock sources and the corresponding reset controls. > > [...] Applied, thanks! [02/15] dt-bindings: memory: snps: Extend schema with IRQs/resets/clocks props https://git.kernel.org/krzk/linux-mem-ctrl/c/5514acb0dd030356e628cdd88b266efaa0a22315 Best regards,
diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml index fb571d3d665d..e68c4306025a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml @@ -33,11 +33,55 @@ properties: const: xlnx,zynqmp-ddrc-2.40a interrupts: - maxItems: 1 + description: + DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":" + ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection, + Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the + signals merged before they reach the IRQ controller or have some of them + absent in case if the corresponding feature is unavailable/disabled. + minItems: 1 + maxItems: 5 + + interrupt-names: + minItems: 1 + maxItems: 5 + oneOf: + - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ + items: + - const: ecc + - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs + items: + enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ] reg: maxItems: 1 + clocks: + description: + A standard set of the clock sources contains CSRs bus clock, AXI-ports + reference clock, DDRC core clock, Scrubber standalone clock + (synchronous to the DDRC clock). + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + items: + enum: [ pclk, aclk, core, sbr ] + + resets: + description: + Each clock domain can have separate reset signal. + minItems: 1 + maxItems: 4 + + reset-names: + minItems: 1 + maxItems: 4 + items: + enum: [ prst, arst, core, sbr ] + required: - compatible - reg @@ -55,5 +99,20 @@ examples: interrupt-parent = <&gic>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ecc"; + }; + - | + #include <dt-bindings/interrupt-controller/irq.h> + + memory-controller@3d400000 { + compatible = "snps,dw-umctl2-ddrc"; + reg = <0x3d400000 0x400000>; + + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>, <148 IRQ_TYPE_LEVEL_HIGH>, + <149 IRQ_TYPE_LEVEL_HIGH>, <150 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ecc_ce", "ecc_ue", "ecc_sbr", "dfi_e"; + + clocks = <&pclk>, <&aclk>, <&core_clk>, <&sbr_clk>; + clock-names = "pclk", "aclk", "core", "sbr"; }; ...
First of all the DW uMCTL2 DDRC IP-core supports the individual IRQ lines for each standard event: ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection, Scrubber-Done signal, DFI Parity/CRC Error. It's possible that the platform engineers merge them up in the IRQ controller level. So let's add both configuration support to the DT-schema. Secondly the DW uMCTL2 DDRC IP-core can have clock sources like APB reference clock, AXI-ports clock, main DDRC core reference clock and Scrubber low-power clock. In addition to that each clock domain can have a dedicated reset signal. Let's add the properties for at least the denoted clock sources and the corresponding reset controls. Note the IRQs and the phandles order is deliberately not fixed since some of the sources may be absent depending on the IP-core synthesize parameters and the particular platform setups. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- Changelog v2: - Replace "snps,ddrc-3.80a" compatible string with "snps,dw-umctl2-ddrc" in the example. - Move unrelated changes in to the dedicated patches. (@Krzysztof) - Use the IRQ macros in the example. (@Krzysztof) --- .../snps,dw-umctl2-ddrc.yaml | 61 ++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-)