diff mbox series

[v4,2/2] arm64: dts: mt8192: Add vcodec lat and core nodes

Message ID 20220930112237.14411-3-allen-kh.cheng@mediatek.com
State Superseded
Headers show
Series [v4,1/2] media: dt-bindings: mediatek: Rename child node names for decoder | expand

Commit Message

Allen-KH Cheng Sept. 30, 2022, 11:22 a.m. UTC 
Add vcodec lat and core nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

Comments

Allen-KH Cheng Nov. 21, 2022, 12:30 p.m. UTC | #1 
Hi Nícolas,

On Fri, 2022-11-18 at 09:10 -0500, Nícolas F. R. A. Prado wrote:
> On Fri, Sep 30, 2022 at 07:22:37PM +0800, Allen-KH Cheng wrote:
> > Add vcodec lat and core nodes for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Tested-by: Chen-Yu Tsai <wenst@chromium.org>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60
> > ++++++++++++++++++++++++
> >  1 file changed, 60 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 6b20376191a7..92a20f87468b 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1449,6 +1449,66 @@
> >  			power-domains = <&spm
> > MT8192_POWER_DOMAIN_ISP2>;
> >  		};
> >  
> > +		vcodec_dec: video-codec@16000000 {
> > +			compatible = "mediatek,mt8192-vcodec-dec";
> > +			reg = <0 0x16000000 0 0x1000>;
> > +			mediatek,scp = <&scp>;
> > +			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > +			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0
> > 0xfff00000>;
> 
> Hi,
> 
> since commit 951d48855d86 ("of: Make of_dma_get_range() work on bus
> nodes") [1]
> was merged this no longer works as is. Running the fluster codec
> tests results
> in IOMMU faults:
> 
> 	[  386.233976] mtk-iommu 1401d000.m4u: fault type=0x280
> iova=0x1fcdc0000 pa=0x0 master=0x500041c(larb=4 port=7) layer=0 read
> 	[  386.250666] mtk_vdec_worker(),241:
> [MTK_V4L2][ERROR]  <===[138], src_buf[0] sz=0x298 pts=0
> vdec_if_decode() ret=1 res_chg=0===>
> 
> The issue is that the DMA configuration supplied by dma-ranges is now
> looked for
> in the parent node, so the vcodec_dec node no longer gets the
> configuration it
> expected.
> 
> That said, given that the node already uses the IOMMU for the address
> translations (iommus property), there shouldn't even be a dma-ranges
> property.
> Indeed simply removing the dma-ranges property from this node fixes
> the issue
> and gets the decoder working again.
> 
> Thanks,
> Nícolas
> 
> [1] 
> https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f1ad5338a4d57fe1fe6475003acb8c70bf9d1bdf__;!!CTRNKA9wMg0ARbw!xdhhnvXMY5-BjI2BXPHQI-Hw8zgtZ1lvFyFFv7KtNuCDxW17VC7RqAaW9B_uXsQucT1sLk_DUl-c99ijF9dF8QXbJQ$
>  

Noted!

The paret node should be

vcodec_dec: video-codec@16000000 {
	compatible = "mediatek,mt8192-vcodec-dec";
	reg = <0 0x16000000 0 0x1000>;
	mediatek,scp = <&scp>;
	iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0 0 0 0x16000000 0 0x26000>;
	
	video-codec-lat@10000 {
...

}

Am I right?

Thanks,
Allen

> 
> > +			#address-cells = <2>;
> > +			#size-cells = <2>;
> > +			ranges = <0 0 0 0x16000000 0 0x26000>;
> > +
> > +			video-codec-lat@10000 {
> > +				compatible = "mediatek,mtk-vcodec-lat";
> > +				reg = <0x0 0x10000 0 0x800>;
> > +				interrupts = <GIC_SPI 426
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > +				iommus = <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > +					 <&vdecsys_soc
> > CLK_VDEC_SOC_VDEC>,
> > +					 <&vdecsys_soc
> > CLK_VDEC_SOC_LAT>,
> > +					 <&vdecsys_soc
> > CLK_VDEC_SOC_LARB1>,
> > +					 <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > +				clock-names = "sel", "soc-vdec", "soc-
> > lat", "vdec", "top";
> > +				assigned-clocks = <&topckgen
> > CLK_TOP_VDEC_SEL>;
> > +				assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > +				power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC>;
> > +			};
> > +
> > +			video-codec-core@25000 {
> > +				compatible = "mediatek,mtk-vcodec-
> > core";
> > +				reg = <0 0x25000 0 0x1000>;
> > +				interrupts = <GIC_SPI 425
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > +				iommus = <&iommu0
> > M4U_PORT_L4_VDEC_MC_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_UFO_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_PP_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_TILE_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_VLD_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_VLD2_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > +					 <&vdecsys CLK_VDEC_VDEC>,
> > +					 <&vdecsys CLK_VDEC_LAT>,
> > +					 <&vdecsys CLK_VDEC_LARB1>,
> > +					 <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > +				clock-names = "sel", "soc-vdec", "soc-
> > lat", "vdec", "top";
> > +				assigned-clocks = <&topckgen
> > CLK_TOP_VDEC_SEL>;
> > +				assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > +				power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC2>;
> > +			};
> > +		};
> > +
Nícolas F. R. A. Prado Nov. 21, 2022, 2:23 p.m. UTC | #2 
On Mon, Nov 21, 2022 at 12:30:37PM +0000, Allen-KH Cheng (程冠勳) wrote:
> Hi Nícolas,
> 
> On Fri, 2022-11-18 at 09:10 -0500, Nícolas F. R. A. Prado wrote:
> > On Fri, Sep 30, 2022 at 07:22:37PM +0800, Allen-KH Cheng wrote:
> > > Add vcodec lat and core nodes for mt8192 SoC.
> > > 
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > Tested-by: Chen-Yu Tsai <wenst@chromium.org>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > ---
> > >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60
> > > ++++++++++++++++++++++++
> > >  1 file changed, 60 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 6b20376191a7..92a20f87468b 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -1449,6 +1449,66 @@
> > >  			power-domains = <&spm
> > > MT8192_POWER_DOMAIN_ISP2>;
> > >  		};
> > >  
> > > +		vcodec_dec: video-codec@16000000 {
> > > +			compatible = "mediatek,mt8192-vcodec-dec";
> > > +			reg = <0 0x16000000 0 0x1000>;
> > > +			mediatek,scp = <&scp>;
> > > +			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > > +			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0
> > > 0xfff00000>;
> > 
> > Hi,
> > 
> > since commit 951d48855d86 ("of: Make of_dma_get_range() work on bus
> > nodes") [1]
> > was merged this no longer works as is. Running the fluster codec
> > tests results
> > in IOMMU faults:
> > 
> > 	[  386.233976] mtk-iommu 1401d000.m4u: fault type=0x280
> > iova=0x1fcdc0000 pa=0x0 master=0x500041c(larb=4 port=7) layer=0 read
> > 	[  386.250666] mtk_vdec_worker(),241:
> > [MTK_V4L2][ERROR]  <===[138], src_buf[0] sz=0x298 pts=0
> > vdec_if_decode() ret=1 res_chg=0===>
> > 
> > The issue is that the DMA configuration supplied by dma-ranges is now
> > looked for
> > in the parent node, so the vcodec_dec node no longer gets the
> > configuration it
> > expected.
> > 
> > That said, given that the node already uses the IOMMU for the address
> > translations (iommus property), there shouldn't even be a dma-ranges
> > property.
> > Indeed simply removing the dma-ranges property from this node fixes
> > the issue
> > and gets the decoder working again.
> > 
> > Thanks,
> > Nícolas
> > 
> > [1] 
> > https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f1ad5338a4d57fe1fe6475003acb8c70bf9d1bdf__;!!CTRNKA9wMg0ARbw!xdhhnvXMY5-BjI2BXPHQI-Hw8zgtZ1lvFyFFv7KtNuCDxW17VC7RqAaW9B_uXsQucT1sLk_DUl-c99ijF9dF8QXbJQ$
> >  
> 
> Noted!
> 
> The paret node should be
> 
> vcodec_dec: video-codec@16000000 {
> 	compatible = "mediatek,mt8192-vcodec-dec";
> 	reg = <0 0x16000000 0 0x1000>;
> 	mediatek,scp = <&scp>;
> 	iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> 	#address-cells = <2>;
> 	#size-cells = <2>;
> 	ranges = <0 0 0 0x16000000 0 0x26000>;
> 	
> 	video-codec-lat@10000 {
> ...
> 
> }
> 
> Am I right?

Yes, that's right.

Thanks,
Nícolas
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6b20376191a7..92a20f87468b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1449,6 +1449,66 @@ 
 			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
 		};
 
+		vcodec_dec: video-codec@16000000 {
+			compatible = "mediatek,mt8192-vcodec-dec";
+			reg = <0 0x16000000 0 0x1000>;
+			mediatek,scp = <&scp>;
+			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0 0 0 0x16000000 0 0x26000>;
+
+			video-codec-lat@10000 {
+				compatible = "mediatek,mtk-vcodec-lat";
+				reg = <0x0 0x10000 0 0x800>;
+				interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+					 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+					 <&topckgen CLK_TOP_MAINPLL_D4>;
+				clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+			};
+
+			video-codec-core@25000 {
+				compatible = "mediatek,mtk-vcodec-core";
+				reg = <0 0x25000 0 0x1000>;
+				interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+					 <&vdecsys CLK_VDEC_VDEC>,
+					 <&vdecsys CLK_VDEC_LAT>,
+					 <&vdecsys CLK_VDEC_LARB1>,
+					 <&topckgen CLK_TOP_MAINPLL_D4>;
+				clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+			};
+		};
+
 		larb5: larb@1600d000 {
 			compatible = "mediatek,mt8192-smi-larb";
 			reg = <0 0x1600d000 0 0x1000>;