| Message ID | 20221216143717.1002015-3-eugen.hristev@microchip.com |
|---|---|
| State | New |
| Headers | show |
| Series | media: dwc: add csi2host driver | expand |
On Fri, Dec 16, 2022 at 04:37:15PM +0200, Eugen Hristev wrote: > From: Luis Oliveira <Luis.Oliveira@synopsys.com> > > Add device-tree bindings documentation for SNPS DesignWare MIPI D-PHY in > RX mode. > > Signed-off-by: Luis Oliveira <luis.oliveira@synopsys.com> > --- > .../bindings/phy/snps,dw-dphy-rx.txt | 29 +++++++++++++++++++ > 1 file changed, 29 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/snps,dw-dphy-rx.txt New bindings must be in schema format. Rob
On Fri, Dec 16, 2022 at 04:37:15PM +0200, Eugen Hristev wrote: > From: Luis Oliveira <Luis.Oliveira@synopsys.com> > > Add device-tree bindings documentation for SNPS DesignWare MIPI D-PHY in > RX mode. > > Signed-off-by: Luis Oliveira <luis.oliveira@synopsys.com> > --- > .../bindings/phy/snps,dw-dphy-rx.txt | 29 +++++++++++++++++++ > 1 file changed, 29 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/snps,dw-dphy-rx.txt > > diff --git a/Documentation/devicetree/bindings/phy/snps,dw-dphy-rx.txt b/Documentation/devicetree/bindings/phy/snps,dw-dphy-rx.txt > new file mode 100644 > index 000000000000..ffb64fe5cbd1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/snps,dw-dphy-rx.txt > @@ -0,0 +1,29 @@ > +Synopsys DesignWare MIPI Rx D-PHY block details > + > +Description > +----------- > + > +The Synopsys MIPI D-PHY controller supports MIPI-DPHY in receiver mode. > +Please refer to phy-bindings.txt for more information. > + > +Required properties: > +- compatible : Shall be "snps,dw-dphy-rx". > +- #phy-cells : Must be 1. There is more than 1 lane/phy for a single instance? > +- bus-width : Size of the test interface data bus (8 bits->8 or > + 12bits->12). Do we need a test interface upstream? If so, needs a vendor prefix. > +- snps,dphy-frequency : Frequency at which D-PHY should start, configurable. > + Check Synopsys databook. (-kHz) Is this frequency of the link? We have properties for that. Or this should somehow be using the clock binding. And anything with units should have a unit suffix as defined in property-units.yaml. > +- reg : Test interface register. This correspondes to the > + physical base address of the controller and size of > + the device memory mapped registers; Check Synopsys > + databook. > + > +Example: > + > + mipi_dphy_rx1: dphy@d00003040 { > + compatible = "snps,dw-dphy-rx"; > + #phy-cells = <1>; > + bus-width = <12>; > + snps,dphy-frequency = <300000>; > + reg = <0xd0003040 0x20>; > + }; > -- > 2.25.1 > >
diff --git a/Documentation/devicetree/bindings/phy/snps,dw-dphy-rx.txt b/Documentation/devicetree/bindings/phy/snps,dw-dphy-rx.txt new file mode 100644 index 000000000000..ffb64fe5cbd1 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/snps,dw-dphy-rx.txt @@ -0,0 +1,29 @@ +Synopsys DesignWare MIPI Rx D-PHY block details + +Description +----------- + +The Synopsys MIPI D-PHY controller supports MIPI-DPHY in receiver mode. +Please refer to phy-bindings.txt for more information. + +Required properties: +- compatible : Shall be "snps,dw-dphy-rx". +- #phy-cells : Must be 1. +- bus-width : Size of the test interface data bus (8 bits->8 or + 12bits->12). +- snps,dphy-frequency : Frequency at which D-PHY should start, configurable. + Check Synopsys databook. (-kHz) +- reg : Test interface register. This correspondes to the + physical base address of the controller and size of + the device memory mapped registers; Check Synopsys + databook. + +Example: + + mipi_dphy_rx1: dphy@d00003040 { + compatible = "snps,dw-dphy-rx"; + #phy-cells = <1>; + bus-width = <12>; + snps,dphy-frequency = <300000>; + reg = <0xd0003040 0x20>; + };