| Message ID | 20221027204720.33611-3-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/isa/piix4: Remove MIPS Malta specific bits | expand |
Am 27. Oktober 2022 20:47:19 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >Linux kernel expects the northbridge & southbridge chipsets >configured by the BIOS firmware. We emulate that by writing >a tiny bootloader code in write_bootloader(). > >Upon introduction in commit 5c2b87e34d ("PIIX4 support"), >the PIIX4 configuration space included values specific to >the Malta board. > >Set the Malta-specific IRQ routing values in the embedded >bootloader, so the next commit can remove the Malta specific >bits from the PIIX4 PCI-ISA bridge and make it generic >(matching the real hardware). > >Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >--- >FIXME: Missing the nanoMIPS counter-part! Who will be taking care of this? I have absolutely no clue how the write_bootloader functions work, so I don't see how to fix it. Couldn't we just do it like in pegasos2_init() where the registers are initialized by QEMU directly if there is no bootloader binary configured? I could do that. Best regards, Bernhard >--- > hw/mips/malta.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > >diff --git a/hw/mips/malta.c b/hw/mips/malta.c >index df0f448b67..4403028778 100644 >--- a/hw/mips/malta.c >+++ b/hw/mips/malta.c >@@ -804,6 +804,8 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, > stw_p(p++, 0x8422); stw_p(p++, 0x9088); > /* sw t0, 0x88(t1) */ > >+ /* TODO set PIIX IRQC[A:D] routing values! */ >+ > stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); > > stw_p(p++, NM_HI2(kernel_entry)); >@@ -841,6 +843,9 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, > static void write_bootloader(uint8_t *base, uint64_t run_addr, > uint64_t kernel_entry) > { >+ const char pci_pins_cfg[PCI_NUM_PINS] = { >+ 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ >+ }; > uint32_t *p; > > /* Small bootloader */ >@@ -915,6 +920,20 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, > > #undef cpu_to_gt32 > >+ /* >+ * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. >+ * Load the PIIX IRQC[A:D] routing config address, then >+ * write routing configuration to the config data register. >+ */ >+ bl_gen_write_u32(&p, /* GT_PCI0_CFGADDR */ >+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), >+ tswap32((1 << 31) /* ConfigEn */ >+ | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 >+ | PIIX_PIRQCA)); >+ bl_gen_write_u32(&p, /* GT_PCI0_CFGDATA */ >+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), >+ tswap32(ldl_be_p(pci_pins_cfg))); >+ > bl_gen_jump_kernel(&p, > true, ENVP_VADDR - 64, > /*
On 21/11/22 16:34, Bernhard Beschow wrote: > > > Am 27. Oktober 2022 20:47:19 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >> Linux kernel expects the northbridge & southbridge chipsets >> configured by the BIOS firmware. We emulate that by writing >> a tiny bootloader code in write_bootloader(). >> >> Upon introduction in commit 5c2b87e34d ("PIIX4 support"), >> the PIIX4 configuration space included values specific to >> the Malta board. >> >> Set the Malta-specific IRQ routing values in the embedded >> bootloader, so the next commit can remove the Malta specific >> bits from the PIIX4 PCI-ISA bridge and make it generic >> (matching the real hardware). >> >> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> --- >> FIXME: Missing the nanoMIPS counter-part! > > Who will be taking care of this? I have absolutely no clue how the write_bootloader functions work, so I don't see how to fix it. Oh actually I wrote that and tested it but context switched and forgot about it... I'll look back when I get some time, probably around the release. > Couldn't we just do it like in pegasos2_init() where the registers are initialized by QEMU directly if there is no bootloader binary configured? I could do that. I rather mimic bootloaders... maybe a matter of taste? Regards, Phil.
Am 21. November 2022 22:43:50 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >On 21/11/22 16:34, Bernhard Beschow wrote: >> >> >> Am 27. Oktober 2022 20:47:19 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>> Linux kernel expects the northbridge & southbridge chipsets >>> configured by the BIOS firmware. We emulate that by writing >>> a tiny bootloader code in write_bootloader(). >>> >>> Upon introduction in commit 5c2b87e34d ("PIIX4 support"), >>> the PIIX4 configuration space included values specific to >>> the Malta board. >>> >>> Set the Malta-specific IRQ routing values in the embedded >>> bootloader, so the next commit can remove the Malta specific >>> bits from the PIIX4 PCI-ISA bridge and make it generic >>> (matching the real hardware). >>> >>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >>> --- >>> FIXME: Missing the nanoMIPS counter-part! >> >> Who will be taking care of this? I have absolutely no clue how the write_bootloader functions work, so I don't see how to fix it. > >Oh actually I wrote that and tested it but context switched and forgot >about it... I'll look back when I get some time, probably around the >release. > >> Couldn't we just do it like in pegasos2_init() where the registers are initialized by QEMU directly if there is no bootloader binary configured? I could do that. >I rather mimic bootloaders... maybe a matter of taste? I don't mind either way. I meant that I could help with the second approach but not with the current one since I have no clue whatsoever how it works. There are just too many magic constants that don't make any sense to me, and too many layers of indirection, for example. Anyway, I'm asking for the current state because I'm pretty much ready for posting a v3 of my PIIX consolidation series which now depends on this series. Best regards, Bernhard > >Regards, > >Phil.
Hello, On Mon, 21 Nov 2022, Bernhard Beschow wrote: > Am 21. November 2022 22:43:50 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >> On 21/11/22 16:34, Bernhard Beschow wrote: >>> Am 27. Oktober 2022 20:47:19 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>>> Linux kernel expects the northbridge & southbridge chipsets >>>> configured by the BIOS firmware. We emulate that by writing >>>> a tiny bootloader code in write_bootloader(). >>>> >>>> Upon introduction in commit 5c2b87e34d ("PIIX4 support"), >>>> the PIIX4 configuration space included values specific to >>>> the Malta board. >>>> >>>> Set the Malta-specific IRQ routing values in the embedded >>>> bootloader, so the next commit can remove the Malta specific >>>> bits from the PIIX4 PCI-ISA bridge and make it generic >>>> (matching the real hardware). >>>> >>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >>>> --- >>>> FIXME: Missing the nanoMIPS counter-part! >>> >>> Who will be taking care of this? I have absolutely no clue how the write_bootloader functions work, so I don't see how to fix it. >> >> Oh actually I wrote that and tested it but context switched and forgot >> about it... I'll look back when I get some time, probably around the >> release. Unrelated to this but found it while looking at malta.c now: another possible clean up is to replace the local generate_eeprom_spd() func with spd_data_generate() from hw/i2c/smbus_eeprom.c that other boards use already but I did not change malta because I could not test it. If you can test malta then it should be an easy change and simplify malta.c a bit. >>> Couldn't we just do it like in pegasos2_init() where the registers are initialized by QEMU directly if there is no bootloader binary configured? I could do that. >> I rather mimic bootloaders... maybe a matter of taste? Is that a bootloader or a replacement firmware? To me bootloader is some OS specific binary that is loaded by firware to boot an OS. But there are OS independent bootloaders like grub so maybe you could emulate something like that, I don't know what malta does. If there's no firmware binary QEMU should provide something to replace it to give the expected environment for the binary loaded by -kernel. In case of pegasos2 the init method sets up regs to init devices as done by the firmware and the rest is implemented by VOF (loaded from pc-bios) that provices the OpenFirmware client interface. The device setup in init is needed because VOF does not do that. > I don't mind either way. I meant that I could help with the second > approach but not with the current one since I have no clue whatsoever > how it works. There are just too many magic constants that don't make > any sense to me, and too many layers of indirection, for example. If malta has a replacement firmware for this case maybe it could be stored in a binary in pc-bios and loaded from there instead of writing it in hex to guest memory. That binary could even be assembled from source which should make it simpler to write and change. Or is YAMON open source? According to this page it is: https://www.mips.com/develop/tools/boot-loaders/ so maybe it could be included as a firmware binary instead of being emulated? Regards, BALATON Zoltan > Anyway, I'm asking for the current state because I'm pretty much ready for posting a v3 of my PIIX consolidation series which now depends on this series. > > Best regards, > Bernhard > >> >> Regards, >> >> Phil. > >
> 2022年11月22日 12:37，BALATON Zoltan <balaton@eik.bme.hu> 写道： > > Hello, > > On Mon, 21 Nov 2022, Bernhard Beschow wrote: >> Am 21. November 2022 22:43:50 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>> On 21/11/22 16:34, Bernhard Beschow wrote: >>>> Am 27. Oktober 2022 20:47:19 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>>>> Linux kernel expects the northbridge & southbridge chipsets >>>>> configured by the BIOS firmware. We emulate that by writing >>>>> a tiny bootloader code in write_bootloader(). >>>>> >>>>> Upon introduction in commit 5c2b87e34d ("PIIX4 support"), >>>>> the PIIX4 configuration space included values specific to >>>>> the Malta board. >>>>> >>>>> Set the Malta-specific IRQ routing values in the embedded >>>>> bootloader, so the next commit can remove the Malta specific >>>>> bits from the PIIX4 PCI-ISA bridge and make it generic >>>>> (matching the real hardware). >>>>> >>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >>>>> --- >>>>> FIXME: Missing the nanoMIPS counter-part! >>>> >>>> Who will be taking care of this? I have absolutely no clue how the write_bootloader functions work, so I don't see how to fix it. >>> >>> Oh actually I wrote that and tested it but context switched and forgot >>> about it... I'll look back when I get some time, probably around the >>> release. I can try to adopt existing boot loader helper functions, just a matter of opcodes I think. > > Unrelated to this but found it while looking at malta.c now: another possible clean up is to replace the local generate_eeprom_spd() func with spd_data_generate() from hw/i2c/smbus_eeprom.c that other boards use already but I did not change malta because I could not test it. If you can test malta then it should be an easy change and simplify malta.c a bit. > >>>> Couldn't we just do it like in pegasos2_init() where the registers are initialized by QEMU directly if there is no bootloader binary configured? I could do that. >>> I rather mimic bootloaders... maybe a matter of taste? > > Is that a bootloader or a replacement firmware? To me bootloader is some OS specific binary that is loaded by firware to boot an OS. But there are OS independent bootloaders like grub so maybe you could emulate something like that, I don't know what malta does. YAMON is a OS-dependent and HW-dependent firmware like u-boot. > > If there's no firmware binary QEMU should provide something to replace it to give the expected environment for the binary loaded by -kernel. In case of pegasos2 the init method sets up regs to init devices as done by the firmware and the rest is implemented by VOF (loaded from pc-bios) that provices the OpenFirmware client interface. The device setup in init is needed because VOF does not do that. > >> I don't mind either way. I meant that I could help with the second approach but not with the current one since I have no clue whatsoever how it works. There are just too many magic constants that don't make any sense to me, and too many layers of indirection, for example. > > If malta has a replacement firmware for this case maybe it could be stored in a binary in pc-bios and loaded from there instead of writing it in hex to guest memory. That binary could even be assembled from source which should make it simpler to write and change. Or is YAMON open source? According to this page it is: https://www.mips.com/develop/tools/boot-loaders/ so maybe it could be included as a firmware binary instead of being emulated? Hmm, YAMON was a open source software but I’m unable to find a copy of source for Malta board comes with GT chipset that QEMU emulated. So nowadays we mainly use -kernel feature to do direct kernel boot. Direct kernel boot is really a brilliant function that I don’t want to lose :-) Thanks - Jiaxun > > Regards, > BALATON Zoltan > >> Anyway, I'm asking for the current state because I'm pretty much ready for posting a v3 of my PIIX consolidation series which now depends on this series. >> >> Best regards, >> Bernhard >> >>> >>> Regards, >>> >>> Phil. >>
Am 21. November 2022 15:34:05 UTC schrieb Bernhard Beschow <shentey@gmail.com>: > > >Am 27. Oktober 2022 20:47:19 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>Linux kernel expects the northbridge & southbridge chipsets >>configured by the BIOS firmware. We emulate that by writing >>a tiny bootloader code in write_bootloader(). >> >>Upon introduction in commit 5c2b87e34d ("PIIX4 support"), >>the PIIX4 configuration space included values specific to >>the Malta board. >> >>Set the Malta-specific IRQ routing values in the embedded >>bootloader, so the next commit can remove the Malta specific >>bits from the PIIX4 PCI-ISA bridge and make it generic >>(matching the real hardware). >> >>Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >>--- >>FIXME: Missing the nanoMIPS counter-part! > >Who will be taking care of this? I have absolutely no clue how the write_bootloader functions work, so I don't see how to fix it. Ping >Couldn't we just do it like in pegasos2_init() where the registers are initialized by QEMU directly if there is no bootloader binary configured? I could do that. > >Best regards, >Bernhard >>--- >> hw/mips/malta.c | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> >>diff --git a/hw/mips/malta.c b/hw/mips/malta.c >>index df0f448b67..4403028778 100644 >>--- a/hw/mips/malta.c >>+++ b/hw/mips/malta.c >>@@ -804,6 +804,8 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, >> stw_p(p++, 0x8422); stw_p(p++, 0x9088); >> /* sw t0, 0x88(t1) */ >> >>+ /* TODO set PIIX IRQC[A:D] routing values! */ >>+ >> stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); >> >> stw_p(p++, NM_HI2(kernel_entry)); >>@@ -841,6 +843,9 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, >> static void write_bootloader(uint8_t *base, uint64_t run_addr, >> uint64_t kernel_entry) >> { >>+ const char pci_pins_cfg[PCI_NUM_PINS] = { >>+ 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ >>+ }; >> uint32_t *p; >> >> /* Small bootloader */ >>@@ -915,6 +920,20 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, >> >> #undef cpu_to_gt32 >> >>+ /* >>+ * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. >>+ * Load the PIIX IRQC[A:D] routing config address, then >>+ * write routing configuration to the config data register. >>+ */ >>+ bl_gen_write_u32(&p, /* GT_PCI0_CFGADDR */ >>+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), >>+ tswap32((1 << 31) /* ConfigEn */ >>+ | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 >>+ | PIIX_PIRQCA)); >>+ bl_gen_write_u32(&p, /* GT_PCI0_CFGDATA */ >>+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), >>+ tswap32(ldl_be_p(pci_pins_cfg))); >>+ >> bl_gen_jump_kernel(&p, >> true, ENVP_VADDR - 64, >> /*
On 31/12/22 10:53, Bernhard Beschow wrote: > > > Am 21. November 2022 15:34:05 UTC schrieb Bernhard Beschow <shentey@gmail.com>: >> >> >> Am 27. Oktober 2022 20:47:19 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>> Linux kernel expects the northbridge & southbridge chipsets >>> configured by the BIOS firmware. We emulate that by writing >>> a tiny bootloader code in write_bootloader(). >>> >>> Upon introduction in commit 5c2b87e34d ("PIIX4 support"), >>> the PIIX4 configuration space included values specific to >>> the Malta board. >>> >>> Set the Malta-specific IRQ routing values in the embedded >>> bootloader, so the next commit can remove the Malta specific >>> bits from the PIIX4 PCI-ISA bridge and make it generic >>> (matching the real hardware). >>> >>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >>> --- >>> FIXME: Missing the nanoMIPS counter-part! >> >> Who will be taking care of this? I have absolutely no clue how the write_bootloader functions work, so I don't see how to fix it. > > Ping This comment has been taken care of: https://lore.kernel.org/qemu-devel/a3c3f639-dbb1-88a7-43fe-547a234c5890@linaro.org/ However while testing the MIPS pull request I prepared I found a bug in the GT64120 which I'm trying to fix since various days... Unfortunately your series depends on it, so this is a blocking issue. Sorry for this long delay... Phil.
Am 31. Dezember 2022 13:44:00 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >On 31/12/22 10:53, Bernhard Beschow wrote: >> >> >> Am 21. November 2022 15:34:05 UTC schrieb Bernhard Beschow <shentey@gmail.com>: >>> >>> >>> Am 27. Oktober 2022 20:47:19 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>>> Linux kernel expects the northbridge & southbridge chipsets >>>> configured by the BIOS firmware. We emulate that by writing >>>> a tiny bootloader code in write_bootloader(). >>>> >>>> Upon introduction in commit 5c2b87e34d ("PIIX4 support"), >>>> the PIIX4 configuration space included values specific to >>>> the Malta board. >>>> >>>> Set the Malta-specific IRQ routing values in the embedded >>>> bootloader, so the next commit can remove the Malta specific >>>> bits from the PIIX4 PCI-ISA bridge and make it generic >>>> (matching the real hardware). >>>> >>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >>>> --- >>>> FIXME: Missing the nanoMIPS counter-part! >>> >>> Who will be taking care of this? I have absolutely no clue how the write_bootloader functions work, so I don't see how to fix it. >> >> Ping > >This comment has been taken care of: >https://lore.kernel.org/qemu-devel/a3c3f639-dbb1-88a7-43fe-547a234c5890@linaro.org/ Ah, now I see where this is going. >However while testing the MIPS pull request I prepared I >found a bug in the GT64120 which I'm trying to fix since >various days... Unfortunately your series depends on it, >so this is a blocking issue. Sorry for this long delay... Don't worry. How can the bug be reproduced? Is there a test run in the CI? Note that I get a 404 when trying to access https://gitlab.com/philmd/qemu/-/commits/mips-testing/ . Best regards, Bernhard > >Phil.
On 2/1/23 01:03, Bernhard Beschow wrote: > > > Am 31. Dezember 2022 13:44:00 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >> On 31/12/22 10:53, Bernhard Beschow wrote: >>> >>> >>> Am 21. November 2022 15:34:05 UTC schrieb Bernhard Beschow <shentey@gmail.com>: >>>> >>>> >>>> Am 27. Oktober 2022 20:47:19 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>>>> Linux kernel expects the northbridge & southbridge chipsets >>>>> configured by the BIOS firmware. We emulate that by writing >>>>> a tiny bootloader code in write_bootloader(). >>>>> >>>>> Upon introduction in commit 5c2b87e34d ("PIIX4 support"), >>>>> the PIIX4 configuration space included values specific to >>>>> the Malta board. >>>>> >>>>> Set the Malta-specific IRQ routing values in the embedded >>>>> bootloader, so the next commit can remove the Malta specific >>>>> bits from the PIIX4 PCI-ISA bridge and make it generic >>>>> (matching the real hardware). >>>>> >>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >>>>> --- >>>>> FIXME: Missing the nanoMIPS counter-part! >>>> >>>> Who will be taking care of this? I have absolutely no clue how the write_bootloader functions work, so I don't see how to fix it. >>> >>> Ping >> >> This comment has been taken care of: >> https://lore.kernel.org/qemu-devel/a3c3f639-dbb1-88a7-43fe-547a234c5890@linaro.org/ > > Ah, now I see where this is going. > >> However while testing the MIPS pull request I prepared I >> found a bug in the GT64120 which I'm trying to fix since >> various days... Unfortunately your series depends on it, >> so this is a blocking issue. Sorry for this long delay... > > Don't worry. > > How can the bug be reproduced? Is there a test run in the CI? My problem was on big-endian hosts, now fixed by: https://lore.kernel.org/qemu-devel/20230104133935.4639-1-philmd@linaro.org/ > Note that I get a 404 when trying to access https://gitlab.com/philmd/qemu/-/commits/mips-testing/ . Oh for some reason my repository was set for 'project members', I now changed that to 'everyone'. I'll rebuild the mips-testing queue later today or tomorrow and restart my testing. Regards, Phil.
diff --git a/hw/mips/malta.c b/hw/mips/malta.c index df0f448b67..4403028778 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -804,6 +804,8 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, stw_p(p++, 0x8422); stw_p(p++, 0x9088); /* sw t0, 0x88(t1) */ + /* TODO set PIIX IRQC[A:D] routing values! */ + stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); stw_p(p++, NM_HI2(kernel_entry)); @@ -841,6 +843,9 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, static void write_bootloader(uint8_t *base, uint64_t run_addr, uint64_t kernel_entry) { + const char pci_pins_cfg[PCI_NUM_PINS] = { + 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ + }; uint32_t *p; /* Small bootloader */ @@ -915,6 +920,20 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, #undef cpu_to_gt32 + /* + * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. + * Load the PIIX IRQC[A:D] routing config address, then + * write routing configuration to the config data register. + */ + bl_gen_write_u32(&p, /* GT_PCI0_CFGADDR */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), + tswap32((1 << 31) /* ConfigEn */ + | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 + | PIIX_PIRQCA)); + bl_gen_write_u32(&p, /* GT_PCI0_CFGDATA */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), + tswap32(ldl_be_p(pci_pins_cfg))); + bl_gen_jump_kernel(&p, true, ENVP_VADDR - 64, /*
Linux kernel expects the northbridge & southbridge chipsets configured by the BIOS firmware. We emulate that by writing a tiny bootloader code in write_bootloader(). Upon introduction in commit 5c2b87e34d ("PIIX4 support"), the PIIX4 configuration space included values specific to the Malta board. Set the Malta-specific IRQ routing values in the embedded bootloader, so the next commit can remove the Malta specific bits from the PIIX4 PCI-ISA bridge and make it generic (matching the real hardware). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- FIXME: Missing the nanoMIPS counter-part! --- hw/mips/malta.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)