| Message ID | 20230125104520.89684-1-quic_kathirav@quicinc.com |
|---|---|
| Headers | show |
| Series | Add minimal boot support for IPQ5332 | expand |
On 25/01/2023 11:45, Kathiravan Thirumoorthy wrote: > From: Kathiravan T <quic_kathirav@quicinc.com> > > Add device tree bindings for IPQ5332 TLMM block. > > Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> > --- > .../pinctrl/qcom,ipq5332-pinctrl.yaml | 134 ++++++++++++++++++ > 1 file changed, 134 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-pinctrl.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-pinctrl.yaml > new file mode 100644 > index 000000000000..d101ee04b8b7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-pinctrl.yaml Name matching compatible, please. > @@ -0,0 +1,134 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm IPQ5332 TLMM pin controller > + > +maintainers: > + - Bjorn Andersson <andersson@kernel.org> > + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > + > +description: | > + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC. > + > +allOf: > + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# > + > +properties: > + compatible: > + const: qcom,ipq5332-tlmm > + > + reg: > + maxItems: 1 > + > + interrupts: true missing maxItems Rebase your patches on latest next and use the latest bindings and drivers as starting point. > + interrupt-controller: true > + "#interrupt-cells": true > + gpio-controller: true > + "#gpio-cells": true > + gpio-ranges: true > + wakeup-parent: true > + > + gpio-reserved-ranges: > + minItems: 1 > + maxItems: 27 > + > + gpio-line-names: > + maxItems: 53 You have 54 GPIOs. > + > +patternProperties: > + "-state$": > + oneOf: > + - $ref: "#/$defs/qcom-ipq5332-tlmm-state" > + - patternProperties: > + "-pins$": > + $ref: "#/$defs/qcom-ipq5332-tlmm-state" > + additionalProperties: false > + > +$defs: > + qcom-ipq5332-tlmm-state: > + type: object > + description: > + Pinctrl node's client devices use subnodes for desired pin configuration. > + Client device subnodes use below standard properties. > + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state > + > + properties: > + pins: > + description: > + List of gpio pins affected by the properties specified in this > + subnode. > + items: > + pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$" > + minItems: 1 > + maxItems: 36 > + > + function: > + description: > + Specify the alternative function to be configured for the specified > + pins. > + > + enum: [ PTA_0, PTA_2, PTA_1, atest_char, atest_char0, atest_char1, 1. lowercase only 2. order all these by name > + atest_char2, atest_char3, atest_tic, audio_pri, audio_pri0, > + audio_pri1, audio_sec, audio_sec0, audio_sec1, blsp0_i2c, > + blsp0_spi, blsp0_uart0, blsp0_uart1, blsp1_i2c0, blsp1_i2c1, > + blsp1_spi0, blsp1_spi1, blsp1_uart0, blsp1_uart1, blsp1_uart2, > + blsp2_i2c0, blsp2_i2c1, blsp2_spi, blsp2_spi0, blsp2_spi1, > + core_voltage, cri_trng0, cri_trng1, cri_trng2, cri_trng3, > + cxc_clk, cxc_data, dbg_out, gcc_plltest, gcc_tlmm, gpio, > + lock_det, mac0, mac1, mdc0, mdc1, mdio0, mdio1, pc, pcie0_clk, Best regards, Krzysztof
On 25/01/2023 11:45, Kathiravan Thirumoorthy wrote: > From: Kathiravan T <quic_kathirav@quicinc.com> > > Add support for the global clock controller found on IPQ5332 SoC. > > Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> > --- > drivers/clk/qcom/Kconfig | 7 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/gcc-ipq5332.c | 3954 ++++++++++++++++++++++++++++++++ > 3 files changed, 3962 insertions(+) > create mode 100644 drivers/clk/qcom/gcc-ipq5332.c > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 70d43f0a8919..1d300c89ecfc 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -141,6 +141,13 @@ config IPQ_GCC_4019 > Say Y if you want to use peripheral devices such as UART, SPI, > i2c, USB, SD/eMMC, etc. > > +config IPQ_GCC_5332 > + tristate "IPQ5332 Global Clock Controller" depends on ARM64 || COMPILE_TEST Best regards, Krzysztof
On 1/25/2023 4:44 PM, Krzysztof Kozlowski wrote: > On 25/01/2023 11:45, Kathiravan Thirumoorthy wrote: >> From: Kathiravan T <quic_kathirav@quicinc.com> >> >> Add support for the global clock controller found on IPQ5332 SoC. >> >> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> >> --- >> drivers/clk/qcom/Kconfig | 7 + >> drivers/clk/qcom/Makefile | 1 + >> drivers/clk/qcom/gcc-ipq5332.c | 3954 ++++++++++++++++++++++++++++++++ >> 3 files changed, 3962 insertions(+) >> create mode 100644 drivers/clk/qcom/gcc-ipq5332.c >> >> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig >> index 70d43f0a8919..1d300c89ecfc 100644 >> --- a/drivers/clk/qcom/Kconfig >> +++ b/drivers/clk/qcom/Kconfig >> @@ -141,6 +141,13 @@ config IPQ_GCC_4019 >> Say Y if you want to use peripheral devices such as UART, SPI, >> i2c, USB, SD/eMMC, etc. >> >> +config IPQ_GCC_5332 >> + tristate "IPQ5332 Global Clock Controller" > depends on ARM64 || COMPILE_TEST Ack. > > > > Best regards, > Krzysztof Thanks, Kathiravan T.
On 25/01/2023 16:49, Kathiravan Thirumoorthy wrote: >> >>> @@ -0,0 +1,134 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-pinctrl.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Qualcomm IPQ5332 TLMM pin controller >>> + >>> +maintainers: >>> + - Bjorn Andersson <andersson@kernel.org> >>> + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >>> + >>> +description: | >>> + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC. >>> + >>> +allOf: >>> + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# >>> + >>> +properties: >>> + compatible: >>> + const: qcom,ipq5332-tlmm >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + interrupts: true >> missing maxItems >> >> Rebase your patches on latest next and use the latest bindings and >> drivers as starting point. > > > Changes are based on v6.2-rc1. I see the maxItems changes in > linux-next. Will update this in V2. Your patches cannot be based on v6.2-rc1. They won't even apply. You miss entire development of last month. > > >>> + interrupt-controller: true >>> + "#interrupt-cells": true >>> + gpio-controller: true >>> + "#gpio-cells": true >>> + gpio-ranges: true >>> + wakeup-parent: true >>> + >>> + gpio-reserved-ranges: >>> + minItems: 1 >>> + maxItems: 27 >>> + >>> + gpio-line-names: >>> + maxItems: 53 >> You have 54 GPIOs. > > > Sorry, GPIO ranges are from 0-52, will update it in all places in V2. Ah, then the gpio pattern needs a fix. Best regards, Krzysztof
On 1/25/2023 9:50 PM, Krzysztof Kozlowski wrote: > On 25/01/2023 16:49, Kathiravan Thirumoorthy wrote: >>>> @@ -0,0 +1,134 @@ >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-pinctrl.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Qualcomm IPQ5332 TLMM pin controller >>>> + >>>> +maintainers: >>>> + - Bjorn Andersson <andersson@kernel.org> >>>> + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >>>> + >>>> +description: | >>>> + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC. >>>> + >>>> +allOf: >>>> + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# >>>> + >>>> +properties: >>>> + compatible: >>>> + const: qcom,ipq5332-tlmm >>>> + >>>> + reg: >>>> + maxItems: 1 >>>> + >>>> + interrupts: true >>> missing maxItems >>> >>> Rebase your patches on latest next and use the latest bindings and >>> drivers as starting point. >> >> Changes are based on v6.2-rc1. I see the maxItems changes in >> linux-next. Will update this in V2. > Your patches cannot be based on v6.2-rc1. They won't even apply. You > miss entire development of last month. Hmmm, Will use linux-next/master as base hereafter. >> >>>> + interrupt-controller: true >>>> + "#interrupt-cells": true >>>> + gpio-controller: true >>>> + "#gpio-cells": true >>>> + gpio-ranges: true >>>> + wakeup-parent: true >>>> + >>>> + gpio-reserved-ranges: >>>> + minItems: 1 >>>> + maxItems: 27 >>>> + >>>> + gpio-line-names: >>>> + maxItems: 53 >>> You have 54 GPIOs. >> >> Sorry, GPIO ranges are from 0-52, will update it in all places in V2. > Ah, then the gpio pattern needs a fix. Yup, will take care of that as well in V2. > > > Best regards, > Krzysztof >
On 1/26/2023 2:24 AM, Stephen Boyd wrote: > Quoting Kathiravan Thirumoorthy (2023-01-25 02:45:15) >> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c >> new file mode 100644 >> index 000000000000..8351096a4d32 >> --- /dev/null >> +++ b/drivers/clk/qcom/gcc-ipq5332.c >> @@ -0,0 +1,3954 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +#include <linux/clk-provider.h> >> +#include <linux/module.h> >> +#include <linux/of_device.h> >> +#include <linux/regmap.h> > [...] >> + >> +static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = { >> + F(24000000, P_XO, 1, 0, 0), >> + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), >> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = { >> + .cmd_rcgr = 0x31004, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data){ >> + .name = "gcc_pcnoc_bfdcd_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .ops = &clk_rcg2_ops, >> + .flags = CLK_IS_CRITICAL, > Why not just turn these clks on in probe and never register them with > the framework? That saves some memory for clks that there is no desire > to control from linux. This is an RCG, so in theory the frequency can > change, but does it really? Usually bus clks are controlled by the > interconnect driver. Thanks Stephen for reviewing the patch. I will look into this and make changes appropriately in V2.
From: Kathiravan T <quic_kathirav@quicinc.com> The IPQ5332 is Qualcomm's 802.11ax SoC for Routers, Gateways and Access Points. This series adds minimal board boot support for ipq5332-mi01.2 board. Also, this series depends on the below patch https://lore.kernel.org/linux-arm-msm/20230120082631.22053-1-quic_kathirav@quicinc.com/ Kathiravan T (10): dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl pinctrl: qcom: Introduce IPQ5332 TLMM driver clk: qcom: Add STROMER PLUS PLL type for IPQ5332 dt-bindings: clock: Add Qualcomm IPQ5332 GCC clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC dt-bindings: qcom: add ipq5332 boards dt-bindings: firmware: document IPQ5332 SCM dt-bindings: mmc: sdhci-msm: add IPQ5332 compatible arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support arm64: defconfig: Enable IPQ5332 SoC base configs .../devicetree/bindings/arm/qcom.yaml | 7 + .../bindings/clock/qcom,ipq5332-gcc.yaml | 55 + .../bindings/firmware/qcom,scm.yaml | 1 + .../devicetree/bindings/mmc/sdhci-msm.yaml | 1 + .../pinctrl/qcom,ipq5332-pinctrl.yaml | 134 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts | 71 + arch/arm64/boot/dts/qcom/ipq5332.dtsi | 273 ++ arch/arm64/configs/defconfig | 2 + drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.c | 11 + drivers/clk/qcom/clk-alpha-pll.h | 1 + drivers/clk/qcom/gcc-ipq5332.c | 3954 +++++++++++++++++ drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq5332.c | 1008 +++++ include/dt-bindings/clock/qcom,gcc-ipq5332.h | 359 ++ 18 files changed, 5897 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-pinctrl.yaml create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq5332.dtsi create mode 100644 drivers/clk/qcom/gcc-ipq5332.c create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5332.c create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5332.h