diff mbox series

[3/5] firmware: scm: Modify only the DLOAD bit in TCSR register for download mode

Message ID 20230113160012.14893-4-quic_poovendh@quicinc.com
State Superseded
Headers show
Series [1/5] dt-bindings: scm: Add compatible for IPQ9574 | expand

Commit Message

Poovendhan Selvaraj Jan. 13, 2023, 4 p.m. UTC 
Add support to read-modify-write TCSR register to modify only DLOAD bit.

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Co-developed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
---
 drivers/firmware/qcom_scm.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

Comments

Guru Das Srinagesh Jan. 14, 2023, 1:16 a.m. UTC | #1 
On Jan 13 2023 21:30, Poovendhan Selvaraj wrote:
> Add support to read-modify-write TCSR register to modify only DLOAD bit.

Could you please add more details on what problem this patch is fixing, and why
this patch is needed?

Thank you.

Guru Das.
Poovendhan Selvaraj Jan. 27, 2023, 3 p.m. UTC | #2 
On 1/14/2023 6:46 AM, Guru Das Srinagesh wrote:
> On Jan 13 2023 21:30, Poovendhan Selvaraj wrote:
>> Add support to read-modify-write TCSR register to modify only DLOAD bit.
> Could you please add more details on what problem this patch is fixing, and why
> this patch is needed?
>
> CrashDump collection is based on the DLOAD bit of TCSR register. To retain other bits, we read the register and modify only the DLOAD bit as the other bits have their own significance.
>
> Thank you.
>
> Guru Das.
>
> Regards,
> Poovendhan S
Lee Jones Jan. 27, 2023, 5:17 p.m. UTC | #3 
On Fri, 27 Jan 2023, POOVENDHAN SELVARAJ wrote:

> 
> On 1/14/2023 6:46 AM, Guru Das Srinagesh wrote:
> > On Jan 13 2023 21:30, Poovendhan Selvaraj wrote:
> > > Add support to read-modify-write TCSR register to modify only DLOAD bit.
> > Could you please add more details on what problem this patch is fixing, and why
> > this patch is needed?
> > 
> > CrashDump collection is based on the DLOAD bit of TCSR register. To retain other bits, we read the register and modify only the DLOAD bit as the other bits have their own significance.
> > 
> > Thank you.
> > 
> > Guru Das.
> > 
> > Regards,
> > Poovendhan S

Could you please fix your email client.

I have no idea which text is yours, in any of your mails.
diff mbox series

Patch

diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index cdbfe54c8146..b56d8f465f71 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -400,7 +400,7 @@  int qcom_scm_set_remote_state(u32 state, u32 id)
 }
 EXPORT_SYMBOL(qcom_scm_set_remote_state);
 
-static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
+static int __qcom_scm_set_dload_mode(struct device *dev, u32 val, bool enable)
 {
 	struct qcom_scm_desc desc = {
 		.svc = QCOM_SCM_SVC_BOOT,
@@ -410,7 +410,7 @@  static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
 		.owner = ARM_SMCCC_OWNER_SIP,
 	};
 
-	desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
+	desc.args[1] = enable ? val | QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
 
 	return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
 }
@@ -419,15 +419,19 @@  static void qcom_scm_set_download_mode(bool enable)
 {
 	bool avail;
 	int ret = 0;
+	u32 dload_addr_val;
 
 	avail = __qcom_scm_is_call_available(__scm->dev,
 					     QCOM_SCM_SVC_BOOT,
 					     QCOM_SCM_BOOT_SET_DLOAD_MODE);
+	ret = qcom_scm_io_readl(__scm->dload_mode_addr, &dload_addr_val);
+
 	if (avail) {
-		ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
+		ret = __qcom_scm_set_dload_mode(__scm->dev, dload_addr_val, enable);
 	} else if (__scm->dload_mode_addr) {
 		ret = qcom_scm_io_writel(__scm->dload_mode_addr,
-				enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
+				enable ? dload_addr_val |
+					QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
 	} else {
 		dev_err(__scm->dev,
 			"No available mechanism for setting download mode\n");