diff mbox series

clk: qcom: ipq5332: mark GPLL4 as critical temporarily

Message ID 20230130120959.9457-1-quic_kathirav@quicinc.com
State New
Headers show
Series clk: qcom: ipq5332: mark GPLL4 as critical temporarily | expand

Commit Message

Kathiravan Thirumoorthy Jan. 30, 2023, 12:09 p.m. UTC 
From: Kathiravan T <quic_kathirav@quicinc.com>

Clock framework disables the GPLL4 source since there are no active users
for this source currently. Some of the clocks initialized by the
bootloaders uses the GPLL4 as the source. Due to this, when the GPLL4 is
disabled by the clock framework, system is going for the reboot.

To avoid this, mark the GPLL4 as CRITICAL so that clock framework
doesn't disable it. Once the users of this source is enabled, we can get
rid of this flag.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Note: This patch depends on the IPQ5332 baseport series
https://lore.kernel.org/linux-arm-msm/20230130114702.20606-1-quic_kathirav@quicinc.com/T/#t

 drivers/clk/qcom/gcc-ipq5332.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Stephen Boyd Jan. 31, 2023, 9:17 p.m. UTC | #1 
Quoting Kathiravan Thirumoorthy (2023-01-30 04:09:59)
> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
> index a8ce618bb81b..6159d0e1e43f 100644
> --- a/drivers/clk/qcom/gcc-ipq5332.c
> +++ b/drivers/clk/qcom/gcc-ipq5332.c
> @@ -127,6 +127,7 @@ static struct clk_alpha_pll gpll4_main = {
>                         .parent_data = &gcc_parent_data_xo,
>                         .num_parents = 1,
>                         .ops = &clk_alpha_pll_stromer_ops,
> +                       .flags = CLK_IS_CRITICAL,

Please add a comment above this line that indicates why this is
critical. What clk needs to be added that will actually use this? If
nothing is ever going to use the PLL then maybe we should simply not
register this PLL with the clk framework?
Kathiravan Thirumoorthy Feb. 1, 2023, 6:03 a.m. UTC | #2 
On 2/1/2023 2:47 AM, Stephen Boyd wrote:
> Quoting Kathiravan Thirumoorthy (2023-01-30 04:09:59)
>> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
>> index a8ce618bb81b..6159d0e1e43f 100644
>> --- a/drivers/clk/qcom/gcc-ipq5332.c
>> +++ b/drivers/clk/qcom/gcc-ipq5332.c
>> @@ -127,6 +127,7 @@ static struct clk_alpha_pll gpll4_main = {
>>                          .parent_data = &gcc_parent_data_xo,
>>                          .num_parents = 1,
>>                          .ops = &clk_alpha_pll_stromer_ops,
>> +                       .flags = CLK_IS_CRITICAL,
> Please add a comment above this line that indicates why this is
> critical. What clk needs to be added that will actually use this? If
> nothing is ever going to use the PLL then maybe we should simply not
> register this PLL with the clk framework?
Sure, will add the comment in the code also.

There are bunch of WCSS, Q6, QDSS, PCIE clocks uses the GPPL4 as source. 
Few of them are getting disabled by clock framework since there are no 
consumers yet (which will added soon) and few of them are yet to be 
added. So we cannot leave out this PLL. If any one of the consumer is 
enabled, this patch can be reverted.
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index a8ce618bb81b..6159d0e1e43f 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -127,6 +127,7 @@  static struct clk_alpha_pll gpll4_main = {
 			.parent_data = &gcc_parent_data_xo,
 			.num_parents = 1,
 			.ops = &clk_alpha_pll_stromer_ops,
+			.flags = CLK_IS_CRITICAL,
 		},
 	},
 };