| Message ID | 20230223145426.193590-5-angelogioacchino.delregno@collabora.com |
|---|---|
| State | New |
| Headers | show |
| Series | MT8195 Cherry: Enable PCIe/WiFi, add PWMs | expand |
On Thu, Feb 23, 2023 at 10:56 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote: > > Configure the hardware PWM for the integrated display's backlight: > all Cherry devices enable the backlight with GPIO82 and manage the > PWM via MediaTek disp-pwm on GPIO97. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> with some additional patches to enable the internal display.
On Fri, Feb 24, 2023 at 4:52 PM Chen-Yu Tsai <wenst@chromium.org> wrote: > > On Thu, Feb 23, 2023 at 10:56 PM AngeloGioacchino Del Regno > <angelogioacchino.delregno@collabora.com> wrote: > > > > Configure the hardware PWM for the integrated display's backlight: > > all Cherry devices enable the backlight with GPIO82 and manage the > > PWM via MediaTek disp-pwm on GPIO97. > > > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > Tested-by: Chen-Yu Tsai <wenst@chromium.org> > > with some additional patches to enable the internal display. Matthias, could you pick up patches 3 and 4 from this series? They are independent of the other two patches. Having them picked up would reduce the number of patches that have to get carried for testing and resent. Thanks ChenYu
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index d679a04207d8..c50f1e2914b2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -22,6 +22,16 @@ aliases { serial0 = &uart0; }; + backlight_lcd0: backlight-lcd0 { + compatible = "pwm-backlight"; + brightness-levels = <0 1023>; + default-brightness-level = <576>; + enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>; + num-interpolated-steps = <1023>; + pwms = <&disp_pwm0 0 500000>; + power-supply = <&ppvar_sys>; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -349,6 +359,13 @@ &auxadc { status = "okay"; }; +&disp_pwm0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pin_default>; +}; + &i2c0 { status = "okay"; @@ -773,6 +790,13 @@ pins-cmd-dat { }; }; + disp_pwm0_pin_default: disp-pwm0-default-pins { + pins-disp-pwm { + pinmux = <PINMUX_GPIO82__FUNC_GPIO82>, + <PINMUX_GPIO97__FUNC_DISP_PWM0>; + }; + }; + i2c0_pins: i2c0-default-pins { pins-bus { pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
Configure the hardware PWM for the integrated display's backlight: all Cherry devices enable the backlight with GPIO82 and manage the PWM via MediaTek disp-pwm on GPIO97. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+)