| Message ID | 20230331105546.13607-16-victor.shih@genesyslogic.com.tw |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [V7,01/23] mmc: core: Cleanup printing of speed mode at card insertion | expand |
On 31/03/23 13:55, Victor Shih wrote: > Sdhci_uhs2_do_detect_init() is a sdhci version of mmc's uhs2_detect_init > operation. After detected, the host's UHS-II capabilities will be set up > here and interrupts will also be enabled. > > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> > Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> > Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw> > --- > drivers/mmc/host/sdhci-uhs2.c | 117 ++++++++++++++++++++++++++++++++++ > 1 file changed, 117 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c > index 9b519bd6d76e..e2972be1889f 100644 > --- a/drivers/mmc/host/sdhci-uhs2.c > +++ b/drivers/mmc/host/sdhci-uhs2.c > @@ -334,6 +334,123 @@ static int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) > * * > \*****************************************************************************/ > > +static int sdhci_uhs2_interface_detect(struct sdhci_host *host) > +{ > + /* 100ms */ > + int timeout = 100000; > + u32 val; > + > + udelay(200); /* wait for 200us before check */ There does not seem to be any need for this function to be atomic, so this should use usleep_range() not udelay(). > + > + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_IF_DETECT), > + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { Does not need to be atomic > + pr_warn("%s: not detect UHS2 interface in 200us.\n", mmc_hostname(host->mmc)); > + sdhci_dumpregs(host); > + return -EIO; > + } > + > + /* Enable UHS2 error interrupts */ > + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK); > + > + /* 150ms */ > + timeout = 150000; > + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_LANE_SYNC), Does not need to be atomic > + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { > + pr_warn("%s: UHS2 Lane sync fail in 150ms.\n", mmc_hostname(host->mmc)); > + sdhci_dumpregs(host); > + return -EIO; > + } > + > + DBG("%s: UHS2 Lane synchronized in UHS2 mode, PHY is initialized.\n", > + mmc_hostname(host->mmc)); > + return 0; > +} > + > +static int sdhci_uhs2_init(struct sdhci_host *host) > +{ > + u16 caps_ptr = 0; > + u32 caps_gen = 0; > + u32 caps_phy = 0; > + u32 caps_tran[2] = {0, 0}; > + struct mmc_host *mmc = host->mmc; > + > + caps_ptr = sdhci_readw(host, SDHCI_UHS2_CAPS_PTR); > + if (caps_ptr < 0x100 || caps_ptr > 0x1FF) { > + pr_err("%s: SDHCI_UHS2_CAPS_PTR(%d) is wrong.\n", > + mmc_hostname(mmc), caps_ptr); > + return -ENODEV; > + } > + caps_gen = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_OFFSET); > + caps_phy = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_PHY_OFFSET); > + caps_tran[0] = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_OFFSET); > + caps_tran[1] = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_1_OFFSET); > + > + /* General Caps */ > + mmc->uhs2_caps.dap = caps_gen & SDHCI_UHS2_CAPS_DAP_MASK; > + mmc->uhs2_caps.gap = FIELD_GET(SDHCI_UHS2_CAPS_GAP_MASK, caps_gen); > + mmc->uhs2_caps.n_lanes = FIELD_GET(SDHCI_UHS2_CAPS_LANE_MASK, caps_gen); > + mmc->uhs2_caps.addr64 = (caps_gen & SDHCI_UHS2_CAPS_ADDR_64) ? 1 : 0; > + mmc->uhs2_caps.card_type = FIELD_GET(SDHCI_UHS2_CAPS_DEV_TYPE_MASK, caps_gen); > + > + /* PHY Caps */ > + mmc->uhs2_caps.phy_rev = caps_phy & SDHCI_UHS2_CAPS_PHY_REV_MASK; > + mmc->uhs2_caps.speed_range = FIELD_GET(SDHCI_UHS2_CAPS_PHY_RANGE_MASK, caps_phy); > + mmc->uhs2_caps.n_lss_sync = FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_SYN_MASK, caps_phy); > + mmc->uhs2_caps.n_lss_dir = FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_DIR_MASK, caps_phy); > + if (mmc->uhs2_caps.n_lss_sync == 0) > + mmc->uhs2_caps.n_lss_sync = 16 << 2; > + else > + mmc->uhs2_caps.n_lss_sync <<= 2; > + if (mmc->uhs2_caps.n_lss_dir == 0) > + mmc->uhs2_caps.n_lss_dir = 16 << 3; > + else > + mmc->uhs2_caps.n_lss_dir <<= 3; > + > + /* LINK/TRAN Caps */ > + mmc->uhs2_caps.link_rev = caps_tran[0] & SDHCI_UHS2_CAPS_TRAN_LINK_REV_MASK; > + mmc->uhs2_caps.n_fcu = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_N_FCU_MASK, caps_tran[0]); > + if (mmc->uhs2_caps.n_fcu == 0) > + mmc->uhs2_caps.n_fcu = 256; > + mmc->uhs2_caps.host_type = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_HOST_TYPE_MASK, caps_tran[0]); > + mmc->uhs2_caps.maxblk_len = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_BLK_LEN_MASK, caps_tran[0]); > + mmc->uhs2_caps.n_data_gap = caps_tran[1] & SDHCI_UHS2_CAPS_TRAN_1_N_DATA_GAP_MASK; > + > + return 0; > +} > + > +static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc) > +{ > + struct sdhci_host *host = mmc_priv(mmc); > + int ret = -EIO; > + > + DBG("Begin do uhs2 detect init.\n"); > + > + if (sdhci_uhs2_interface_detect(host)) { > + pr_warn("%s: cannot detect UHS2 interface.\n", > + mmc_hostname(host->mmc)); > + goto out; Might as well be return -EIO; > + } > + > + if (sdhci_uhs2_init(host)) { > + pr_warn("%s: UHS2 init fail.\n", mmc_hostname(host->mmc)); > + goto out; Might as well be return -EIO; > + } > + > + /* Init complete, do soft reset and enable UHS2 error irqs. */ > + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); > + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK); > + /* > + * N.B SDHCI_INT_ENABLE and SDHCI_SIGNAL_ENABLE was cleared > + * by SDHCI_UHS2_SW_RESET_SD > + */ > + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); > + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); > + > + ret = 0; > +out: > + return ret; Might as well be return 0; so "out:" and ret not needed. > +} > + > static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) > { > host->mmc_host_ops.start_signal_voltage_switch =
Hi, Adrian On Wed, Apr 12, 2023 at 9:13 PM Adrian Hunter <adrian.hunter@intel.com> wrote: > > On 31/03/23 13:55, Victor Shih wrote: > > Sdhci_uhs2_do_detect_init() is a sdhci version of mmc's uhs2_detect_init > > operation. After detected, the host's UHS-II capabilities will be set up > > here and interrupts will also be enabled. > > > > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> > > Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> > > Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw> > > --- > > drivers/mmc/host/sdhci-uhs2.c | 117 ++++++++++++++++++++++++++++++++++ > > 1 file changed, 117 insertions(+) > > > > diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c > > index 9b519bd6d76e..e2972be1889f 100644 > > --- a/drivers/mmc/host/sdhci-uhs2.c > > +++ b/drivers/mmc/host/sdhci-uhs2.c > > @@ -334,6 +334,123 @@ static int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) > > * * > > \*****************************************************************************/ > > > > +static int sdhci_uhs2_interface_detect(struct sdhci_host *host) > > +{ > > + /* 100ms */ > > + int timeout = 100000; > > + u32 val; > > + > > + udelay(200); /* wait for 200us before check */ > > There does not seem to be any need for this function > to be atomic, so this should use usleep_range() not udelay(). > I will update it to the V8 version. > > + > > + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_IF_DETECT), > > + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { > > Does not need to be atomic > I will update it to the V8 version. > > + pr_warn("%s: not detect UHS2 interface in 200us.\n", mmc_hostname(host->mmc)); > > + sdhci_dumpregs(host); > > + return -EIO; > > + } > > + > > + /* Enable UHS2 error interrupts */ > > + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK); > > + > > + /* 150ms */ > > + timeout = 150000; > > + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_LANE_SYNC), > > Does not need to be atomic > I will update it to the V8 version. > > + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { > > + pr_warn("%s: UHS2 Lane sync fail in 150ms.\n", mmc_hostname(host->mmc)); > > + sdhci_dumpregs(host); > > + return -EIO; > > + } > > + > > + DBG("%s: UHS2 Lane synchronized in UHS2 mode, PHY is initialized.\n", > > + mmc_hostname(host->mmc)); > > + return 0; > > +} > > + > > +static int sdhci_uhs2_init(struct sdhci_host *host) > > +{ > > + u16 caps_ptr = 0; > > + u32 caps_gen = 0; > > + u32 caps_phy = 0; > > + u32 caps_tran[2] = {0, 0}; > > + struct mmc_host *mmc = host->mmc; > > + > > + caps_ptr = sdhci_readw(host, SDHCI_UHS2_CAPS_PTR); > > + if (caps_ptr < 0x100 || caps_ptr > 0x1FF) { > > + pr_err("%s: SDHCI_UHS2_CAPS_PTR(%d) is wrong.\n", > > + mmc_hostname(mmc), caps_ptr); > > + return -ENODEV; > > + } > > + caps_gen = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_OFFSET); > > + caps_phy = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_PHY_OFFSET); > > + caps_tran[0] = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_OFFSET); > > + caps_tran[1] = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_1_OFFSET); > > + > > + /* General Caps */ > > + mmc->uhs2_caps.dap = caps_gen & SDHCI_UHS2_CAPS_DAP_MASK; > > + mmc->uhs2_caps.gap = FIELD_GET(SDHCI_UHS2_CAPS_GAP_MASK, caps_gen); > > + mmc->uhs2_caps.n_lanes = FIELD_GET(SDHCI_UHS2_CAPS_LANE_MASK, caps_gen); > > + mmc->uhs2_caps.addr64 = (caps_gen & SDHCI_UHS2_CAPS_ADDR_64) ? 1 : 0; > > + mmc->uhs2_caps.card_type = FIELD_GET(SDHCI_UHS2_CAPS_DEV_TYPE_MASK, caps_gen); > > + > > + /* PHY Caps */ > > + mmc->uhs2_caps.phy_rev = caps_phy & SDHCI_UHS2_CAPS_PHY_REV_MASK; > > + mmc->uhs2_caps.speed_range = FIELD_GET(SDHCI_UHS2_CAPS_PHY_RANGE_MASK, caps_phy); > > + mmc->uhs2_caps.n_lss_sync = FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_SYN_MASK, caps_phy); > > + mmc->uhs2_caps.n_lss_dir = FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_DIR_MASK, caps_phy); > > + if (mmc->uhs2_caps.n_lss_sync == 0) > > + mmc->uhs2_caps.n_lss_sync = 16 << 2; > > + else > > + mmc->uhs2_caps.n_lss_sync <<= 2; > > + if (mmc->uhs2_caps.n_lss_dir == 0) > > + mmc->uhs2_caps.n_lss_dir = 16 << 3; > > + else > > + mmc->uhs2_caps.n_lss_dir <<= 3; > > + > > + /* LINK/TRAN Caps */ > > + mmc->uhs2_caps.link_rev = caps_tran[0] & SDHCI_UHS2_CAPS_TRAN_LINK_REV_MASK; > > + mmc->uhs2_caps.n_fcu = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_N_FCU_MASK, caps_tran[0]); > > + if (mmc->uhs2_caps.n_fcu == 0) > > + mmc->uhs2_caps.n_fcu = 256; > > + mmc->uhs2_caps.host_type = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_HOST_TYPE_MASK, caps_tran[0]); > > + mmc->uhs2_caps.maxblk_len = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_BLK_LEN_MASK, caps_tran[0]); > > + mmc->uhs2_caps.n_data_gap = caps_tran[1] & SDHCI_UHS2_CAPS_TRAN_1_N_DATA_GAP_MASK; > > + > > + return 0; > > +} > > + > > +static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc) > > +{ > > + struct sdhci_host *host = mmc_priv(mmc); > > + int ret = -EIO; > > + > > + DBG("Begin do uhs2 detect init.\n"); > > + > > + if (sdhci_uhs2_interface_detect(host)) { > > + pr_warn("%s: cannot detect UHS2 interface.\n", > > + mmc_hostname(host->mmc)); > > + goto out; > > Might as well be > > return -EIO; > I will update it to the V8 version. > > + } > > + > > + if (sdhci_uhs2_init(host)) { > > + pr_warn("%s: UHS2 init fail.\n", mmc_hostname(host->mmc)); > > + goto out; > > Might as well be > > return -EIO; > I will update it to the V8 version. > > + } > > + > > + /* Init complete, do soft reset and enable UHS2 error irqs. */ > > + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); > > + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK); > > + /* > > + * N.B SDHCI_INT_ENABLE and SDHCI_SIGNAL_ENABLE was cleared > > + * by SDHCI_UHS2_SW_RESET_SD > > + */ > > + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); > > + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); > > + > > + ret = 0; > > +out: > > + return ret; > > Might as well be > > return 0; > > so "out:" and ret not needed. > I will update it to the V8 version. > > +} > > + > > static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) > > { > > host->mmc_host_ops.start_signal_voltage_switch = > Thanks, Victor Shih
diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 9b519bd6d76e..e2972be1889f 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -334,6 +334,123 @@ static int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) * * \*****************************************************************************/ +static int sdhci_uhs2_interface_detect(struct sdhci_host *host) +{ + /* 100ms */ + int timeout = 100000; + u32 val; + + udelay(200); /* wait for 200us before check */ + + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_IF_DETECT), + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { + pr_warn("%s: not detect UHS2 interface in 200us.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + + /* Enable UHS2 error interrupts */ + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK); + + /* 150ms */ + timeout = 150000; + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_LANE_SYNC), + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { + pr_warn("%s: UHS2 Lane sync fail in 150ms.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + + DBG("%s: UHS2 Lane synchronized in UHS2 mode, PHY is initialized.\n", + mmc_hostname(host->mmc)); + return 0; +} + +static int sdhci_uhs2_init(struct sdhci_host *host) +{ + u16 caps_ptr = 0; + u32 caps_gen = 0; + u32 caps_phy = 0; + u32 caps_tran[2] = {0, 0}; + struct mmc_host *mmc = host->mmc; + + caps_ptr = sdhci_readw(host, SDHCI_UHS2_CAPS_PTR); + if (caps_ptr < 0x100 || caps_ptr > 0x1FF) { + pr_err("%s: SDHCI_UHS2_CAPS_PTR(%d) is wrong.\n", + mmc_hostname(mmc), caps_ptr); + return -ENODEV; + } + caps_gen = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_OFFSET); + caps_phy = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_PHY_OFFSET); + caps_tran[0] = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_OFFSET); + caps_tran[1] = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_1_OFFSET); + + /* General Caps */ + mmc->uhs2_caps.dap = caps_gen & SDHCI_UHS2_CAPS_DAP_MASK; + mmc->uhs2_caps.gap = FIELD_GET(SDHCI_UHS2_CAPS_GAP_MASK, caps_gen); + mmc->uhs2_caps.n_lanes = FIELD_GET(SDHCI_UHS2_CAPS_LANE_MASK, caps_gen); + mmc->uhs2_caps.addr64 = (caps_gen & SDHCI_UHS2_CAPS_ADDR_64) ? 1 : 0; + mmc->uhs2_caps.card_type = FIELD_GET(SDHCI_UHS2_CAPS_DEV_TYPE_MASK, caps_gen); + + /* PHY Caps */ + mmc->uhs2_caps.phy_rev = caps_phy & SDHCI_UHS2_CAPS_PHY_REV_MASK; + mmc->uhs2_caps.speed_range = FIELD_GET(SDHCI_UHS2_CAPS_PHY_RANGE_MASK, caps_phy); + mmc->uhs2_caps.n_lss_sync = FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_SYN_MASK, caps_phy); + mmc->uhs2_caps.n_lss_dir = FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_DIR_MASK, caps_phy); + if (mmc->uhs2_caps.n_lss_sync == 0) + mmc->uhs2_caps.n_lss_sync = 16 << 2; + else + mmc->uhs2_caps.n_lss_sync <<= 2; + if (mmc->uhs2_caps.n_lss_dir == 0) + mmc->uhs2_caps.n_lss_dir = 16 << 3; + else + mmc->uhs2_caps.n_lss_dir <<= 3; + + /* LINK/TRAN Caps */ + mmc->uhs2_caps.link_rev = caps_tran[0] & SDHCI_UHS2_CAPS_TRAN_LINK_REV_MASK; + mmc->uhs2_caps.n_fcu = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_N_FCU_MASK, caps_tran[0]); + if (mmc->uhs2_caps.n_fcu == 0) + mmc->uhs2_caps.n_fcu = 256; + mmc->uhs2_caps.host_type = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_HOST_TYPE_MASK, caps_tran[0]); + mmc->uhs2_caps.maxblk_len = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_BLK_LEN_MASK, caps_tran[0]); + mmc->uhs2_caps.n_data_gap = caps_tran[1] & SDHCI_UHS2_CAPS_TRAN_1_N_DATA_GAP_MASK; + + return 0; +} + +static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + int ret = -EIO; + + DBG("Begin do uhs2 detect init.\n"); + + if (sdhci_uhs2_interface_detect(host)) { + pr_warn("%s: cannot detect UHS2 interface.\n", + mmc_hostname(host->mmc)); + goto out; + } + + if (sdhci_uhs2_init(host)) { + pr_warn("%s: UHS2 init fail.\n", mmc_hostname(host->mmc)); + goto out; + } + + /* Init complete, do soft reset and enable UHS2 error irqs. */ + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK); + /* + * N.B SDHCI_INT_ENABLE and SDHCI_SIGNAL_ENABLE was cleared + * by SDHCI_UHS2_SW_RESET_SD + */ + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + + ret = 0; +out: + return ret; +} + static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) { host->mmc_host_ops.start_signal_voltage_switch =