Message ID | 20230416190950.18929-1-avolmat@me.com |
---|---|
State | Accepted |
Commit | ae087ca2b3931f23218b162a30ae542259f88846 |
Headers | show |
Series | dt-bindings: irqchip: sti: remove stih415/stih416 and stid127 | expand |
On Sun, 16 Apr 2023 21:09:50 +0200, Alain Volmat wrote: > Remove bindings for the stih415/stih416/stid127 since they are > not supported within the kernel anymore. > > Signed-off-by: Alain Volmat <avolmat@me.com> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > Patch sent previously via serie: https://lore.kernel.org/all/20230209091659.1409-5-avolmat@me.com/ > .../bindings/interrupt-controller/st,sti-irq-syscfg.txt | 9 ++------- > 1 file changed, 2 insertions(+), 7 deletions(-) > Applied, thanks!
diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt b/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt index ced6014061a3..977d7ed3670e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt @@ -6,11 +6,7 @@ and PL310 L2 Cache IRQs are controlled using System Configuration registers. This driver is used to unmask them prior to use. Required properties: -- compatible : Should be set to one of: - "st,stih415-irq-syscfg" - "st,stih416-irq-syscfg" - "st,stih407-irq-syscfg" - "st,stid127-irq-syscfg" +- compatible : Should be "st,stih407-irq-syscfg" - st,syscfg : Phandle to Cortex-A9 IRQ system config registers - st,irq-device : Array of IRQs to enable - should be 2 in length - st,fiq-device : Array of FIQs to enable - should be 2 in length @@ -25,11 +21,10 @@ Optional properties: Example: irq-syscfg { - compatible = "st,stih416-irq-syscfg"; + compatible = "st,stih407-irq-syscfg"; st,syscfg = <&syscfg_cpu>; st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, <ST_IRQ_SYSCFG_PMU_1>; st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, <ST_IRQ_SYSCFG_DISABLED>; - st,invert-ext = <(ST_IRQ_SYSCFG_EXT_1_INV | ST_IRQ_SYSCFG_EXT_3_INV)>; };