| Message ID | 20230417053355.25691-4-quic_devipriy@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Incremental patches on minimal boot support | expand |
On 4/19/2023 4:24 PM, Konrad Dybcio wrote: > > > On 17.04.2023 07:33, Devi Priya wrote: >> Drop the unused backup source bias_pll_ubi_nc_clk. >> Also, update the size of GICC and GICV region to 8kB and add target CPU >> encoding. > These things have too big and too distant consequences to go in > a single patch and the GIC fix should have a fixes tag. > >> >> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 13 +++---------- >> 1 file changed, 3 insertions(+), 10 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index 3bb7435f5e7f..f1f959b43180 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -16,12 +16,6 @@ >> #size-cells = <2>; >> >> clocks { >> - bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { >> - compatible = "fixed-clock"; >> - clock-frequency = <353000000>; >> - #clock-cells = <0>; >> - }; >> - >> sleep_clk: sleep-clk { >> compatible = "fixed-clock"; >> #clock-cells = <0>; >> @@ -131,7 +125,6 @@ >> reg = <0x01800000 0x80000>; >> clocks = <&xo_board_clk>, >> <&sleep_clk>, >> - <&bias_pll_ubi_nc_clk>, > NAK, this is an ABI break. If you want to drop it, you'd need > to leave a <0> here. Okay, Got it. Thanks, Devi Priya > > Konrad >> <0>, >> <0>, >> <0>, >> @@ -172,14 +165,14 @@ >> intc: interrupt-controller@b000000 { >> compatible = "qcom,msm-qgic2"; >> reg = <0x0b000000 0x1000>, /* GICD */ >> - <0x0b002000 0x1000>, /* GICC */ >> + <0x0b002000 0x2000>, /* GICC */ >> <0x0b001000 0x1000>, /* GICH */ >> - <0x0b004000 0x1000>; /* GICV */ >> + <0x0b004000 0x2000>; /* GICV */ >> #address-cells = <1>; >> #size-cells = <1>; >> interrupt-controller; >> #interrupt-cells = <3>; >> - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; >> ranges = <0 0x0b00c000 0x3000>; >> >> v2m0: v2m@0 {
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 3bb7435f5e7f..f1f959b43180 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -16,12 +16,6 @@ #size-cells = <2>; clocks { - bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { - compatible = "fixed-clock"; - clock-frequency = <353000000>; - #clock-cells = <0>; - }; - sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -131,7 +125,6 @@ reg = <0x01800000 0x80000>; clocks = <&xo_board_clk>, <&sleep_clk>, - <&bias_pll_ubi_nc_clk>, <0>, <0>, <0>, @@ -172,14 +165,14 @@ intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */ - <0x0b002000 0x1000>, /* GICC */ + <0x0b002000 0x2000>, /* GICC */ <0x0b001000 0x1000>, /* GICH */ - <0x0b004000 0x1000>; /* GICV */ + <0x0b004000 0x2000>; /* GICV */ #address-cells = <1>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <3>; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; ranges = <0 0x0b00c000 0x3000>; v2m0: v2m@0 {
Drop the unused backup source bias_pll_ubi_nc_clk. Also, update the size of GICC and GICV region to 8kB and add target CPU encoding. Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-)