| Message ID | 20230426185647.180166-1-robimarko@gmail.com |
|---|---|
| State | Accepted |
| Commit | cb0c14dae63fae037db41174fc95a59dea0ecf77 |
| Headers | show |
| Series | arm64: dts: qcom: ipq8074: Add QUP5 SPI node | expand |
On Mon, 1 May 2023 at 12:03, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 26/04/2023 20:56, Robert Marko wrote: > > Add node to support the QUP5 SPI controller inside of IPQ8074. > > Some devices use this bus in order to manage external switches. > > > > Signed-off-by: Robert Marko <robimarko@gmail.com> > > --- > > arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++ > > 1 file changed, 14 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi > > index 64c2a30d9c25..4a682e3442f8 100644 > > --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi > > +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi > > @@ -774,6 +774,20 @@ blsp1_i2c5: i2c@78b9000 { > > status = "disabled"; > > }; > > > > + blsp1_spi5: spi@78b9000 { > > + compatible = "qcom,spi-qup-v2.2.1"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x78b9000 0x600>; > > reg is always after compatible. I agree usually, but here its just matching the same pattern like other BLSP nodes. Regards, Robert > > Best regards, > Krzysztof >
On Wed, 26 Apr 2023 20:56:47 +0200, Robert Marko wrote: > Add node to support the QUP5 SPI controller inside of IPQ8074. > Some devices use this bus in order to manage external switches. > > Applied, thanks! [1/1] arm64: dts: qcom: ipq8074: Add QUP5 SPI node commit: cb0c14dae63fae037db41174fc95a59dea0ecf77 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 64c2a30d9c25..4a682e3442f8 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -774,6 +774,20 @@ blsp1_i2c5: i2c@78b9000 { status = "disabled"; }; + blsp1_spi5: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b9000 0x600>; + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 20>, <&blsp_dma 21>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + blsp1_i2c6: i2c@78ba000 { compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>;
Add node to support the QUP5 SPI controller inside of IPQ8074. Some devices use this bus in order to manage external switches. Signed-off-by: Robert Marko <robimarko@gmail.com> --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)