diff mbox series

arm64: dts: imx8mp: Fix video clock parents

Message ID 20230512010423.1227793-1-aford173@gmail.com
State Accepted
Commit 07bb2e368820a4de9b4b586691e143976b74ea44
Headers show
Series arm64: dts: imx8mp: Fix video clock parents | expand

Commit Message

Adam Ford May 12, 2023, 1:04 a.m. UTC 
There are a few clocks whose parents are set in mipi_dsi
and lcdif nodes, but these clocks are used by the media_blk_ctrl
power domain.  This may cause an issue when re-parenting, because
the media_blk_ctrl may start the clocks before the reparent is
done resulting in a disp_pixel clock having the wrong parent and
rate.

Fix this by moving the assigned-clock-parents and rates to the
media_blk_ctrl node to configure these clocks before they are enabled.

After this patch, both disp1_pix_root and dixp2_pix_root clock
become children of the video_pll1.

video_pll1_ref_sel           24000000
  video_pll1               1039500000
    video_pll1_bypass        1039500000
      video_pll1_out           1039500000
        media_disp2_pix          1039500000
          media_disp2_pix_root_clk   1039500000
        media_disp1_pix          1039500000
          media_disp1_pix_root_clk   1039500000

Fixes: eda09fe149df ("arm64: dts: imx8mp: Add display pipeline components")
Signed-off-by: Adam Ford <aford173@gmail.com>

Comments

Shawn Guo May 15, 2023, 3:16 a.m. UTC | #1 
On Thu, May 11, 2023 at 08:04:23PM -0500, Adam Ford wrote:
> There are a few clocks whose parents are set in mipi_dsi
> and lcdif nodes, but these clocks are used by the media_blk_ctrl
> power domain.  This may cause an issue when re-parenting, because
> the media_blk_ctrl may start the clocks before the reparent is
> done resulting in a disp_pixel clock having the wrong parent and
> rate.
> 
> Fix this by moving the assigned-clock-parents and rates to the
> media_blk_ctrl node to configure these clocks before they are enabled.
> 
> After this patch, both disp1_pix_root and dixp2_pix_root clock
> become children of the video_pll1.
> 
> video_pll1_ref_sel           24000000
>   video_pll1               1039500000
>     video_pll1_bypass        1039500000
>       video_pll1_out           1039500000
>         media_disp2_pix          1039500000
>           media_disp2_pix_root_clk   1039500000
>         media_disp1_pix          1039500000
>           media_disp1_pix_root_clk   1039500000
> 
> Fixes: eda09fe149df ("arm64: dts: imx8mp: Add display pipeline components")
> Signed-off-by: Adam Ford <aford173@gmail.com>

Applied, thanks!
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index f81391993354..428c60462e3d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1211,13 +1211,6 @@  lcdif1: display-controller@32e80000 {
 					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
 					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
 				clock-names = "pix", "axi", "disp_axi";
-				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
-						  <&clk IMX8MP_CLK_MEDIA_AXI>,
-						  <&clk IMX8MP_CLK_MEDIA_APB>;
-				assigned-clock-parents = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
-							 <&clk IMX8MP_SYS_PLL2_1000M>,
-							 <&clk IMX8MP_SYS_PLL1_800M>;
-				assigned-clock-rates = <594000000>, <500000000>, <200000000>;
 				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
 				status = "disabled";
@@ -1237,11 +1230,6 @@  lcdif2: display-controller@32e90000 {
 					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
 					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
 				clock-names = "pix", "axi", "disp_axi";
-				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
-						  <&clk IMX8MP_VIDEO_PLL1>;
-				assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,
-							 <&clk IMX8MP_VIDEO_PLL1_REF_SEL>;
-				assigned-clock-rates = <0>, <1039500000>;
 				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
 				status = "disabled";
 
@@ -1296,11 +1284,16 @@  media_blk_ctrl: blk-ctrl@32ec0000 {
 					      "disp1", "disp2", "isp", "phy";
 
 				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
-						  <&clk IMX8MP_CLK_MEDIA_APB>;
+						  <&clk IMX8MP_CLK_MEDIA_APB>,
+						  <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
+						  <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
+						  <&clk IMX8MP_VIDEO_PLL1>;
 				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
-							 <&clk IMX8MP_SYS_PLL1_800M>;
-				assigned-clock-rates = <500000000>, <200000000>;
-
+							 <&clk IMX8MP_SYS_PLL1_800M>,
+							 <&clk IMX8MP_VIDEO_PLL1_OUT>,
+							 <&clk IMX8MP_VIDEO_PLL1_OUT>;
+				assigned-clock-rates = <500000000>, <200000000>,
+						       <0>, <0>, <1039500000>;
 				#power-domain-cells = <1>;
 
 				lvds_bridge: bridge@5c {