| Message ID | 20230518112750.57924-6-minda.chen@starfivetech.com |
|---|---|
| State | Accepted |
| Commit | 5aa735a4742c5ffff2fe34f764cbcbd917e100ae |
| Headers | show |
| Series | [v6,1/7] dt-bindings: phy: Add StarFive JH7110 USB PHY | expand |
On Thu, May 18, 2023 at 07:27:48PM +0800, Minda Chen wrote: > StarFive JH7110 platforms USB have a wrapper module around > the Cadence USBSS-DRD controller. Add binding information doc > for that. > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> > Reviewed-by: Peter Chen <peter.chen@kernel.org> > Reviewed-by: Hal Feng <hal.feng@starfivetech.com> > --- > .../bindings/usb/starfive,jh7110-usb.yaml | 115 ++++++++++++++++++ > 1 file changed, 115 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml > > diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml > new file mode 100644 > index 000000000000..24aa9c10d6ab > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml > @@ -0,0 +1,115 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller I think you told Krzysztof you'd rename this to "StarFive JH7110 Cadence USBSS-DRD SoC controller"? Otherwise, it looks like all the stuff from him and Rob have been sorted out, so other than $title this is Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor..
On 2023/5/26 5:34, Conor Dooley wrote: > On Thu, May 18, 2023 at 07:27:48PM +0800, Minda Chen wrote: >> StarFive JH7110 platforms USB have a wrapper module around >> the Cadence USBSS-DRD controller. Add binding information doc >> for that. >> >> Signed-off-by: Minda Chen <minda.chen@starfivetech.com> >> Reviewed-by: Peter Chen <peter.chen@kernel.org> >> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> >> --- >> .../bindings/usb/starfive,jh7110-usb.yaml | 115 ++++++++++++++++++ >> 1 file changed, 115 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml >> >> diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml >> new file mode 100644 >> index 000000000000..24aa9c10d6ab >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml >> @@ -0,0 +1,115 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller > > I think you told Krzysztof you'd rename this to "StarFive JH7110 Cadence > USBSS-DRD SoC controller"? > The previous title describe whole USB controller for previous dts node is merged. Now the dts node is split. "starfive,jh7110-usb" just contain starfive wrapper layer dts configuration. > Otherwise, it looks like all the stuff from him and Rob have been sorted > out, so other than $title this is > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Thanks, > Conor.. Thanks
On Fri, May 26, 2023 at 06:24:48PM +0800, Minda Chen wrote: > >> +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller > > > > I think you told Krzysztof you'd rename this to "StarFive JH7110 Cadence > > USBSS-DRD SoC controller"? > > > The previous title describe whole USB controller for previous dts node is > merged. Now the dts node is split. > "starfive,jh7110-usb" just contain starfive wrapper layer dts configuration. Okay, I must have misunderstood the conversation on the previous version. Sorry about that. > > Otherwise, it looks like all the stuff from him and Rob have been sorted > > out, so other than $title this is > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml new file mode 100644 index 000000000000..24aa9c10d6ab --- /dev/null +++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller + +maintainers: + - Minda Chen <minda.chen@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-usb + + ranges: true + + starfive,stg-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller stg_syscon node. + - description: dr mode register offset of STG_SYSCONSAIF__SYSCFG register for USB. + description: + The phandle to System Register Controller syscon node and the offset + of STG_SYSCONSAIF__SYSCFG register for USB. + + dr_mode: + enum: [host, otg, peripheral] + + "#address-cells": + enum: [1, 2] + + "#size-cells": + enum: [1, 2] + + clocks: + items: + - description: link power management clock + - description: standby clock + - description: APB clock + - description: AXI clock + - description: UTMI APB clock + + clock-names: + items: + - const: lpm + - const: stb + - const: apb + - const: axi + - const: utmi_apb + + resets: + items: + - description: Power up reset + - description: APB clock reset + - description: AXI clock reset + - description: UTMI APB clock reset + + reset-names: + items: + - const: pwrup + - const: apb + - const: axi + - const: utmi_apb + +patternProperties: + "^usb@[0-9a-f]+$": + $ref: cdns,usb3.yaml# + description: Required child node + +required: + - compatible + - ranges + - starfive,stg-syscon + - '#address-cells' + - '#size-cells' + - dr_mode + - clocks + - resets + +additionalProperties: false + +examples: + - | + usb@10100000 { + compatible = "starfive,jh7110-usb"; + ranges = <0x0 0x10100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + starfive,stg-syscon = <&stg_syscon 0x4>; + clocks = <&syscrg 4>, + <&stgcrg 5>, + <&stgcrg 1>, + <&stgcrg 3>, + <&stgcrg 2>; + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; + resets = <&stgcrg 10>, + <&stgcrg 8>, + <&stgcrg 7>, + <&stgcrg 9>; + reset-names = "pwrup", "apb", "axi", "utmi_apb"; + dr_mode = "host"; + + usb@0 { + compatible = "cdns,usb3"; + reg = <0x0 0x10000>, + <0x10000 0x10000>, + <0x20000 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <100>, <108>, <110>; + interrupt-names = "host", "peripheral", "otg"; + maximum-speed = "super-speed"; + }; + };