| Message ID | 20230519155602.6642-5-quic_jkona@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/4] clk: qcom: clk-alpha-pll: Add support for rivian ole pll ops | expand |
Hi Konrad, Thanks for your review! On 5/19/2023 10:22 PM, Konrad Dybcio wrote: > > > On 19.05.2023 17:56, Jagadeesh Kona wrote: >> Add device node for camera clock controller on Qualcomm >> SM8550 platform. >> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++++ >> 1 file changed, 15 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi >> index e67e7c69dae6..ac82d3774ed8 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi >> @@ -4,6 +4,7 @@ >> */ >> >> #include <dt-bindings/clock/qcom,rpmh.h> >> +#include <dt-bindings/clock/qcom,sm8550-camcc.h> >> #include <dt-bindings/clock/qcom,sm8550-gcc.h> >> #include <dt-bindings/clock/qcom,sm8550-tcsr.h> >> #include <dt-bindings/clock/qcom,sm8550-dispcc.h> >> @@ -2397,6 +2398,20 @@ opp-202000000 { >> }; >> }; >> >> + camcc: clock-controller@ade0000 { >> + compatible = "qcom,sm8550-camcc"; >> + reg = <0 0xade0000 0 0x20000>; > Please pad the non-zero address part to 8 hex digits > Will take care of this in next series. > Konrad >> + clocks = <&bi_tcxo_div2>, >> + <&bi_tcxo_ao_div2>, >> + <&sleep_clk>, >> + <&gcc GCC_CAMERA_AHB_CLK>; >> + power-domains = <&rpmhpd SM8550_MMCX>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> mdss: display-subsystem@ae00000 { >> compatible = "qcom,sm8550-mdss"; >> reg = <0 0x0ae00000 0 0x1000>; Thanks & Regards, Jagadeesh
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index e67e7c69dae6..ac82d3774ed8 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm8550-camcc.h> #include <dt-bindings/clock/qcom,sm8550-gcc.h> #include <dt-bindings/clock/qcom,sm8550-tcsr.h> #include <dt-bindings/clock/qcom,sm8550-dispcc.h> @@ -2397,6 +2398,20 @@ opp-202000000 { }; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8550-camcc"; + reg = <0 0xade0000 0 0x20000>; + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>, + <&gcc GCC_CAMERA_AHB_CLK>; + power-domains = <&rpmhpd SM8550_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,sm8550-mdss"; reg = <0 0x0ae00000 0 0x1000>;