diff mbox series

arm64: dts: qcom: sc8180x: Fix adreno smmu compatible

Message ID 20230612220532.1884860-1-quic_bjorande@quicinc.com
State Accepted
Commit e537d5ef47097360d8df524c748f3df451383dcd
Headers show
Series arm64: dts: qcom: sc8180x: Fix adreno smmu compatible | expand

Commit Message

Bjorn Andersson June 12, 2023, 10:05 p.m. UTC
The adreno smmu should be compatible with qcom,adreno-smmu as well for
per-process page tables to work.

Fixes: 8575f197b077 ("arm64: dts: qcom: Introduce the SC8180x platform")
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc8180x.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Dmitry Baryshkov June 12, 2023, 10:34 p.m. UTC | #1
On 13/06/2023 01:05, Bjorn Andersson wrote:
> The adreno smmu should be compatible with qcom,adreno-smmu as well for
> per-process page tables to work.
> 
> Fixes: 8575f197b077 ("arm64: dts: qcom: Introduce the SC8180x platform")
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> ---
>   arch/arm64/boot/dts/qcom/sc8180x.dtsi | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Bjorn Andersson June 13, 2023, 10:30 p.m. UTC | #2
On Mon, 12 Jun 2023 15:05:32 -0700, Bjorn Andersson wrote:
> The adreno smmu should be compatible with qcom,adreno-smmu as well for
> per-process page tables to work.
> 
> 

Applied, thanks!

[1/1] arm64: dts: qcom: sc8180x: Fix adreno smmu compatible
      commit: e537d5ef47097360d8df524c748f3df451383dcd

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index e8613a00fcab..88015742315b 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -2310,7 +2310,8 @@  gpucc: clock-controller@2c90000 {
 		};
 
 		adreno_smmu: iommu@2ca0000 {
-			compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
+			compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
+				     "qcom,smmu-500", "arm,mmu-500";
 			reg = <0 0x02ca0000 0 0x10000>;
 			#iommu-cells = <2>;
 			#global-interrupts = <1>;