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[v4,0/8] Add minimal boot support for IPQ5018

Message ID 20230510134121.1232286-1-quic_srichara@quicinc.com
Headers show
Series Add minimal boot support for IPQ5018 | expand

Message

Sricharan R May 10, 2023, 1:41 p.m. UTC 
The IPQ5018 is Qualcomm's 802.11ax SoC for Routers,
Gateways and Access Points.

This series adds minimal board boot support for ipq5018-mp03.1-c2 board.

[v4]
       Fixed all comments for clocks, schema, dts
       Added Reviewed-by tags.

[v3]
	Fixed all comments for clocks, schema fixes
        Picked up Reviewed-by from Bjorn for pinctrl driver

[v2]
	Fixed all comments and rebased for TOT.

Sricharan Ramabadhran (8):
  dt-bindings: arm64: Add IPQ5018 clock and reset
  clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018
  dt-bindings: pinctrl: qcom: Add support for ipq5018
  pinctrl: qcom: Add IPQ5018 pinctrl driver
  dt-bindings: qcom: Add ipq5018 bindings
  dt-bindings: firmware: document IPQ5018 SCM
  arm64: dts: Add ipq5018 SoC and rdp432-c2 board support
  arm64: defconfig: Enable IPQ5018 SoC base configs

 .../devicetree/bindings/arm/qcom.yaml         |    7 +
 .../bindings/clock/qcom,ipq5018-gcc.yaml      |   63 +
 .../bindings/firmware/qcom,scm.yaml           |    1 +
 .../bindings/pinctrl/qcom,ipq5018-tlmm.yaml   |  127 +
 arch/arm64/boot/dts/qcom/Makefile             |    1 +
 .../arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts |   72 +
 arch/arm64/boot/dts/qcom/ipq5018.dtsi         |  250 ++
 arch/arm64/configs/defconfig                  |    3 +
 drivers/clk/qcom/Kconfig                      |   10 +-
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/gcc-ipq5018.c                | 3731 +++++++++++++++++
 drivers/pinctrl/qcom/Kconfig                  |   10 +
 drivers/pinctrl/qcom/Makefile                 |    1 +
 drivers/pinctrl/qcom/pinctrl-ipq5018.c        |  791 ++++
 include/dt-bindings/clock/qcom,gcc-ipq5018.h  |  183 +
 include/dt-bindings/reset/qcom,gcc-ipq5018.h  |  122 +
 16 files changed, 5371 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml
 create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
 create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
 create mode 100644 drivers/clk/qcom/gcc-ipq5018.c
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5018.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h
 create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h

Comments

Sricharan R May 11, 2023, 6:19 a.m. UTC | #1 
On 5/10/2023 7:54 PM, andy.shevchenko@gmail.com wrote:
> Wed, May 10, 2023 at 07:11:17PM +0530, Sricharan Ramabadhran kirjoitti:
>> Add pinctrl definitions for the TLMM of IPQ5018.
> 
> ...
> 
>> +#define FUNCTION(fname)			                \
>> +	[msm_mux_##fname] = {		                \
>> +		.name = #fname,				\
>> +		.groups = fname##_groups,               \
>> +		.ngroups = ARRAY_SIZE(fname##_groups),	\
>> +	}
> 
> Can you coordinate with Rohit Agarwal <quic_rohiagar@quicinc.com> and use
> his work [1] which moves the QCom drivers to use struct pingroup and struct
> pinfunction?
> 
> [1]: https://lore.kernel.org/r/1683718725-14869-1-git-send-email-quic_rohiagar@quicinc.com
> 

  ok, will do.

> ...
> 
>> +static const struct of_device_id ipq5018_pinctrl_of_match[] = {
>> +	{ .compatible = "qcom,ipq5018-tlmm", },
> 
>> +	{ },
> 
> No comma for the terminator entry.
> 

  ok.

>> +};
> 
> Move MODULE_DEVICE_TABLE() here.
> 

  ok

Regards,
  Sricharan
Robert Marko May 11, 2023, 10:55 a.m. UTC | #2 
> +
> +static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
> +	F(143713, P_XO, 1, 1, 167),
> +	F(400000, P_XO, 1, 1, 60),
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(48000000, P_GPLL2, 12, 1, 2),
> +	F(96000000, P_GPLL2, 12, 0, 0),
> +	F(177777778, P_GPLL0, 1, 2, 9),
> +	F(192000000, P_GPLL2, 6, 0, 0),
> +	F(200000000, P_GPLL0, 4, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 sdcc1_apps_clk_src = {
> +	.cmd_rcgr = 0x42004,
> +	.freq_tbl = ftbl_sdcc1_apps_clk_src,
> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "sdcc1_apps_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
> +		.ops = &clk_rcg2_ops,
Hi,
SDCC clocks should be using "clk_rcg2_floor_ops" to round down and avoid 
overclocking
the cards and kernel will warn about it:
[    1.016194] mmc0: Card appears overclocked; req 52000000 Hz, actual 
96000000 Hz
[    1.016278] mmc0: Card appears overclocked; req 52000000 Hz, actual 
96000000 Hz

Regards,
Robert
Sricharan R June 13, 2023, 1:16 p.m. UTC | #3 
Hi Konrad,

On 5/27/2023 12:47 AM, Konrad Dybcio wrote:
> 
> 
> On 10.05.2023 15:41, Sricharan Ramabadhran wrote:
>> Add support for the global clock controller found on IPQ5018
>> based devices.
>>
>> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
>> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
>> Co-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
>> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> ---
>>   [v4] Fixed to use ARRAY_SIZE() wherever parent_data was used
>>        Changed GPL v2 to GPL as per comments
>>
>>   drivers/clk/qcom/Kconfig       |   10 +-
>>   drivers/clk/qcom/Makefile      |    1 +
>>   drivers/clk/qcom/gcc-ipq5018.c | 3731 ++++++++++++++++++++++++++++++++
>>   3 files changed, 3740 insertions(+), 2 deletions(-)
>>   create mode 100644 drivers/clk/qcom/gcc-ipq5018.c
>>
> [...]
> 
>> +struct clk_rcg2 lpass_axim_clk_src = {
>> +	.cmd_rcgr = 0x2E028,
> Please use lowercase hex for non-macro-defines, all throughout the file.
> 

  ok. Will fix this in V10.

> [...]
> 
>> +static struct clk_rcg2 system_noc_bfdcd_clk_src = {
> Drop clocks that are managed in RPM, they will conflict.
> 

   IPQ5018 does not have RPM.

Regards,
  Sricharan
Konrad Dybcio June 13, 2023, 3:23 p.m. UTC | #4 
On 13.06.2023 15:16, Sricharan Ramabadhran wrote:
> Hi Konrad,
> 
> On 5/27/2023 12:47 AM, Konrad Dybcio wrote:
>>
>>
>> On 10.05.2023 15:41, Sricharan Ramabadhran wrote:
>>> Add support for the global clock controller found on IPQ5018
>>> based devices.
>>>
>>> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
>>> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
>>> Co-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
>>> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
>>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>>> ---
>>>   [v4] Fixed to use ARRAY_SIZE() wherever parent_data was used
>>>        Changed GPL v2 to GPL as per comments
>>>
>>>   drivers/clk/qcom/Kconfig       |   10 +-
>>>   drivers/clk/qcom/Makefile      |    1 +
>>>   drivers/clk/qcom/gcc-ipq5018.c | 3731 ++++++++++++++++++++++++++++++++
>>>   3 files changed, 3740 insertions(+), 2 deletions(-)
>>>   create mode 100644 drivers/clk/qcom/gcc-ipq5018.c
>>>
>> [...]
>>
>>> +struct clk_rcg2 lpass_axim_clk_src = {
>>> +    .cmd_rcgr = 0x2E028,
>> Please use lowercase hex for non-macro-defines, all throughout the file.
>>
> 
>  ok. Will fix this in V10.
> 
>> [...]
>>
>>> +static struct clk_rcg2 system_noc_bfdcd_clk_src = {
>> Drop clocks that are managed in RPM, they will conflict.
>>
> 
>   IPQ5018 does not have RPM.
Oh that's new. I suppose you'll be interested in clk-interconnect for
voting on bus resources then.

Konrad
> 
> Regards,
>  Sricharan