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[0/4] Add support for Qualcomm ECPRI clock controller

Message ID 20230808051407.647395-1-quic_imrashai@quicinc.com
Headers show
Series Add support for Qualcomm ECPRI clock controller | expand

Message

Imran Shaik Aug. 8, 2023, 5:14 a.m. UTC 
The ECPRI clock controller support for QDU1000 and QRU1000. The clock
controller has a special branch which requires an additional memory to
be enabled/disabled before the branch ops.

Imran Shaik (3):
  dt-bindings: clock: qcom: Add ECPRICC clocks for QDU1000 and QRU1000
  clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000
  arm64: dts: qcom: qdu1000: Add ECPRI clock controller

Taniya Das (1):
  clk: qcom: branch: Add mem ops support for branch2 clocks

 .../bindings/clock/qcom,qdu1000-ecpricc.yaml  |   68 +
 arch/arm64/boot/dts/qcom/qdu1000.dtsi         |   14 +
 drivers/clk/qcom/Kconfig                      |    8 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/clk-branch.c                 |   38 +
 drivers/clk/qcom/clk-branch.h                 |    4 +
 drivers/clk/qcom/ecpricc-qdu1000.c            | 3808 +++++++++++++++++
 .../dt-bindings/clock/qcom,qdu1000-ecpricc.h  |  192 +
 8 files changed, 4133 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml
 create mode 100644 drivers/clk/qcom/ecpricc-qdu1000.c
 create mode 100644 include/dt-bindings/clock/qcom,qdu1000-ecpricc.h

Comments

Imran Shaik Aug. 22, 2023, 11:46 a.m. UTC | #1 
On 8/10/2023 1:31 AM, Konrad Dybcio wrote:
> On 8.08.2023 07:14, Imran Shaik wrote:
>> Add ECPRI Clock Controller (ECPRICC) support for QDU1000 and QRU1000 SoCs.
>>
>> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
>> ---
> Please ensure inline hex is lowercase
> 

Sure, will update all the hex values in lowercase and push another series.

> No GDSCs in this clock controller?
> 
> Konrad

There are no GDSCs in this clock controller.

Thanks,
Imran