| Message ID | 20230830-fp5-initial-v1-1-5a954519bbad@fairphone.com |
|---|---|
| State | New |
| Headers | show |
| Series | Initial support for the Fairphone 5 smartphone | expand |
On Wed Aug 30, 2023 at 12:08 PM CEST, Konrad Dybcio wrote: > On 30.08.2023 11:58, Luca Weiss wrote: > > With the standard Qualcomm TrustZone setup, components such as lpasscc, > > pdc_reset and watchdog shouldn't be touched by Linux. Mark them with > > the status 'reserved' and reeable them in the chrome-common dtsi. > > > > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > > --- > Could probably use /* Owned by ADSP firmware */ or /* Owned by Gunyah hyp */ Do you know which one is more fitting for these nodes? I don't really have a reference to if the ADSP or Gunyah (is this even used here?) owns this. Regards Luca > > the change lgtm though > > Konrad
On 30.08.2023 12:35, Luca Weiss wrote: > On Wed Aug 30, 2023 at 12:08 PM CEST, Konrad Dybcio wrote: >> On 30.08.2023 11:58, Luca Weiss wrote: >>> With the standard Qualcomm TrustZone setup, components such as lpasscc, >>> pdc_reset and watchdog shouldn't be touched by Linux. Mark them with >>> the status 'reserved' and reeable them in the chrome-common dtsi. >>> >>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> >>> --- >> Could probably use /* Owned by ADSP firmware */ or /* Owned by Gunyah hyp */ > > Do you know which one is more fitting for these nodes? I don't really > have a reference to if the ADSP or Gunyah (is this even used here?) owns > this. ADSP owns the audio hw, Gunyah owns the wdog Konrad
diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi index 2e1cd219fc18..8eb30aa226a2 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -46,6 +46,14 @@ wpss_mem: memory@9ae00000 { }; }; +&lpasscc { + status = "okay"; +}; + +&pdc_reset { + status = "okay"; +}; + /* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */ &pmk8350_pon { status = "disabled"; @@ -84,6 +92,10 @@ &scm { dma-coherent; }; +&watchdog { + status = "okay"; +}; + &wifi { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 042908048d09..98a8d627a348 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2267,6 +2267,7 @@ lpasscc: lpasscc@3000000 { clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; clock-names = "iface"; #clock-cells = <1>; + status = "reserved"; }; lpass_rx_macro: codec@3200000 { @@ -4216,6 +4217,7 @@ pdc_reset: reset-controller@b5e0000 { compatible = "qcom,sc7280-pdc-global"; reg = <0 0x0b5e0000 0 0x20000>; #reset-cells = <1>; + status = "reserved"; }; tsens0: thermal-sensor@c263000 { @@ -5212,11 +5214,12 @@ msi-controller@17a40000 { }; }; - watchdog@17c10000 { + watchdog: watchdog@17c10000 { compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; reg = <0 0x17c10000 0 0x1000>; clocks = <&sleep_clk>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + status = "reserved"; }; timer@17c20000 {
With the standard Qualcomm TrustZone setup, components such as lpasscc, pdc_reset and watchdog shouldn't be touched by Linux. Mark them with the status 'reserved' and reeable them in the chrome-common dtsi. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> --- arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 ++++- 2 files changed, 16 insertions(+), 1 deletion(-)