| Message ID | 20231010062917.3624223-1-xianwei.zhao@amlogic.com |
|---|---|
| Headers | show |
| Series | Add C3 SoC PLLs and Peripheral clock | expand |
On Tue, 10 Oct 2023 14:29:14 +0800, Xianwei Zhao wrote: > Add the C3 PLL clock controller dt-bindings for Amlogic C3 SoC family > > Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> > --- > V1 -> V2: Fix errors when check dtbinding use "make dt_binding_check" > --- > .../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 +++++++++++++++++++ > .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 42 +++++++++++++ > 2 files changed, 101 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml > create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.example.dts:18:18: fatal error: dt-bindings/clock/amlogic,c3-peripherals-clkc.h: No such file or directory 18 | #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[2]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.example.dtb] Error 1 make[2]: *** Waiting for unfinished jobs.... make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1427: dt_binding_check] Error 2 make: *** [Makefile:234: __sub-make] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20231010062917.3624223-2-xianwei.zhao@amlogic.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Hi Rob,
Thanks for your advise.
On 2023/10/10 21:21, Rob Herring wrote:
> [ EXTERNAL EMAIL ]
>
> On Tue, Oct 10, 2023 at 02:29:14PM +0800, Xianwei Zhao wrote:
>> Add the C3 PLL clock controller dt-bindings for Amlogic C3 SoC family
>>
>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>> ---
>> V1 -> V2: Fix errors when check dtbinding use "make dt_binding_check"
>
> Your patches aren't bisectable. It's fine if you want to combine patch 1
> and 2 into 1 patch. Or just use the raw numbers here instead of the
> header.
>
I will combine patch 1 and 2 into 1 patch in V3.
>> ---
>> .../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 +++++++++++++++++++
>> .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 42 +++++++++++++
>> 2 files changed, 101 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
>> create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
>> new file mode 100644
>> index 000000000000..a646992917b7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
>> @@ -0,0 +1,59 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Amlogic C3 serials PLL Clock Controller
>
> s/serials/Serials/
>
Will fix
>> +
>> +maintainers:
>> + - Chuan Liu <chuan.liu@amlogic.com>
>> +
>> +properties:
>> + compatible:
>> + const: amlogic,c3-pll-clkc
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + minItems: 1
>> + items:
>> + - description: input pll_in
>> + - description: input mclk_pll_in
>> +
>> + clock-names:
>> + minItems: 1
>> + items:
>> + - const: pll_in
>> + - const: mclk_pll_in
>> +
>> + "#clock-cells":
>> + const: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - "#clock-cells"
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
>> + apb {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + clkc_pll: clock-controller@8000 {
>
> Drop unused labels.
>
Will delete clkc_pll.
>> + compatible = "amlogic,c3-pll-clkc";
>
> Your indentation is not consistent.
>
Will fix it in V3.
>> + reg = <0x0 0x8000 0x0 0x1a4>;
>> + clocks = <&clkc_periphs CLKID_PLL_IN>,
>> + <&clkc_periphs CLKID_MCLK_PLL_IN>;
>> + clock-names = "pll_in", "mclk_pll_in";
>> + #clock-cells = <1>;
>> + };
>> + };
>> diff --git a/include/dt-bindings/clock/amlogic,c3-pll-clkc.h b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
>> new file mode 100644
>> index 000000000000..aa731e8fae29
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
>> @@ -0,0 +1,42 @@
>> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
>> +/*
>> + * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
>> + * Author: Chuan Liu <chuan.liu@amlogic.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
>> +#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
>> +
>> +#define CLKID_FIXED_PLL_DCO 0
>> +#define CLKID_FIXED_PLL 1
>> +#define CLKID_FCLK_DIV40_DIV 2
>> +#define CLKID_FCLK_DIV40 3
>> +#define CLKID_FCLK_DIV2_DIV 4
>> +#define CLKID_FCLK_DIV2 5
>> +#define CLKID_FCLK_DIV2P5_DIV 6
>> +#define CLKID_FCLK_DIV2P5 7
>> +#define CLKID_FCLK_DIV3_DIV 8
>> +#define CLKID_FCLK_DIV3 9
>> +#define CLKID_FCLK_DIV4_DIV 10
>> +#define CLKID_FCLK_DIV4 11
>> +#define CLKID_FCLK_DIV5_DIV 12
>> +#define CLKID_FCLK_DIV5 13
>> +#define CLKID_FCLK_DIV7_DIV 14
>> +#define CLKID_FCLK_DIV7 15
>> +#define CLKID_GP0_PLL_DCO 16
>> +#define CLKID_GP0_PLL 17
>> +#define CLKID_HIFI_PLL_DCO 18
>> +#define CLKID_HIFI_PLL 19
>> +#define CLKID_MCLK_PLL_DCO 20
>> +#define CLKID_MCLK_PLL 21
>> +#define CLKID_MCLK_PLL_CLK 22
>> +#define CLKID_MCLK0_SEL 23
>> +#define CLKID_MCLK0_SEL_OUT 24
>> +#define CLKID_MCLK0_DIV 25
>> +#define CLKID_MCLK0 26
>> +#define CLKID_MCLK1_SEL 27
>> +#define CLKID_MCLK1_SEL_OUT 28
>> +#define CLKID_MCLK1_DIV 29
>> +#define CLKID_MCLK1 30
>> +
>> +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */
>>
>> base-commit: 57b55c76aaf1ba50ecc6dcee5cd6843dc4d85239
>> --
>> 2.37.1
>>
Add C3 SoC PLLs and Peripheral clock controller dt-bindings. Add PLLs and Peripheral clock controller driver for C3 SOC. V1 -> V2: 1. Fix errors when check binding by using "make dt_binding_check" 2. Delete macro definition Xianwei Zhao (4): dt-bindings: clock: add Amlogic C3 PLL clock controller bindings dt-bindings: clock: add Amlogic C3 peripherals clock controller bindings clk: meson: c3: add support for the C3 SoC PLL clock clk: meson: c3: add c3 clock peripherals controller driver .../clock/amlogic,c3-peripherals-clkc.yaml | 92 + .../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 + drivers/clk/meson/Kconfig | 25 + drivers/clk/meson/Makefile | 2 + drivers/clk/meson/c3-peripherals.c | 3096 +++++++++++++++++ drivers/clk/meson/c3-peripherals.h | 48 + drivers/clk/meson/c3-pll.c | 808 +++++ drivers/clk/meson/c3-pll.h | 35 + .../clock/amlogic,c3-peripherals-clkc.h | 230 ++ .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 42 + 10 files changed, 4437 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-peripherals-clkc.yaml create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml create mode 100644 drivers/clk/meson/c3-peripherals.c create mode 100644 drivers/clk/meson/c3-peripherals.h create mode 100644 drivers/clk/meson/c3-pll.c create mode 100644 drivers/clk/meson/c3-pll.h create mode 100644 include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h base-commit: 57b55c76aaf1ba50ecc6dcee5cd6843dc4d85239