| Message ID | 20231201160925.3136868-1-peter.griffin@linaro.org |
|---|---|
| Headers | show |
| Series | Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board | expand |
On Fri, Dec 1, 2023 at 10:10 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > Provide dt-schema documentation for Google gs101 SoC clock controller. > Currently this adds support for cmu_top, cmu_misc and cmu_apm. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- Except for my nitpicks below (very minor, can be ignored): Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > .../bindings/clock/google,gs101-clock.yaml | 110 +++++ > include/dt-bindings/clock/google,gs101.h | 392 ++++++++++++++++++ > 2 files changed, 502 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml > create mode 100644 include/dt-bindings/clock/google,gs101.h > > diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml > new file mode 100644 > index 000000000000..4612886fcc15 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml > @@ -0,0 +1,110 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Google GS101 SoC clock controller > + > +maintainers: > + - Peter Griffin <peter.griffin@linaro.org> > + > +description: | > + Google GS101 clock controller is comprised of several CMU units, generating > + clocks for different domains. Those CMU units are modeled as separate device > + tree nodes, and might depend on each other. The root clock in that clock tree > + is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate > + clock in dts. > + > + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and > + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. > + > + Each clock is assigned an identifier and client nodes can use this identifier > + to specify the clock which they consume. All clocks available for usage > + in clock consumer nodes are defined as preprocessor macros in > + 'dt-bindings/clock/gs101.h' header. > + > +properties: > + compatible: > + enum: > + - google,gs101-cmu-top > + - google,gs101-cmu-apm > + - google,gs101-cmu-misc > + > + clocks: > + minItems: 1 > + maxItems: 2 > + > + clock-names: > + minItems: 1 > + maxItems: 2 > + > + "#clock-cells": > + const: 1 > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - "#clock-cells" > + - clocks > + - clock-names > + - reg > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - google,gs101-cmu-top > + - google,gs101-cmu-apm > + then: > + properties: > + clocks: > + items: > + - description: External reference clock (24.576 MHz) > + > + clock-names: > + items: > + - const: oscclk > + > + - if: > + properties: > + compatible: > + contains: > + const: google,gs101-cmu-misc > + > + then: > + properties: > + clocks: > + items: > + - description: External reference clock (24.576 MHz) > + - description: Misc bus clock (from CMU_TOP) > + > + clock-names: > + items: > + - const: oscclk > + - const: dout_cmu_misc_bus > + > +additionalProperties: false > + > +examples: > + # Clock controller node for CMU_TOP > + - | > + #include <dt-bindings/clock/google,gs101.h> Not really needed for the particular example below, but I guess it's ok to have it here for the reference. > + soc { > + #address-cells = <2>; > + #size-cells = <1>; > + > + cmu_top: clock-controller@1e080000 { > + compatible = "google,gs101-cmu-top"; > + reg = <0x0 0x1e080000 0x8000>; Having 0x0 here doesn't match how it's done in gs101.dtsi in this series. If you remove it, then above soc node and its properties can be removed too. > + #clock-cells = <1>; > + clocks = <&ext_24_5m>; > + clock-names = "oscclk"; > + }; > + }; > + > +... > diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h > new file mode 100644 > index 000000000000..9f280f74578a > --- /dev/null > +++ b/include/dt-bindings/clock/google,gs101.h > @@ -0,0 +1,392 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (C) 2023 Linaro Ltd. > + * Author: Peter Griffin <peter.griffin@linaro.org> > + * > + * Device Tree binding constants for Google gs101 clock controller. > + */ > + > +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H > +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H > + > +/* CMU_TOP PLL */ > +#define CLK_FOUT_SHARED0_PLL 1 > +#define CLK_FOUT_SHARED1_PLL 2 > +#define CLK_FOUT_SHARED2_PLL 3 > +#define CLK_FOUT_SHARED3_PLL 4 > +#define CLK_FOUT_SPARE_PLL 5 > + > +/* CMU_TOP MUX */ > +#define CLK_MOUT_SHARED0_PLL 6 > +#define CLK_MOUT_SHARED1_PLL 7 > +#define CLK_MOUT_SHARED2_PLL 8 > +#define CLK_MOUT_SHARED3_PLL 9 > +#define CLK_MOUT_SPARE_PLL 10 > +#define CLK_MOUT_BO_BUS 11 > +#define CLK_MOUT_BUS0_BUS 12 > +#define CLK_MOUT_BUS1_BUS 13 > +#define CLK_MOUT_BUS2_BUS 14 > +#define CLK_MOUT_CIS_CLK0 15 > +#define CLK_MOUT_CIS_CLK1 16 > +#define CLK_MOUT_CIS_CLK2 17 > +#define CLK_MOUT_CIS_CLK3 18 > +#define CLK_MOUT_CIS_CLK4 19 > +#define CLK_MOUT_CIS_CLK5 20 > +#define CLK_MOUT_CIS_CLK6 21 > +#define CLK_MOUT_CIS_CLK7 22 > +#define CLK_MOUT_CMU_BOOST 23 > +#define CLK_MOUT_BOOST_OPTION1 24 > +#define CLK_MOUT_CORE_BUS 25 > +#define CLK_MOUT_CPUCL0_DBG 26 > +#define CLK_MOUT_CPUCL0_SWITCH 27 > +#define CLK_MOUT_CPUCL1_SWITCH 28 > +#define CLK_MOUT_CPUCL2_SWITCH 29 > +#define CLK_MOUT_CSIS_BUS 30 > +#define CLK_MOUT_DISP_BUS 31 > +#define CLK_MOUT_DNS_BUS 32 > +#define CLK_MOUT_DPU_BUS 33 > +#define CLK_MOUT_EH_BUS 34 > +#define CLK_MOUT_G2D_G2D 35 > +#define CLK_MOUT_G2D_MSCL 36 > +#define CLK_MOUT_G3AA_G3AA 37 > +#define CLK_MOUT_G3D_BUSD 38 > +#define CLK_MOUT_G3D_GLB 39 > +#define CLK_MOUT_G3D_SWITCH 40 > +#define CLK_MOUT_GDC_GDC0 41 > +#define CLK_MOUT_GDC_GDC1 42 > +#define CLK_MOUT_GDC_SCSC 43 > +#define CLK_MOUT_CMU_HPM 44 > +#define CLK_MOUT_HSI0_BUS 45 > +#define CLK_MOUT_HSI0_DPGTC 46 > +#define CLK_MOUT_HSI0_USB31DRD 47 > +#define CLK_MOUT_HSI0_USBDPDGB 48 > +#define CLK_MOUT_HSI1_BUS 49 > +#define CLK_MOUT_HSI1_PCIE 50 > +#define CLK_MOUT_HSI2_BUS 51 > +#define CLK_MOUT_HSI2_MMC_CARD 52 > +#define CLK_MOUT_HSI2_PCIE 53 > +#define CLK_MOUT_HSI2_UFS_EMBD 54 > +#define CLK_MOUT_IPP_BUS 55 > +#define CLK_MOUT_ITP_BUS 56 > +#define CLK_MOUT_MCSC_ITSC 57 > +#define CLK_MOUT_MCSC_MCSC 58 > +#define CLK_MOUT_MFC_MFC 59 > +#define CLK_MOUT_MIF_BUSP 60 > +#define CLK_MOUT_MIF_SWITCH 61 > +#define CLK_MOUT_MISC_BUS 62 > +#define CLK_MOUT_MISC_SSS 63 > +#define CLK_MOUT_PDP_BUS 64 > +#define CLK_MOUT_PDP_VRA 65 > +#define CLK_MOUT_PERIC0_BUS 66 > +#define CLK_MOUT_PERIC0_IP 67 > +#define CLK_MOUT_PERIC1_BUS 68 > +#define CLK_MOUT_PERIC1_IP 69 > +#define CLK_MOUT_TNR_BUS 70 > +#define CLK_MOUT_TOP_BOOST_OPTION1 71 > +#define CLK_MOUT_TOP_CMUREF 72 > +#define CLK_MOUT_TPU_BUS 73 > +#define CLK_MOUT_TPU_TPU 74 > +#define CLK_MOUT_TPU_TPUCTL 75 > +#define CLK_MOUT_TPU_UART 76 > +#define CLK_MOUT_CMU_CMUREF 77 > + > +/* CMU_TOP Dividers */ > +#define CLK_DOUT_BO_BUS 78 > +#define CLK_DOUT_BUS0_BUS 79 > +#define CLK_DOUT_BUS1_BUS 80 > +#define CLK_DOUT_BUS2_BUS 81 > +#define CLK_DOUT_CIS_CLK0 82 > +#define CLK_DOUT_CIS_CLK1 83 > +#define CLK_DOUT_CIS_CLK2 84 > +#define CLK_DOUT_CIS_CLK3 85 > +#define CLK_DOUT_CIS_CLK4 86 > +#define CLK_DOUT_CIS_CLK5 87 > +#define CLK_DOUT_CIS_CLK6 88 > +#define CLK_DOUT_CIS_CLK7 89 > +#define CLK_DOUT_CORE_BUS 90 > +#define CLK_DOUT_CPUCL0_DBG 91 > +#define CLK_DOUT_CPUCL0_SWITCH 92 > +#define CLK_DOUT_CPUCL1_SWITCH 93 > +#define CLK_DOUT_CPUCL2_SWITCH 94 > +#define CLK_DOUT_CSIS_BUS 95 > +#define CLK_DOUT_DISP_BUS 96 > +#define CLK_DOUT_DNS_BUS 97 > +#define CLK_DOUT_DPU_BUS 98 > +#define CLK_DOUT_EH_BUS 99 > +#define CLK_DOUT_G2D_G2D 100 > +#define CLK_DOUT_G2D_MSCL 101 > +#define CLK_DOUT_G3AA_G3AA 102 > +#define CLK_DOUT_G3D_BUSD 103 > +#define CLK_DOUT_G3D_GLB 104 > +#define CLK_DOUT_G3D_SWITCH 105 > +#define CLK_DOUT_GDC_GDC0 106 > +#define CLK_DOUT_GDC_GDC1 107 > +#define CLK_DOUT_GDC_SCSC 108 > +#define CLK_DOUT_CMU_HPM 109 > +#define CLK_DOUT_HSI0_BUS 110 > +#define CLK_DOUT_HSI0_DPGTC 111 > +#define CLK_DOUT_HSI0_USB31DRD 112 > +#define CLK_DOUT_HSI0_USBDPDGB 113 > +#define CLK_DOUT_HSI1_BUS 114 > +#define CLK_DOUT_HSI1_PCIE 115 > +#define CLK_DOUT_HSI2_BUS 116 > +#define CLK_DOUT_HSI2_MMC_CARD 117 > +#define CLK_DOUT_HSI2_PCIE 118 > +#define CLK_DOUT_HSI2_UFS_EMBD 119 > +#define CLK_DOUT_IPP_BUS 107 > +#define CLK_DOUT_ITP_BUS 108 > +#define CLK_DOUT_MCSC_ITSC 109 > +#define CLK_DOUT_MCSC_MCSC 110 > +#define CLK_DOUT_MFC_MFC 111 > +#define CLK_DOUT_MIF_BUSP 112 > +#define CLK_DOUT_MISC_BUS 113 > +#define CLK_DOUT_MISC_SSS 114 > +#define CLK_DOUT_PDP_BUS 115 > +#define CLK_DOUT_PDP_VRA 116 > +#define CLK_DOUT_PERIC0_BUS 117 > +#define CLK_DOUT_PERIC0_IP 118 > +#define CLK_DOUT_PERIC1_BUS 119 > +#define CLK_DOUT_PERIC1_IP 120 > +#define CLK_DOUT_TNR_BUS 121 > +#define CLK_DOUT_TPU_BUS 122 > +#define CLK_DOUT_TPU_TPU 123 > +#define CLK_DOUT_TPU_TPUCTL 124 > +#define CLK_DOUT_TPU_UART 125 > +#define CLK_DOUT_CMU_BOOST 126 > +#define CLK_DOUT_CMU_CMUREF 127 > +#define CLK_DOUT_SHARED0_DIV2 128 > +#define CLK_DOUT_SHARED0_DIV3 129 > +#define CLK_DOUT_SHARED0_DIV4 130 > +#define CLK_DOUT_SHARED0_DIV5 131 > +#define CLK_DOUT_SHARED1_DIV2 132 > +#define CLK_DOUT_SHARED1_DIV3 133 > +#define CLK_DOUT_SHARED1_DIV4 134 > +#define CLK_DOUT_SHARED2_DIV2 135 > +#define CLK_DOUT_SHARED3_DIV2 136 > + > +/* CMU_TOP Gates */ > +#define CLK_GOUT_BUS0_BOOST 137 > +#define CLK_GOUT_BUS1_BOOST 138 > +#define CLK_GOUT_BUS2_BOOST 139 > +#define CLK_GOUT_CORE_BOOST 140 > +#define CLK_GOUT_CPUCL0_BOOST 141 > +#define CLK_GOUT_CPUCL1_BOOST 142 > +#define CLK_GOUT_CPUCL2_BOOST 143 > +#define CLK_GOUT_MIF_BOOST 144 > +#define CLK_GOUT_MIF_SWITCH 145 > +#define CLK_GOUT_BO_BUS 146 > +#define CLK_GOUT_BUS0_BUS 147 > +#define CLK_GOUT_BUS1_BUS 148 > +#define CLK_GOUT_BUS2_BUS 149 > +#define CLK_GOUT_CIS_CLK0 150 > +#define CLK_GOUT_CIS_CLK1 151 > +#define CLK_GOUT_CIS_CLK2 152 > +#define CLK_GOUT_CIS_CLK3 153 > +#define CLK_GOUT_CIS_CLK4 154 > +#define CLK_GOUT_CIS_CLK5 155 > +#define CLK_GOUT_CIS_CLK6 156 > +#define CLK_GOUT_CIS_CLK7 157 > +#define CLK_GOUT_CMU_BOOST 158 > +#define CLK_GOUT_CORE_BUS 159 > +#define CLK_GOUT_CPUCL0_DBG 160 > +#define CLK_GOUT_CPUCL0_SWITCH 161 > +#define CLK_GOUT_CPUCL1_SWITCH 162 > +#define CLK_GOUT_CPUCL2_SWITCH 163 > +#define CLK_GOUT_CSIS_BUS 164 > +#define CLK_GOUT_DISP_BUS 165 > +#define CLK_GOUT_DNS_BUS 166 > +#define CLK_GOUT_DPU_BUS 167 > +#define CLK_GOUT_EH_BUS 168 > +#define CLK_GOUT_G2D_G2D 169 > +#define CLK_GOUT_G2D_MSCL 170 > +#define CLK_GOUT_G3AA_G3AA 171 > +#define CLK_GOUT_G3D_BUSD 172 > +#define CLK_GOUT_G3D_GLB 173 > +#define CLK_GOUT_G3D_SWITCH 174 > +#define CLK_GOUT_GDC_GDC0 175 > +#define CLK_GOUT_GDC_GDC1 176 > +#define CLK_GOUT_GDC_SCSC 177 > +#define CLK_GOUT_CMU_HPM 178 > +#define CLK_GOUT_HSI0_BUS 179 > +#define CLK_GOUT_HSI0_DPGTC 180 > +#define CLK_GOUT_HSI0_USB31DRD 181 > +#define CLK_GOUT_HSI0_USBDPDGB 182 > +#define CLK_GOUT_HSI1_BUS 183 > +#define CLK_GOUT_HSI1_PCIE 184 > +#define CLK_GOUT_HSI2_BUS 185 > +#define CLK_GOUT_HSI2_MMC_CARD 186 > +#define CLK_GOUT_HSI2_PCIE 187 > +#define CLK_GOUT_HSI2_UFS_EMBD 188 > +#define CLK_GOUT_IPP_BUS 189 > +#define CLK_GOUT_ITP_BUS 190 > +#define CLK_GOUT_MCSC_ITSC 191 > +#define CLK_GOUT_MCSC_MCSC 192 > +#define CLK_GOUT_MFC_MFC 193 > +#define CLK_GOUT_MIF_BUSP 194 > +#define CLK_GOUT_MISC_BUS 195 > +#define CLK_GOUT_MISC_SSS 196 > +#define CLK_GOUT_PDP_BUS 197 > +#define CLK_GOUT_PDP_VRA 298 > +#define CLK_GOUT_G3AA 299 > +#define CLK_GOUT_PERIC0_BUS 200 > +#define CLK_GOUT_PERIC0_IP 201 > +#define CLK_GOUT_PERIC1_BUS 202 > +#define CLK_GOUT_PERIC1_IP 203 > +#define CLK_GOUT_TNR_BUS 204 > +#define CLK_GOUT_TOP_CMUREF 205 > +#define CLK_GOUT_TPU_BUS 206 > +#define CLK_GOUT_TPU_TPU 207 > +#define CLK_GOUT_TPU_TPUCTL 208 > +#define CLK_GOUT_TPU_UART 209 > + > +/* CMU_APM */ > +#define CLK_MOUT_APM_FUNC 1 > +#define CLK_MOUT_APM_FUNCSRC 2 > +#define CLK_DOUT_APM_BOOST 3 > +#define CLK_DOUT_APM_USI0_UART 4 > +#define CLK_DOUT_APM_USI0_USI 5 > +#define CLK_DOUT_APM_USI1_UART 6 > +#define CLK_GOUT_APM_APM_CMU_APM_IPCLKPORT_PCLK 7 > +#define CLK_GOUT_BUS0_BOOST_OPTION1 8 > +#define CLK_GOUT_CMU_BOOST_OPTION1 9 > +#define CLK_GOUT_CORE_BOOST_OPTION1 10 > +#define CLK_GOUT_APM_FUNC 11 > +#define CLK_GOUT_APM_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 12 > +#define CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 13 > +#define CLK_GOUT_APM_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 14 > +#define CLK_GOUT_APM_APBIF_RTC_IPCLKPORT_PCLK 15 > +#define CLK_GOUT_APM_APBIF_TRTC_IPCLKPORT_PCLK 16 > +#define CLK_GOUT_APM_APM_USI0_UART_IPCLKPORT_IPCLK 17 > +#define CLK_GOUT_APM_APM_USI0_UART_IPCLKPORT_PCLK 18 > +#define CLK_GOUT_APM_APM_USI0_USI_IPCLKPORT_IPCLK 19 > +#define CLK_GOUT_APM_APM_USI0_USI_IPCLKPORT_PCLK 20 > +#define CLK_GOUT_APM_APM_USI1_UART_IPCLKPORT_IPCLK 21 > +#define CLK_GOUT_APM_APM_USI1_UART_IPCLKPORT_PCLK 22 > +#define CLK_GOUT_APM_D_TZPC_APM_IPCLKPORT_PCLK 23 > +#define CLK_GOUT_APM_GPC_APM_IPCLKPORT_PCLK 24 > +#define CLK_GOUT_APM_GREBEINTEGRATION_IPCLKPORT_HCLK 25 > +#define CLK_GOUT_APM_INTMEM_IPCLKPORT_ACLK 26 > +#define CLK_GOUT_APM_INTMEM_IPCLKPORT_PCLK 27 > +#define CLK_GOUT_APM_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 28 > +#define CLK_GOUT_APM_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 29 > +#define CLK_GOUT_APM_LHM_AXI_P_APM_IPCLKPORT_I_CLK 30 > +#define CLK_GOUT_APM_LHS_AXI_D_APM_IPCLKPORT_I_CLK 31 > +#define CLK_GOUT_APM_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 32 > +#define CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 33 > +#define CLK_GOUT_APM_MAILBOX_APM_AOC_IPCLKPORT_PCLK 34 > +#define CLK_GOUT_APM_MAILBOX_APM_AP_IPCLKPORT_PCLK 35 > +#define CLK_GOUT_APM_MAILBOX_APM_GSA_IPCLKPORT_PCLK 36 > +#define CLK_GOUT_APM_MAILBOX_APM_SWD_IPCLKPORT_PCLK 37 > +#define CLK_GOUT_APM_MAILBOX_APM_TPU_IPCLKPORT_PCLK 38 > +#define CLK_GOUT_APM_MAILBOX_AP_AOC_IPCLKPORT_PCLK 39 > +#define CLK_GOUT_APM_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 40 This value (40) is not aligned with the rest of values. > +#define CLK_GOUT_APM_PMU_INTR_GEN_IPCLKPORT_PCLK 41 > +#define CLK_GOUT_APM_ROM_CRC32_HOST_IPCLKPORT_ACLK 42 > +#define CLK_GOUT_APM_ROM_CRC32_HOST_IPCLKPORT_PCLK 43 > +#define CLK_GOUT_APM_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 44 > +#define CLK_GOUT_APM_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 45 > +#define CLK_GOUT_APM_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 46 > +#define CLK_GOUT_APM_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 47 > +#define CLK_GOUT_APM_SPEEDY_APM_IPCLKPORT_PCLK 48 > +#define CLK_GOUT_APM_SPEEDY_SUB_APM_IPCLKPORT_PCLK 49 > +#define CLK_GOUT_APM_SSMT_D_APM_IPCLKPORT_ACLK 50 > +#define CLK_GOUT_APM_SSMT_D_APM_IPCLKPORT_PCLK 51 > +#define CLK_GOUT_APM_SSMT_G_DBGCORE_IPCLKPORT_ACLK 52 > +#define CLK_GOUT_APM_SSMT_G_DBGCORE_IPCLKPORT_PCLK 53 > +#define CLK_GOUT_APM_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 54 > +#define CLK_GOUT_APM_SYSMMU_D_APM_IPCLKPORT_CLK_S2 55 > +#define CLK_GOUT_APM_SYSREG_APM_IPCLKPORT_PCLK 56 > +#define CLK_GOUT_APM_UASC_APM_IPCLKPORT_ACLK 57 > +#define CLK_GOUT_APM_UASC_APM_IPCLKPORT_PCLK 58 > +#define CLK_GOUT_APM_UASC_DBGCORE_IPCLKPORT_ACLK 59 > +#define CLK_GOUT_APM_UASC_DBGCORE_IPCLKPORT_PCLK 60 > +#define CLK_GOUT_APM_UASC_G_SWD_IPCLKPORT_ACLK 61 > +#define CLK_GOUT_APM_UASC_G_SWD_IPCLKPORT_PCLK 62 > +#define CLK_GOUT_APM_UASC_P_AOCAPM_IPCLKPORT_ACLK 63 > +#define CLK_GOUT_APM_UASC_P_AOCAPM_IPCLKPORT_PCLK 64 > +#define CLK_GOUT_APM_UASC_P_APM_IPCLKPORT_ACLK 65 > +#define CLK_GOUT_APM_UASC_P_APM_IPCLKPORT_PCLK 66 > +#define CLK_GOUT_APM_WDT_APM_IPCLKPORT_PCLK 67 > +#define CLK_GOUT_APM_XIU_DP_APM_IPCLKPORT_ACLK 68 > +#define CLK_APM_PLL_DIV2_APM 69 > +#define CLK_APM_PLL_DIV4_APM 70 > +#define CLK_APM_PLL_DIV16_APM 71 > + > +/* CMU_MISC */ > + This empty line can be removed, for consistency with the rest of similar comments in this file. > +#define CLK_MOUT_MISC_BUS_USER 1 > +#define CLK_MOUT_MISC_SSS_USER 2 > +#define CLK_MOUT_MISC_GIC 3 > +#define CLK_DOUT_MISC_BUSP 4 > +#define CLK_DOUT_MISC_GIC 5 > +#define CLK_GOUT_MISC_MISC_CMU_MISC_IPCLKPORT_PCLK 6 > +#define CLK_GOUT_MISC_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 7 > +#define CLK_GOUT_MISC_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 8 > +#define CLK_GOUT_MISC_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 9 > +#define CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 10 > +#define CLK_GOUT_MISC_ADM_AHB_SSS_IPCLKPORT_HCLKM 11 > +#define CLK_GOUT_MISC_AD_APB_DIT_IPCLKPORT_PCLKM 12 > +#define CLK_GOUT_MISC_AD_APB_PUF_IPCLKPORT_PCLKM 13 > +#define CLK_GOUT_MISC_DIT_IPCLKPORT_ICLKL2A 14 > +#define CLK_GOUT_MISC_D_TZPC_MISC_IPCLKPORT_PCLK 15 > +#define CLK_GOUT_MISC_GIC_IPCLKPORT_GICCLK 16 > +#define CLK_GOUT_MISC_GPC_MISC_IPCLKPORT_PCLK 17 > +#define CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 18 > +#define CLK_GOUT_MISC_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 19 > +#define CLK_GOUT_MISC_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 20 > +#define CLK_GOUT_MISC_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 21 > +#define CLK_GOUT_MISC_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 22 > +#define CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 23 > +#define CLK_GOUT_MISC_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 24 > +#define CLK_GOUT_MISC_MCT_IPCLKPORT_PCLK 25 > +#define CLK_GOUT_MISC_OTP_CON_BIRA_IPCLKPORT_PCLK 26 > +#define CLK_GOUT_MISC_OTP_CON_BISR_IPCLKPORT_PCLK 27 > +#define CLK_GOUT_MISC_OTP_CON_TOP_IPCLKPORT_PCLK 28 > +#define CLK_GOUT_MISC_PDMA_IPCLKPORT_ACLK 29 > +#define CLK_GOUT_MISC_PPMU_DMA_IPCLKPORT_ACLK 30 > +#define CLK_GOUT_MISC_PPMU_MISC_IPCLKPORT_ACLK 31 > +#define CLK_GOUT_MISC_PPMU_MISC_IPCLKPORT_PCLK 32 > +#define CLK_GOUT_MISC_PUF_IPCLKPORT_I_CLK 33 > +#define CLK_GOUT_MISC_QE_DIT_IPCLKPORT_ACLK 34 > +#define CLK_GOUT_MISC_QE_DIT_IPCLKPORT_PCLK 35 > +#define CLK_GOUT_MISC_QE_PDMA_IPCLKPORT_ACLK 36 > +#define CLK_GOUT_MISC_QE_PDMA_IPCLKPORT_PCLK 37 > +#define CLK_GOUT_MISC_QE_PPMU_DMA_IPCLKPORT_ACLK 38 > +#define CLK_GOUT_MISC_QE_PPMU_DMA_IPCLKPORT_PCLK 39 > +#define CLK_GOUT_MISC_QE_RTIC_IPCLKPORT_ACLK 40 > +#define CLK_GOUT_MISC_QE_RTIC_IPCLKPORT_PCLK 41 > +#define CLK_GOUT_MISC_QE_SPDMA_IPCLKPORT_ACLK 42 > +#define CLK_GOUT_MISC_QE_SPDMA_IPCLKPORT_PCLK 43 > +#define CLK_GOUT_MISC_QE_SSS_IPCLKPORT_ACLK 44 > +#define CLK_GOUT_MISC_QE_SSS_IPCLKPORT_PCLK 45 > +#define CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 46 > +#define CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 47 > +#define CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 48 > +#define CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 49 > +#define CLK_GOUT_MISC_RTIC_IPCLKPORT_I_ACLK 50 > +#define CLK_GOUT_MISC_RTIC_IPCLKPORT_I_PCLK 51 > +#define CLK_GOUT_MISC_SPDMA_IPCLKPORT_ACLK 52 > +#define CLK_GOUT_MISC_SSMT_DIT_IPCLKPORT_ACLK 53 > +#define CLK_GOUT_MISC_SSMT_DIT_IPCLKPORT_PCLK 54 > +#define CLK_GOUT_MISC_SSMT_PDMA_IPCLKPORT_ACLK 55 > +#define CLK_GOUT_MISC_SSMT_PDMA_IPCLKPORT_PCLK 56 > +#define CLK_GOUT_MISC_SSMT_PPMU_DMA_IPCLKPORT_ACLK 57 > +#define CLK_GOUT_MISC_SSMT_PPMU_DMA_IPCLKPORT_PCLK 58 > +#define CLK_GOUT_MISC_SSMT_RTIC_IPCLKPORT_ACLK 59 > +#define CLK_GOUT_MISC_SSMT_RTIC_IPCLKPORT_PCLK 60 > +#define CLK_GOUT_MISC_SSMT_SPDMA_IPCLKPORT_ACLK 61 > +#define CLK_GOUT_MISC_SSMT_SPDMA_IPCLKPORT_PCLK 62 > +#define CLK_GOUT_MISC_SSMT_SSS_IPCLKPORT_ACLK 63 > +#define CLK_GOUT_MISC_SSMT_SSS_IPCLKPORT_PCLK 64 > +#define CLK_GOUT_MISC_SSS_IPCLKPORT_I_ACLK 65 > +#define CLK_GOUT_MISC_SSS_IPCLKPORT_I_PCLK 66 > +#define CLK_GOUT_MISC_SYSMMU_MISC_IPCLKPORT_CLK_S2 67 > +#define CLK_GOUT_MISC_SYSMMU_SSS_IPCLKPORT_CLK_S1 68 > +#define CLK_GOUT_MISC_SYSREG_MISC_IPCLKPORT_PCLK 69 > +#define CLK_GOUT_MISC_TMU_SUB_IPCLKPORT_PCLK 70 > +#define CLK_GOUT_MISC_TMU_TOP_IPCLKPORT_PCLK 71 > +#define CLK_GOUT_MISC_WDT_CLUSTER0_IPCLKPORT_PCLK 72 > +#define CLK_GOUT_MISC_WDT_CLUSTER1_IPCLKPORT_PCLK 73 > +#define CLK_GOUT_MISC_XIU_D_MISC_IPCLKPORT_ACLK 74 > + > +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ > -- > 2.43.0.rc2.451.g8631bc7472-goog >
On 12/01/2023, Peter Griffin wrote: > Hi folks, > > Thanks to everyone who reviewed the previous rounds. V5 incorporates > the review feedback received so far, and is rebased onto linux-next as > per Krzysztof request to incorporate all his dt-binding changes for > exynos. > > As this series spans multiple subsytems the expectation is that Krzysztof > will apply the whole series through the Samsung SoC tree. If the relevant > subsystem maintainers can give a acked-by or reviewed-by on the relevant > patches that would be most appreciated! > > This series adds initial SoC support for the GS101 SoC and also initial board > support for Pixel 6 phone (Oriole). > > The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro > (raven) phones. Currently DT is added for the gs101 SoC and Oriole. > As you can see from the patches the SoC is based on a Samsung Exynos SoC, > and therefore lots of the low level Exynos drivers can be re-used. > > The support added in this series consists of: > * cpus > * pinctrl > * CCF implementation of cmu_top, cmu_misc & cmu_apm > * watchdog > * USI uart > * gpio > > This is enough to boot through to a busybox initramfs and shell using an > upstream kernel though :) More platform support will be added over the > following weeks and months. > > For further information on how to build and flash the upstream kernel on your > Pixel 6, with a prebuilt busybox initramfs please refer to the script and > README.md here: > > https://git.codelinaro.org/linaro/googlelt/pixelscripts > > Note: Booting without a dtbo works with some versions of the bootloader > but crashes on others. Later versions aren't necessarily better. You can > get the bootloader version with `fastboot getvar version-bootloader` > Known good bootloader versions are: - > - slider-1.3-11000330 > - slider-1.2-9152140 > Known to crash without dtbo > - slider-1.3-10780582 > > kind regards, > > Peter. > > lore v4: https://lore.kernel.org/linux-arm-kernel/20231120212037.911774-1-peter.griffin@linaro.org/T/ > pw v3: https://patchwork.kernel.org/project/linux-samsung-soc/cover/20231011184823.443959-1-peter.griffin@linaro.org/ > lore v2: https://lore.kernel.org/all/20231010224928.2296997-1-peter.griffin@linaro.org/ > lore v1: https://lore.kernel.org/linux-arm-kernel/20231005155618.700312-1-peter.griffin@linaro.org/ > > Changes since v4: > - clk-gs101: order cmu_top by register address, fix incorrect mux widths, > add missing mux/div/gates (Andre) > - google,gs101.h: add missing space in comment (Andre) > - ckl-gs101:google,gs101.h add all remaining gates for cmu_misc and cmu_apm > - update pmu dt labels (Krzysztof) > - Remove uart16 rts/tx gpio definitions (Krzysztof) > - Fixup various dts cosmetic nits (using consts, alignments, > names) (Sam/Krzysztof) > - Add more specific compatibles for arm cpu's and pmu (Sam) > - Use address-cells 1 and ranges property for SoC addresses (Sam) > - Encapsulate uart node in USI node (Sam) > - Remove earlycon from bootargs > - s3c2410_wdt: Reword QUIRK_HAS_DBGACK_BIT docs and add comment (Guenter) > - s3c2410_wdt: Reorder DBGACK_MASK functionality first, gs101 > SoC second (Sam/Krzysztof) > > Changes since v3: > - Add reviewed-by and tested-by tags > - google,gs101-clock.yaml: move Required to before Allof, > enum for cmu*top/misc (Krzysztof) > - samsung-wdt.yaml: stick to 80chars (Sam) > - google.yaml - remove new line > - samsung,pinctrl-wakeup-interrupt: sort alphabetically (RobH) > - gs101-oriole.dts: update gpio-keys pinctrl-0 phandle for keys (Stephen) > - samsung,exynos-sysreg.yaml - Alphabetical order (RobH) > - pinctrl-exynos: update/move comments, slight cosmetic changes (Sam) > - samsung_tty.c: update to generic drv_data name/macro (Arnd) > - samsung_uart.yaml: make samsung,uart-fifosize required for gs101-uart (Arnd) > - pinctrl-exynos: Remove eint irqs from alive pin controller node (Peter/Rob) > - Fixup kernel test robot unused const variable warnings > - clk-gs101: Update to mout_cmu_eh_bus to CLK_CON_MUX_MUX_CLKCMU_EH_BUS > (Chanwoo) > - clk-gs101: Update g3aa gout/dout/mout names to g3aa_g3aa for > consistency (Chanwoo) > - Remove .eint_gpio_init() cb on alive, alive_far, gsacore & gsactrl > banks (Sam) > - s3c2410_wdt: Drop windowed watchdog mode for now (Peter) > - s3c2410_wdt: Separate gs101 SoC support from dbgack feature (Sam) > - Move dts to arch/arm64/boot/dts/exynos/google directory (Krzysztof) > > Changes since v2: > - Fixup pinctrl@174d0000: interrupts: [..] is too long DTC warning (Tudor) > - Add missing windowed watchdog code (Guenter) > - Fixup UART YAML bindings error (Krzysztof) > - gs101.dtsi add missing serial_0 alias (me) > - samsung_tty.c: fixup gs101_serial_drv_data so fifosize is obtained from DT > > Changes since v1: > - Remove irq/gs101.h and replace macros with irq numbers globally > - exynos-pmu - keep alphabetical order > - add cmu_apm to clock bindings documentation > - sysreg bindings - remove superfluous `google,gs101-sysreg` > - watchdog bindings - Alphanumerical order, update gs201 comment > - samsung,pinctrl.yaml - add new "if:then:else:" to narrow for google SoC > - samsung,pinctrl-wakeup-interrupt.yaml - Alphanumerical order > - samsung,pinctrl- add google,gs101-wakeup-eint compatible > - clk-pll: fixup typos > - clk-gs101: fix kernel test robot warnings (add 2 new clocks,dividers,gate) > - clk-gs101: fix alphabetical order > - clk-gs101: cmu_apm: fixup typo and missing empty entry > - clk-gs101: cmu_misc: remove clocks that were being registered twice > - pinctrl: filter sel: rename/reorder variables, add comment for FLTCON > bitfield > - pinctrl: filter sel: avoid setting reserved bits by loop over FLTCON1 pins > as well > - pinctrl: gs101: rename bank_type_6/7 structs to be more specific, > split from filter > - watchdog: s3c2410_wdt: remove dev_info prints > - gs101.dtsi/oriole.dts: order by unit node, remove underscores from node > name, blank lines add SoC node, split dts and dtsi into separate patches, > remove 'DVT' suffix > - gs101-oriole.dtso: Remove overlay until board_id is documented properly > - Add GS101_PIN_* macros to gs101-pinctrl.h instead of using Exynos ones > - gpio-keys: update linux,code to use input-event-code macros > - add dedicated gs101-uart compatible > > Peter Griffin (19): > dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible > dt-bindings: clock: Add Google gs101 clock management unit bindings > dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG > compatibles to GS101 > dt-bindings: watchdog: Document Google gs101 watchdog bindings > dt-bindings: arm: google: Add bindings for Google ARM platforms > dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible > dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible > dt-bindings: serial: samsung: Add google-gs101-uart compatible > dt-bindings: serial: samsung: Make samsung,uart-fifosize required > property > clk: samsung: clk-pll: Add support for pll_{0516,0517,518} > clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support > pinctrl: samsung: Add filter selection support for alive banks > pinctrl: samsung: Add gs101 SoC pinctrl configuration > watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit > watchdog: s3c2410_wdt: Add support for Google gs101 SoC > tty: serial: samsung: Add gs101 compatible and common > fifoszdt_serial_drv_data > arm64: dts: exynos: google: Add initial Google gs101 SoC support > arm64: dts: exynos: google: Add initial Oriole/pixel 6 board support > MAINTAINERS: add entry for Google Tensor SoC > > Tudor Ambarus (1): > dt-bindings: soc: samsung: usi: add google,gs101-usi compatible > > .../devicetree/bindings/arm/google.yaml | 53 + > .../bindings/clock/google,gs101-clock.yaml | 110 + > .../samsung,pinctrl-wakeup-interrupt.yaml | 2 + > .../bindings/pinctrl/samsung,pinctrl.yaml | 1 + > .../bindings/serial/samsung_uart.yaml | 11 + > .../bindings/soc/samsung/exynos-pmu.yaml | 2 + > .../bindings/soc/samsung/exynos-usi.yaml | 3 + > .../soc/samsung/samsung,exynos-sysreg.yaml | 6 + > .../bindings/watchdog/samsung-wdt.yaml | 8 +- > MAINTAINERS | 10 + > arch/arm64/boot/dts/exynos/Makefile | 2 + > arch/arm64/boot/dts/exynos/google/Makefile | 4 + > .../boot/dts/exynos/google/gs101-oriole.dts | 105 + > .../boot/dts/exynos/google/gs101-pinctrl.dtsi | 1250 +++++++++ > .../boot/dts/exynos/google/gs101-pinctrl.h | 33 + > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 476 ++++ > drivers/clk/samsung/Makefile | 1 + > drivers/clk/samsung/clk-gs101.c | 2495 +++++++++++++++++ > drivers/clk/samsung/clk-pll.c | 6 + > drivers/clk/samsung/clk-pll.h | 3 + > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 159 ++ > drivers/pinctrl/samsung/pinctrl-exynos.c | 91 +- > drivers/pinctrl/samsung/pinctrl-exynos.h | 41 + > drivers/pinctrl/samsung/pinctrl-samsung.c | 4 + > drivers/pinctrl/samsung/pinctrl-samsung.h | 23 + > drivers/tty/serial/samsung_tty.c | 16 + > drivers/watchdog/s3c2410_wdt.c | 74 +- > include/dt-bindings/clock/google,gs101.h | 392 +++ > 28 files changed, 5370 insertions(+), 11 deletions(-) > create mode 100644 Documentation/devicetree/bindings/arm/google.yaml > create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml > create mode 100644 arch/arm64/boot/dts/exynos/google/Makefile > create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-oriole.dts > create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi > create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > create mode 100644 arch/arm64/boot/dts/exynos/google/gs101.dtsi > create mode 100644 drivers/clk/samsung/clk-gs101.c > create mode 100644 include/dt-bindings/clock/google,gs101.h > > -- > 2.43.0.rc2.451.g8631bc7472-goog > Thanks Peter for the updated patch series! I've gone through and reviewed the changes and tested them on my Oriole device. I was able to boot to the busybox console and verify the appropriate drivers probed. Great work! Regards, Will
On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > cmu_top is the top level clock management unit which contains PLLs, muxes, > dividers and gates that feed the other clock management units. > > cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the > APM module. > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com> > Tested-by: Will McVicker <willmcvicker@google.com> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/clk/samsung/Makefile | 1 + > drivers/clk/samsung/clk-gs101.c | 2495 +++++++++++++++++++++++++++++++ > 2 files changed, 2496 insertions(+) > create mode 100644 drivers/clk/samsung/clk-gs101.c > > diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile > index ebbeacabe88f..3056944a5a54 100644 > --- a/drivers/clk/samsung/Makefile > +++ b/drivers/clk/samsung/Makefile > @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o > +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o > obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o > obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o > obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c > new file mode 100644 > index 000000000000..6bd233a7ab63 > --- /dev/null > +++ b/drivers/clk/samsung/clk-gs101.c > @@ -0,0 +1,2495 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2023 Linaro Ltd. > + * Author: Peter Griffin <peter.griffin@linaro.org> > + * > + * Common Clock Framework support for GS101. > + */ > + > +#include <linux/clk.h> > +#include <linux/clk-provider.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > + > +#include <dt-bindings/clock/google,gs101.h> > + > +#include "clk.h" > +#include "clk-exynos-arm64.h" > + > +/* NOTE: Must be equal to the last clock ID increased by one */ > +#define TOP_NR_CLK (CLK_GOUT_TPU_UART + 1) > +#define APM_NR_CLK (CLK_APM_PLL_DIV16_APM + 1) > +#define MISC_NR_CLK (CLK_GOUT_MISC_XIU_D_MISC_IPCLKPORT_ACLK + 1) > + Suggest using CLKS_NR_* naming, to follow other drivers for consistency. > +/* ---- CMU_TOP ------------------------------------------------------------- */ > + > +/* Register Offset definitions for CMU_TOP (0x1e080000) */ > + > +#define PLL_LOCKTIME_PLL_SHARED0 0x0000 > +#define PLL_LOCKTIME_PLL_SHARED1 0x0004 > +#define PLL_LOCKTIME_PLL_SHARED2 0x0008 > +#define PLL_LOCKTIME_PLL_SHARED3 0x000c > +#define PLL_LOCKTIME_PLL_SPARE 0x0010 > +#define PLL_CON0_PLL_SHARED0 0x0100 > +#define PLL_CON1_PLL_SHARED0 0x0104 > +#define PLL_CON2_PLL_SHARED0 0x0108 > +#define PLL_CON3_PLL_SHARED0 0x010c > +#define PLL_CON4_PLL_SHARED0 0x0110 > +#define PLL_CON0_PLL_SHARED1 0x0140 > +#define PLL_CON1_PLL_SHARED1 0x0144 > +#define PLL_CON2_PLL_SHARED1 0x0148 > +#define PLL_CON3_PLL_SHARED1 0x014c > +#define PLL_CON4_PLL_SHARED1 0x0150 > +#define PLL_CON0_PLL_SHARED2 0x0180 > +#define PLL_CON1_PLL_SHARED2 0x0184 > +#define PLL_CON2_PLL_SHARED2 0x0188 > +#define PLL_CON3_PLL_SHARED2 0x018c > +#define PLL_CON4_PLL_SHARED2 0x0190 > +#define PLL_CON0_PLL_SHARED3 0x01c0 > +#define PLL_CON1_PLL_SHARED3 0x01c4 > +#define PLL_CON2_PLL_SHARED3 0x01c8 > +#define PLL_CON3_PLL_SHARED3 0x01cc > +#define PLL_CON4_PLL_SHARED3 0x01d0 > +#define PLL_CON0_PLL_SPARE 0x0200 > +#define PLL_CON1_PLL_SPARE 0x0204 > +#define PLL_CON2_PLL_SPARE 0x0208 > +#define PLL_CON3_PLL_SPARE 0x020c > +#define PLL_CON4_PLL_SPARE 0x0210 > +#define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800 > +#define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810 > +#define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840 > +#define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844 > +#define CMU_HCHGEN_CLKMUX 0x0850 > +#define POWER_FAIL_DETECT_PLL 0x0864 > +#define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870 > +#define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874 > +#define EARLY_WAKEUP_APM_CTRL 0x0878 > +#define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c > +#define EARLY_WAKEUP_DPU_CTRL 0x0880 > +#define EARLY_WAKEUP_CSIS_CTRL 0x0884 > +#define EARLY_WAKEUP_APM_DEST 0x0890 > +#define EARLY_WAKEUP_CLUSTER0_DEST 0x0894 > +#define EARLY_WAKEUP_DPU_DEST 0x0898 > +#define EARLY_WAKEUP_CSIS_DEST 0x089c > +#define EARLY_WAKEUP_SW_TRIG_APM 0x08c0 > +#define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4 > +#define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8 > +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0 > +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4 > +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8 > +#define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0 > +#define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4 > +#define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8 > +#define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0 > +#define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4 > +#define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8 > + > +#define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000 > +#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004 > +#define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008 > +#define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010 > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014 > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018 > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020 > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024 > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028 > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c > +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030 > +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034 > +#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038 > +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c > +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040 > +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044 > +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048 > +#define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c > +#define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050 > +#define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054 > +#define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058 > +#define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c > +#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060 > +#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064 > +#define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068 > +#define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c > +#define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070 > +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074 > +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078 > +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c > +#define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080 > +#define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c > +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c > +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac > +#define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0 > +#define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4 > +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8 > +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc > +#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0 > +#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4 > +#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8 > +#define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc > +#define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0 > +#define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4 > +#define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8 > +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc > +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0 > +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4 > +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8 > +#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec > +#define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0 > +#define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4 > +#define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8 > +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc > +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100 > +#define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104 > +#define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108 > + > +#define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800 > +#define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804 > +#define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808 > +#define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c > +#define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810 > +#define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814 > +#define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818 > +#define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c > +#define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820 > +#define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824 > +#define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828 > +#define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c > +#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830 > +#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834 > +#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838 > +#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c > +#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840 > +#define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844 > +#define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848 > +#define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c > +#define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850 > +#define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854 > +#define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858 > +#define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c > +#define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860 > +#define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864 > +#define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868 > +#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c > +#define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870 > +#define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874 > +#define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878 > +#define CLK_CON_DIV_CLKCMU_HPM 0x187c > +#define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880 > +#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884 > +#define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888 > +#define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c > +#define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890 > +#define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894 > +#define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898 > +#define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c > +#define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0 > +#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4 > +#define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8 > +#define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac > +#define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0 > +#define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4 > +#define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8 > +#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc > +#define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0 > +#define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4 > +#define CLK_CON_DIV_CLKCMU_OTP 0x18c8 > +#define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc > +#define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0 > +#define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4 > +#define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8 > +#define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc > +#define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0 > +#define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4 > +#define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8 > +#define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec > +#define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0 > +#define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4 > +#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8 > +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc > +#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900 > +#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904 > +#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908 > +#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c > +#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910 > +#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914 > +#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918 > +#define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c > +#define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920 > + > +/* CLK_CON_GAT_UPDATES */ > +#define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000 > +#define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004 > +#define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008 > +#define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c > +#define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010 > +#define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014 > +#define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018 > +#define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c > +#define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020 > +#define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024 > +#define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028 > +#define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c > +#define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030 > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034 > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038 > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040 > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044 > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048 > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050 > +#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054 > +#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058 > +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c > +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060 > +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064 > +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068 > +#define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c > +#define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070 > +#define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074 > +#define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078 > +#define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c > +#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080 > +#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084 > +#define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088 > +#define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c > +#define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090 > +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094 > +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098 > +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c > +#define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0 > +#define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac > +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc > +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc > +#define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0 > +#define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4 > +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8 > +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc > +#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0 > +#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4 > +#define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8 > +#define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec > +#define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0 > +#define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4 > +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8 > +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc > +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100 > +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104 > +#define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108 > +#define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c > +#define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110 > +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114 > +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118 > +#define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c > + > +#define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000 > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004 > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008 > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010 > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014 > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018 > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020 > +#define DMYQCH_CON_OTP_QCH 0x3024 > +#define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00 > +#define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10 > +#define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14 > +#define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18 > +#define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c > +#define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20 > +#define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24 > +#define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28 > +#define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c > +#define MIFMIRROR_QUEUE_CTRL_REG 0x3e00 > +#define MIFMIRROR_QUEUE_ENTRY0 0x3e10 > +#define MIFMIRROR_QUEUE_ENTRY1 0x3e14 > +#define MIFMIRROR_QUEUE_ENTRY2 0x3e18 > +#define MIFMIRROR_QUEUE_ENTRY3 0x3e1c > +#define MIFMIRROR_QUEUE_ENTRY4 0x3e20 > +#define MIFMIRROR_QUEUE_ENTRY5 0x3e24 > +#define MIFMIRROR_QUEUE_ENTRY6 0x3e28 > +#define MIFMIRROR_QUEUE_ENTRY7 0x3e2c > +#define MIFMIRROR_QUEUE_BUSY 0x3e30 > +#define GENERALIO_ACD_CHANNEL_0 0x3f00 > +#define GENERALIO_ACD_CHANNEL_1 0x3f04 > +#define GENERALIO_ACD_CHANNEL_2 0x3f08 > +#define GENERALIO_ACD_CHANNEL_3 0x3f0c > +#define GENERALIO_ACD_MASK 0x3f14 > + > +static const unsigned long cmu_top_clk_regs[] __initconst = { > + PLL_LOCKTIME_PLL_SHARED0, > + PLL_LOCKTIME_PLL_SHARED1, > + PLL_LOCKTIME_PLL_SHARED2, > + PLL_LOCKTIME_PLL_SHARED3, > + PLL_LOCKTIME_PLL_SPARE, > + PLL_CON0_PLL_SHARED0, > + PLL_CON1_PLL_SHARED0, > + PLL_CON2_PLL_SHARED0, > + PLL_CON3_PLL_SHARED0, > + PLL_CON4_PLL_SHARED0, > + PLL_CON0_PLL_SHARED1, > + PLL_CON1_PLL_SHARED1, > + PLL_CON2_PLL_SHARED1, > + PLL_CON3_PLL_SHARED1, > + PLL_CON4_PLL_SHARED1, > + PLL_CON0_PLL_SHARED2, > + PLL_CON1_PLL_SHARED2, > + PLL_CON2_PLL_SHARED2, > + PLL_CON3_PLL_SHARED2, > + PLL_CON4_PLL_SHARED2, > + PLL_CON0_PLL_SHARED3, > + PLL_CON1_PLL_SHARED3, > + PLL_CON2_PLL_SHARED3, > + PLL_CON3_PLL_SHARED3, > + PLL_CON4_PLL_SHARED3, > + PLL_CON0_PLL_SPARE, > + PLL_CON1_PLL_SPARE, > + PLL_CON2_PLL_SPARE, > + PLL_CON3_PLL_SPARE, > + PLL_CON4_PLL_SPARE, > + CMU_CMU_TOP_CONTROLLER_OPTION, > + CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0, > + CMU_HCHGEN_CLKMUX_CMU_BOOST, > + CMU_HCHGEN_CLKMUX_TOP_BOOST, > + CMU_HCHGEN_CLKMUX, > + POWER_FAIL_DETECT_PLL, > + EARLY_WAKEUP_FORCED_0_ENABLE, > + EARLY_WAKEUP_FORCED_1_ENABLE, > + EARLY_WAKEUP_APM_CTRL, > + EARLY_WAKEUP_CLUSTER0_CTRL, > + EARLY_WAKEUP_DPU_CTRL, > + EARLY_WAKEUP_CSIS_CTRL, > + EARLY_WAKEUP_APM_DEST, > + EARLY_WAKEUP_CLUSTER0_DEST, > + EARLY_WAKEUP_DPU_DEST, > + EARLY_WAKEUP_CSIS_DEST, > + EARLY_WAKEUP_SW_TRIG_APM, > + EARLY_WAKEUP_SW_TRIG_APM_SET, > + EARLY_WAKEUP_SW_TRIG_APM_CLEAR, > + EARLY_WAKEUP_SW_TRIG_CLUSTER0, > + EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET, > + EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR, > + EARLY_WAKEUP_SW_TRIG_DPU, > + EARLY_WAKEUP_SW_TRIG_DPU_SET, > + EARLY_WAKEUP_SW_TRIG_DPU_CLEAR, > + EARLY_WAKEUP_SW_TRIG_CSIS, > + EARLY_WAKEUP_SW_TRIG_CSIS_SET, > + EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR, > + CLK_CON_MUX_MUX_CLKCMU_BO_BUS, > + CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, > + CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, > + CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, > + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, > + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, > + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, > + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, > + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, > + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, > + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, > + CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, > + CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, > + CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, > + CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, > + CLK_CON_MUX_MUX_CLKCMU_EH_BUS, > + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, > + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, > + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, > + CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, > + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, > + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, > + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, > + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, > + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, > + CLK_CON_MUX_MUX_CLKCMU_HPM, > + CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, > + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, > + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, > + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, > + CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, > + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, > + CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, > + CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, > + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, > + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, > + CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, > + CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, > + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, > + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, > + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, > + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, > + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, > + CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, > + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, > + CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, > + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, > + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, > + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, > + CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, > + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, > + CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, > + CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, > + CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, > + CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, > + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, > + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, > + CLK_CON_MUX_MUX_CLKCMU_TPU_UART, > + CLK_CON_MUX_MUX_CMU_CMUREF, > + CLK_CON_DIV_CLKCMU_BO_BUS, > + CLK_CON_DIV_CLKCMU_BUS0_BUS, > + CLK_CON_DIV_CLKCMU_BUS1_BUS, > + CLK_CON_DIV_CLKCMU_BUS2_BUS, > + CLK_CON_DIV_CLKCMU_CIS_CLK0, > + CLK_CON_DIV_CLKCMU_CIS_CLK1, > + CLK_CON_DIV_CLKCMU_CIS_CLK2, > + CLK_CON_DIV_CLKCMU_CIS_CLK3, > + CLK_CON_DIV_CLKCMU_CIS_CLK4, > + CLK_CON_DIV_CLKCMU_CIS_CLK5, > + CLK_CON_DIV_CLKCMU_CIS_CLK6, > + CLK_CON_DIV_CLKCMU_CIS_CLK7, > + CLK_CON_DIV_CLKCMU_CORE_BUS, > + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, > + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, > + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, > + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, > + CLK_CON_DIV_CLKCMU_CSIS_BUS, > + CLK_CON_DIV_CLKCMU_DISP_BUS, > + CLK_CON_DIV_CLKCMU_DNS_BUS, > + CLK_CON_DIV_CLKCMU_DPU_BUS, > + CLK_CON_DIV_CLKCMU_EH_BUS, > + CLK_CON_DIV_CLKCMU_G2D_G2D, > + CLK_CON_DIV_CLKCMU_G2D_MSCL, > + CLK_CON_DIV_CLKCMU_G3AA_G3AA, > + CLK_CON_DIV_CLKCMU_G3D_BUSD, > + CLK_CON_DIV_CLKCMU_G3D_GLB, > + CLK_CON_DIV_CLKCMU_G3D_SWITCH, > + CLK_CON_DIV_CLKCMU_GDC_GDC0, > + CLK_CON_DIV_CLKCMU_GDC_GDC1, > + CLK_CON_DIV_CLKCMU_GDC_SCSC, > + CLK_CON_DIV_CLKCMU_HPM, > + CLK_CON_DIV_CLKCMU_HSI0_BUS, > + CLK_CON_DIV_CLKCMU_HSI0_DPGTC, > + CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, > + CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, > + CLK_CON_DIV_CLKCMU_HSI1_BUS, > + CLK_CON_DIV_CLKCMU_HSI1_PCIE, > + CLK_CON_DIV_CLKCMU_HSI2_BUS, > + CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, > + CLK_CON_DIV_CLKCMU_HSI2_PCIE, > + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, > + CLK_CON_DIV_CLKCMU_IPP_BUS, > + CLK_CON_DIV_CLKCMU_ITP_BUS, > + CLK_CON_DIV_CLKCMU_MCSC_ITSC, > + CLK_CON_DIV_CLKCMU_MCSC_MCSC, > + CLK_CON_DIV_CLKCMU_MFC_MFC, > + CLK_CON_DIV_CLKCMU_MIF_BUSP, > + CLK_CON_DIV_CLKCMU_MISC_BUS, > + CLK_CON_DIV_CLKCMU_MISC_SSS, > + CLK_CON_DIV_CLKCMU_OTP, > + CLK_CON_DIV_CLKCMU_PDP_BUS, > + CLK_CON_DIV_CLKCMU_PDP_VRA, > + CLK_CON_DIV_CLKCMU_PERIC0_BUS, > + CLK_CON_DIV_CLKCMU_PERIC0_IP, > + CLK_CON_DIV_CLKCMU_PERIC1_BUS, > + CLK_CON_DIV_CLKCMU_PERIC1_IP, > + CLK_CON_DIV_CLKCMU_TNR_BUS, > + CLK_CON_DIV_CLKCMU_TPU_BUS, > + CLK_CON_DIV_CLKCMU_TPU_TPU, > + CLK_CON_DIV_CLKCMU_TPU_TPUCTL, > + CLK_CON_DIV_CLKCMU_TPU_UART, > + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, > + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, > + CLK_CON_DIV_PLL_SHARED0_DIV2, > + CLK_CON_DIV_PLL_SHARED0_DIV3, > + CLK_CON_DIV_PLL_SHARED0_DIV4, > + CLK_CON_DIV_PLL_SHARED0_DIV5, > + CLK_CON_DIV_PLL_SHARED1_DIV2, > + CLK_CON_DIV_PLL_SHARED1_DIV3, > + CLK_CON_DIV_PLL_SHARED1_DIV4, > + CLK_CON_DIV_PLL_SHARED2_DIV2, > + CLK_CON_DIV_PLL_SHARED3_DIV2, > + CLK_CON_GAT_CLKCMU_BUS0_BOOST, > + CLK_CON_GAT_CLKCMU_BUS1_BOOST, > + CLK_CON_GAT_CLKCMU_BUS2_BOOST, > + CLK_CON_GAT_CLKCMU_CORE_BOOST, > + CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, > + CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, > + CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, > + CLK_CON_GAT_CLKCMU_MIF_BOOST, > + CLK_CON_GAT_CLKCMU_MIF_SWITCH, > + CLK_CON_GAT_GATE_CLKCMU_BO_BUS, > + CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, > + CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, > + CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, > + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, > + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, > + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, > + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, > + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, > + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, > + CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, > + CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, > + CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, > + CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, > + CLK_CON_GAT_GATE_CLKCMU_EH_BUS, > + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, > + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, > + CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA, > + CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, > + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, > + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, > + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, > + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, > + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, > + CLK_CON_GAT_GATE_CLKCMU_HPM, > + CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, > + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, > + CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, > + CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, > + CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, > + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, > + CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, > + CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, > + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, > + CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, > + CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, > + CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, > + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, > + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, > + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, > + CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, > + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, > + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, > + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, > + CLK_CON_GAT_GATE_CLKCMU_PDP_VRA, > + CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, > + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, > + CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, > + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, > + CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, > + CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, > + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, > + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, > + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, > + CLK_CON_GAT_GATE_CLKCMU_TPU_UART, > + DMYQCH_CON_CMU_TOP_CMUREF_QCH, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7, > + DMYQCH_CON_OTP_QCH, > + QUEUE_CTRL_REG_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY0_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY1_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY2_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY3_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY4_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY5_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY6_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY7_BLK_CMU_CMU_TOP, > + MIFMIRROR_QUEUE_CTRL_REG, > + MIFMIRROR_QUEUE_ENTRY0, > + MIFMIRROR_QUEUE_ENTRY1, > + MIFMIRROR_QUEUE_ENTRY2, > + MIFMIRROR_QUEUE_ENTRY3, > + MIFMIRROR_QUEUE_ENTRY4, > + MIFMIRROR_QUEUE_ENTRY5, > + MIFMIRROR_QUEUE_ENTRY6, > + MIFMIRROR_QUEUE_ENTRY7, > + MIFMIRROR_QUEUE_BUSY, > + GENERALIO_ACD_CHANNEL_0, > + GENERALIO_ACD_CHANNEL_1, > + GENERALIO_ACD_CHANNEL_2, > + GENERALIO_ACD_CHANNEL_3, > + GENERALIO_ACD_MASK, > +}; > + > +static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = { > + /* CMU_TOP_PURECLKCOMP */ > + PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", > + PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, > + NULL), > + PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", > + PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, > + NULL), > + PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk", > + PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, > + NULL), > + PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk", > + PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, > + NULL), > + PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk", > + PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE, > + NULL), > +}; > + > +/* List of parent clocks for Muxes in CMU_TOP */ > +PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; > +PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; > +PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" }; > +PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" }; > +PNAME(mout_spare_pll_p) = { "oscclk", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BO */ > +PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_shared0_div3", > + "fout_shared3_pll", "dout_shared1_div3", > + "dout_shared0_div4", "dout_shared1_div4", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS0 */ > +PNAME(mout_cmu_bus0_bus_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "dout_shared3_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS1 */ > +PNAME(mout_cmu_bus1_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS2 */ > +PNAME(mout_cmu_bus2_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div5", "fout_spare_pll" }; > + > +PNAME(mout_cmu_cis_clk0_7_p) = { "oscclk", "dout_shared0_div3", > + "dout_shared1_div3", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > + > +PNAME(mout_cmu_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "dout_shared3_div2" }; > + > +/* TRM lists CLK_CMU_BOOST_OPTION1 but cmu_diagram links to pll_alv_div4_apm */ > +PNAME(mout_cmu_cmu_boost_option1_p) = { "dout_cmu_boost", "pll_alv_div4_apm" }; > + > +PNAME(mout_cmu_top_boost_option1_p) = { "dout_cmu_boost", "pll_alv_div4_apm" }; > + > +PNAME(mout_cmu_top_cmuref_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "dout_shared3_div2" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ > +PNAME(mout_cmu_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div5", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_EH */ > +PNAME(mout_cmu_eh_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div5", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL2 */ > +PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_shared0_div2", > + "dout_shared1_div2", "fout_shared2_pll", > + "fout_shared3_pll", "dout_shared0_div3", > + "dout_shared1_div3", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */ > +PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_shared0_div2", > + "dout_shared1_div2", "fout_shared2_pll", > + "fout_shared3_pll", "dout_shared0_div3", > + "dout_shared1_div3", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */ > +PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_shared0_div2", > + "dout_shared1_div2", "fout_shared2_pll", > + "fout_shared3_pll", "dout_shared0_div3", > + "dout_shared1_div3", "fout_spare_pll" }; > + > +PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "fout_spare_pll" }; > + > +PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_shared1_div3", > + "dout_shared0_div4", "dout_shared2_div2" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */ > +PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_shared0_div3", > + "fout_shared3_pll", "dout_shared1_div3", > + "dout_shared0_div4", "dout_shared1_div4", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_g3d_busd_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div4", "fout_spare_pll" }; > + > +PNAME(mout_cmu_g3d_glb_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div4", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */ > +PNAME(mout_cmu_dpu_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DISP */ > +PNAME(mout_cmu_disp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */ > +PNAME(mout_cmu_g2d_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_g2d_mscl_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "dout_shared3_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI0 */ > +PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_shared2_div2" }; > + > +PNAME(mout_cmu_hsi0_bus_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "dout_shared3_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_shared0_div4", > + "dout_shared2_div2", "fout_spare_pll" }; > + > +PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_shared2_div2" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI1 */ > +PNAME(mout_cmu_hsi1_bus_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "dout_shared3_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_shared2_div2" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI2 */ > +PNAME(mout_cmu_hsi2_bus_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "dout_shared3_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_shared2_div2" }; > + > +PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared0_div4", > + "dout_shared2_div2", "fout_spare_pll" }; > + > +PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div4", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CSIS */ > +PNAME(mout_cmu_csis_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PDP */ > +PNAME(mout_cmu_pdp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3", > + "fout_shared3_pll", "dout_shared1_div3", > + "dout_shared0_div4", "dout_shared1_div4", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_IPP */ > +PNAME(mout_cmu_ipp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3AA */ > +PNAME(mout_cmu_g3aa_g3aa_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_ITP */ > +PNAME(mout_cmu_itp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DNS */ > +PNAME(mout_cmu_dns_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_TNR */ > +PNAME(mout_cmu_tnr_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MCSC */ > +PNAME(mout_cmu_mcsc_itsc_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_GDC */ > +PNAME(mout_cmu_gdc_scsc_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_gdc_gdc0_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_gdc_gdc1_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFC */ > +PNAME(mout_cmu_mfc_mfc_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for DDRPHY0/1/2/3 */ > + > +PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll", > + "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "dout_shared0_div3", > + "fout_shared3_pll", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MIF0/1/2/3 */ > +PNAME(mout_cmu_mif_busp_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared0_div5", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MISC */ > +PNAME(mout_cmu_misc_bus_p) = { "dout_shared0_div4", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > +PNAME(mout_cmu_misc_sss_p) = { "dout_shared0_div4", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC0 */ > +PNAME(mout_cmu_peric0_bus_p) = { "dout_shared0_div4", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > +PNAME(mout_cmu_peric0_ip_p) = { "dout_shared0_div4", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC1 */ > +PNAME(mout_cmu_peric1_bus_p) = { "dout_shared0_div4", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > +PNAME(mout_cmu_peric1_ip_p) = { "dout_shared0_div4", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_TPU */ > +PNAME(mout_cmu_tpu_tpu_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div4", "fout_spare_pll" }; > + > +PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div4", "fout_spare_pll" }; > + > +PNAME(mout_cmu_tpu_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div4", "fout_spare_pll" }; > + > +PNAME(mout_cmu_tpu_uart_p) = { "dout_shared0_div4", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > + > +PNAME(mout_cmu_cmuref_p) = { "mout_cmu_top_boost_option1", > + "dout_cmu_cmuref" }; > + > +static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = { > + /* CMU_TOP_PURECLKCOMP */ > + MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, > + PLL_CON0_PLL_SHARED0, 4, 1), > + MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, > + PLL_CON0_PLL_SHARED1, 4, 1), > + MUX(CLK_MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p, > + PLL_CON0_PLL_SHARED2, 4, 1), > + MUX(CLK_MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p, > + PLL_CON0_PLL_SHARED3, 4, 1), > + MUX(CLK_MOUT_SPARE_PLL, "mout_spare_pll", mout_spare_pll_p, > + PLL_CON0_PLL_SPARE, 4, 1), > + MUX(CLK_MOUT_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 3), > + MUX(CLK_MOUT_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 3), > + MUX(CLK_MOUT_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 3), > + MUX(CLK_MOUT_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 3), > + MUX(CLK_MOUT_CIS_CLK0, "mout_cmu_cis_clk0", mout_cmu_cis_clk0_7_p, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 3), > + MUX(CLK_MOUT_CIS_CLK1, "mout_cmu_cis_clk1", mout_cmu_cis_clk0_7_p, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 3), > + MUX(CLK_MOUT_CIS_CLK2, "mout_cmu_cis_clk2", mout_cmu_cis_clk0_7_p, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 3), > + MUX(CLK_MOUT_CIS_CLK3, "mout_cmu_cis_clk3", mout_cmu_cis_clk0_7_p, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 3), > + MUX(CLK_MOUT_CIS_CLK4, "mout_cmu_cis_clk4", mout_cmu_cis_clk0_7_p, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 3), > + MUX(CLK_MOUT_CIS_CLK5, "mout_cmu_cis_clk5", mout_cmu_cis_clk0_7_p, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 3), > + MUX(CLK_MOUT_CIS_CLK6, "mout_cmu_cis_clk6", mout_cmu_cis_clk0_7_p, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 3), > + MUX(CLK_MOUT_CIS_CLK7, "mout_cmu_cis_clk7", mout_cmu_cis_clk0_7_p, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 3), > + MUX(CLK_MOUT_CMU_BOOST, "mout_cmu_cmu_boost", mout_cmu_cmu_boost_p, > + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2), > + MUX(CLK_MOUT_BOOST_OPTION1, "mout_cmu_boost_option1", > + mout_cmu_cmu_boost_option1_p, > + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 0, 1), > + MUX(CLK_MOUT_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3), > + MUX(CLK_MOUT_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p, > + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3), > + MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", > + mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, > + 0, 3), > + MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", > + mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, > + 0, 3), > + MUX(CLK_MOUT_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", > + mout_cmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, > + 0, 3), > + MUX(CLK_MOUT_CSIS_BUS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 3), > + MUX(CLK_MOUT_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 3), > + MUX(CLK_MOUT_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3), > + MUX(CLK_MOUT_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p, > + CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3), > + MUX(CLK_MOUT_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 0, 3), > + MUX(CLK_MOUT_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p, > + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3), > + MUX(CLK_MOUT_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p, > + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 3), > + MUX(CLK_MOUT_G3AA_G3AA, "mout_cmu_g3aa_g3aa", mout_cmu_g3aa_g3aa_p, > + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 3), > + MUX(CLK_MOUT_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p, > + CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 3), > + MUX(CLK_MOUT_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p, > + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 3), > + MUX(CLK_MOUT_G3D_SWITCH, "mout_cmu_g3d_switch", mout_cmu_g3d_switch_p, > + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 3), > + MUX(CLK_MOUT_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p, > + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 3), > + MUX(CLK_MOUT_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p, > + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 3), > + MUX(CLK_MOUT_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p, > + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 3), > + MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p, > + CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2), > + MUX(CLK_MOUT_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3), > + MUX(CLK_MOUT_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", mout_cmu_hsi0_dpgtc_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2), > + MUX(CLK_MOUT_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", > + mout_cmu_hsi0_usb31drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, > + 0, 1), > + MUX(CLK_MOUT_HSI0_USBDPDGB, "mout_cmu_hsi0_usbdpdbg", > + mout_cmu_hsi0_usbdpdbg_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, > + 0, 1), > + MUX(CLK_MOUT_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3), > + MUX(CLK_MOUT_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1), > + MUX(CLK_MOUT_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 3), > + MUX(CLK_MOUT_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", > + mout_cmu_hsi2_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, > + 0, 2), > + MUX(CLK_MOUT_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1), > + MUX(CLK_MOUT_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", > + mout_cmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, > + 0, 2), > + MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3), > + MUX(CLK_MOUT_ITP_BUS, "mout_cmu_itp_bus", mout_cmu_itp_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3), > + MUX(CLK_MOUT_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p, > + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 3), > + MUX(CLK_MOUT_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p, > + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3), > + MUX(CLK_MOUT_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p, > + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 3), > + MUX(CLK_MOUT_MIF_BUSP, "mout_cmu_mif_busp", mout_cmu_mif_busp_p, > + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2), > + MUX(CLK_MOUT_MIF_SWITCH, "mout_cmu_mif_switch", mout_cmu_mif_switch_p, > + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3), > + MUX(CLK_MOUT_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2), > + MUX(CLK_MOUT_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p, > + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2), > + MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 3), > + MUX(CLK_MOUT_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p, > + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 3), > + MUX(CLK_MOUT_PERIC0_BUS, "mout_cmu_peric0_bus", mout_cmu_peric0_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2), > + MUX(CLK_MOUT_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p, > + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2), > + MUX(CLK_MOUT_PERIC1_BUS, "mout_cmu_peric1_bus", mout_cmu_peric1_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2), > + MUX(CLK_MOUT_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p, > + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2), > + MUX(CLK_MOUT_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3), > + MUX(CLK_MOUT_TOP_BOOST_OPTION1, "mout_cmu_top_boost_option1", > + mout_cmu_top_boost_option1_p, > + CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 0, 1), > + MUX(CLK_MOUT_TOP_CMUREF, "mout_cmu_top_cmuref", > + mout_cmu_top_cmuref_p, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 0, 2), > + MUX(CLK_MOUT_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 3), > + MUX(CLK_MOUT_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p, > + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 3), > + MUX(CLK_MOUT_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", mout_cmu_tpu_tpuctl_p, > + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 3), > + MUX(CLK_MOUT_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p, > + CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2), > + MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", mout_cmu_cmuref_p, > + CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), > +}; > + > +static const struct samsung_div_clock cmu_top_div_clks[] __initconst = { > + DIV(CLK_DOUT_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus", > + CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4), > + DIV(CLK_DOUT_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus", > + CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4), > + DIV(CLK_DOUT_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus", > + CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4), > + DIV(CLK_DOUT_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus", > + CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4), > + DIV(CLK_DOUT_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0", > + CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5), > + DIV(CLK_DOUT_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1", > + CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5), > + DIV(CLK_DOUT_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2", > + CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5), > + DIV(CLK_DOUT_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3", > + CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5), > + DIV(CLK_DOUT_CIS_CLK4, "dout_cmu_cis_clk4", "gout_cmu_cis_clk4", > + CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5), > + DIV(CLK_DOUT_CIS_CLK5, "dout_cmu_cis_clk5", "gout_cmu_cis_clk5", > + CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5), > + DIV(CLK_DOUT_CIS_CLK6, "dout_cmu_cis_clk6", "gout_cmu_cis_clk6", > + CLK_CON_DIV_CLKCMU_CIS_CLK6, 0, 5), > + DIV(CLK_DOUT_CIS_CLK7, "dout_cmu_cis_clk7", "gout_cmu_cis_clk7", > + CLK_CON_DIV_CLKCMU_CIS_CLK7, 0, 5), > + DIV(CLK_DOUT_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus", > + CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), > + DIV(CLK_DOUT_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", "gout_cmu_cpucl0_dbg", > + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4), > + DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", > + "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3), > + DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", > + "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3), > + DIV(CLK_DOUT_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", > + "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3), > + DIV(CLK_DOUT_CSIS_BUS, "dout_cmu_csis_bus", "gout_cmu_csis_bus", > + CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4), > + DIV(CLK_DOUT_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus", > + CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4), > + DIV(CLK_DOUT_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus", > + CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4), > + DIV(CLK_DOUT_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus", > + CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4), > + DIV(CLK_DOUT_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus", > + CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4), > + DIV(CLK_DOUT_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d", > + CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4), > + DIV(CLK_DOUT_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl", > + CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4), > + DIV(CLK_DOUT_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa", > + CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4), > + DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd", > + CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4), > + DIV(CLK_DOUT_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb", > + CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4), > + DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_switch", "gout_cmu_g3d_switch", > + CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), > + DIV(CLK_DOUT_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0", > + CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4), > + DIV(CLK_DOUT_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1", > + CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4), > + DIV(CLK_DOUT_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc", > + CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4), > + DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm", > + CLK_CON_DIV_CLKCMU_HPM, 0, 2), > + DIV(CLK_DOUT_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus", > + CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4), > + DIV(CLK_DOUT_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", "gout_cmu_hsi0_dpgtc", > + CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4), > + DIV(CLK_DOUT_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", > + "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5), > + /* TODO register exists but all lower bits are reserved */ > + DIV(CLK_DOUT_HSI0_USBDPDGB, "dout_cmu_hsi0_usbdpdbg", > + "gout_cmu_hsi0_usbdpdbg", CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 0, 0), > + DIV(CLK_DOUT_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus", > + CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4), > + DIV(CLK_DOUT_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie", > + CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3), > + DIV(CLK_DOUT_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus", > + CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4), > + DIV(CLK_DOUT_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", > + "gout_cmu_hsi2_mmc_card", CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9), > + DIV(CLK_DOUT_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie", > + CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3), > + DIV(CLK_DOUT_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", > + "gout_cmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4), > + DIV(CLK_DOUT_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus", > + CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4), > + DIV(CLK_DOUT_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus", > + CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4), > + DIV(CLK_DOUT_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc", > + CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4), > + DIV(CLK_DOUT_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc", > + CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4), > + DIV(CLK_DOUT_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc", > + CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4), > + DIV(CLK_DOUT_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp", > + CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4), > + DIV(CLK_DOUT_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus", > + CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4), > + DIV(CLK_DOUT_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss", > + CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4), > + /* CLK_CON_DIV_CLKCMU_OTP lower bits reserved*/ Why the above clock where bits are reserved is declared, but this one is not? Also, above comment is marked as TODO, but this one is not. And there is no space before */. > + DIV(CLK_DOUT_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus", > + CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4), > + DIV(CLK_DOUT_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra", > + CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4), > + DIV(CLK_DOUT_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus", > + CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4), > + DIV(CLK_DOUT_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip", > + CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4), > + DIV(CLK_DOUT_PERIC1_BUS, "dout_cmu_peric1_bus", "gout_cmu_peric1_bus", > + CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4), > + DIV(CLK_DOUT_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip", > + CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4), > + DIV(CLK_DOUT_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus", > + CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4), > + DIV(CLK_DOUT_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus", > + CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4), > + DIV(CLK_DOUT_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu", > + CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4), > + DIV(CLK_DOUT_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", "gout_cmu_tpu_tpuctl", > + CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4), > + DIV(CLK_DOUT_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart", > + CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4), > + DIV(CLK_DOUT_CMU_BOOST, "dout_cmu_boost", "gout_cmu_cmu_boost", > + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2), > + DIV(CLK_DOUT_CMU_CMUREF, "dout_cmu_cmuref", "gout_cmu_cmuref", > + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2), > + DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", > + CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), > + DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", > + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), > + DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", > + CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), > + DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll", > + CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3), > + DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", > + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), > + DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", > + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), > + DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "mout_shared1_pll", > + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), > + DIV(CLK_DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll", > + CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), > + DIV(CLK_DOUT_SHARED3_DIV2, "dout_shared3_div2", "mout_shared3_pll", > + CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1), > +}; > + > +static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = { > + GATE(CLK_GOUT_BUS0_BOOST, "gout_cmu_bus0_boost", "mout_cmu_boost_option1", Please stick to 80 characters length, here and below. > + CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0), > + GATE(CLK_GOUT_BUS1_BOOST, "gout_cmu_bus1_boost", "mout_cmu_boost_option1", > + CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0), > + GATE(CLK_GOUT_BUS2_BOOST, "gout_cmu_bus2_boost", "mout_cmu_boost_option1", > + CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0), > + GATE(CLK_GOUT_CORE_BOOST, "gout_cmu_core_boost", "mout_cmu_boost_option1", > + CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0), > + GATE(CLK_GOUT_CPUCL0_BOOST, "gout_cmu_cpucl0_boost", > + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, > + 21, 0, 0), > + GATE(CLK_GOUT_CPUCL1_BOOST, "gout_cmu_cpucl1_boost", > + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, > + 21, 0, 0), > + GATE(CLK_GOUT_CPUCL2_BOOST, "gout_cmu_cpucl2_boost", > + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, > + 21, 0, 0), > + GATE(CLK_GOUT_MIF_BOOST, "gout_cmu_mif_boost", > + "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_MIF_BOOST, > + 21, 0, 0), > + GATE(CLK_GOUT_MIF_SWITCH, "gout_cmu_mif_switch", "mout_cmu_mif_switch", > + CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0), > + GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus", > + CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0), > + GATE(CLK_GOUT_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus", > + CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0), > + GATE(CLK_GOUT_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus", > + CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0), > + GATE(CLK_GOUT_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus", > + CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0), > + GATE(CLK_GOUT_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0", > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0), > + GATE(CLK_GOUT_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1", > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0), > + GATE(CLK_GOUT_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2", > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0), > + GATE(CLK_GOUT_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3", > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0), > + GATE(CLK_GOUT_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4", > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0), > + GATE(CLK_GOUT_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5", > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0), > + GATE(CLK_GOUT_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6", > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0), > + GATE(CLK_GOUT_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7", > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0), > + GATE(CLK_GOUT_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost", > + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0), > + GATE(CLK_GOUT_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus", > + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), > + GATE(CLK_GOUT_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg", > + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 21, 0, 0), > + GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", > + "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, > + 21, 0, 0), > + GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", > + "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, > + 21, 0, 0), > + GATE(CLK_GOUT_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", > + "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, > + 21, 0, 0), > + GATE(CLK_GOUT_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus", > + CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0), > + GATE(CLK_GOUT_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus", > + CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0), > + GATE(CLK_GOUT_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus", > + CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0), > + GATE(CLK_GOUT_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus", > + CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0), > + GATE(CLK_GOUT_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus", > + CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0), > + GATE(CLK_GOUT_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d", > + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0), > + GATE(CLK_GOUT_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl", > + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0), > + GATE(CLK_GOUT_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa", > + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0), > + GATE(CLK_GOUT_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd", > + CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0), > + GATE(CLK_GOUT_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb", > + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0), > + GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch", > + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0), > + GATE(CLK_GOUT_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0", > + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0), > + GATE(CLK_GOUT_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1", > + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0), > + GATE(CLK_GOUT_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc", > + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0), > + GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm", > + CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0), > + GATE(CLK_GOUT_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus", > + CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0), > + GATE(CLK_GOUT_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", "mout_cmu_hsi0_dpgtc", > + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 21, 0, 0), > + GATE(CLK_GOUT_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", > + "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, > + 21, 0, 0), > + GATE(CLK_GOUT_HSI0_USBDPDGB, "gout_cmu_hsi0_usbdpdbg", > + "mout_cmu_hsi0_usbdpdbg", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, > + 21, 0, 0), > + GATE(CLK_GOUT_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus", > + CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0), > + GATE(CLK_GOUT_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie", > + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0), > + GATE(CLK_GOUT_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus", > + CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0), > + GATE(CLK_GOUT_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", > + "mout_cmu_hsi2_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, > + 21, 0, 0), > + GATE(CLK_GOUT_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie", > + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0), > + GATE(CLK_GOUT_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", > + "mout_cmu_hsi2_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, > + 21, 0, 0), > + GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus", > + CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0), > + GATE(CLK_GOUT_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus", > + CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0), > + GATE(CLK_GOUT_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc", > + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0), > + GATE(CLK_GOUT_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc", > + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0), > + GATE(CLK_GOUT_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc", > + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0), > + GATE(CLK_GOUT_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp", > + CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0), > + GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus", > + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss", > + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0), > + GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus", > + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), > + GATE(CLK_GOUT_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra", > + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_BUS, "gout_cmu_peric0_bus", "mout_cmu_peric0_bus", > + CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip", > + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0), > + GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus", > + CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0), > + GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip", > + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0), > + GATE(CLK_GOUT_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus", > + CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0), > + GATE(CLK_GOUT_TOP_CMUREF, "gout_cmu_top_cmuref", "mout_cmu_top_cmuref", > + CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 21, 0, 0), > + GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus", > + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0), > + GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu", > + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0), > + GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl", > + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0), > + GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart", > + CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0), > +}; > + > +static const struct samsung_cmu_info top_cmu_info __initconst = { > + .pll_clks = cmu_top_pll_clks, > + .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks), > + .mux_clks = cmu_top_mux_clks, > + .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks), > + .div_clks = cmu_top_div_clks, > + .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks), > + .gate_clks = cmu_top_gate_clks, > + .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks), > + .nr_clk_ids = TOP_NR_CLK, > + .clk_regs = cmu_top_clk_regs, > + .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs), > +}; > + > +static void __init gs101_cmu_top_init(struct device_node *np) > +{ > + exynos_arm64_register_cmu(NULL, np, &top_cmu_info); > +} > + > +/* Register CMU_TOP early, as it's a dependency for other early domains */ > +CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top", > + gs101_cmu_top_init); > + > +/* ---- CMU_APM ------------------------------------------------------------- */ Suggest adding an empty line here. > +/* Register Offset definitions for CMU_APM (0x17400000) */ > +#define APM_CMU_APM_CONTROLLER_OPTION 0x0800 > +#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810 > +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000 > +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004 > +#define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800 > +#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804 > +#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808 > +#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c > +#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000 > +#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004 > +#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008 > +#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c > +#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0 As I understand, all those parts like IPCLKPORT, BLK, UID (RSTNSYNC probably too) -- they don't really mean anything in the context of the driver, just noise. And if you remove those -- there won't be any conflicts with other names, because those bits are not the unique parts. Following the TRM letter for letter in this case just makes things extremely long without adding any value IMHO. For example, that name above might be: CLK_CON_GAT_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK or even CLK_CON_GAT_GOUT_APM_SS_DBGCORE_HCLK would be fine. In clk-exynos850 driver I removed all those parts, because they make it pretty much impossible to read both the driver and dts. And yeah, because those names consequenty lead to very long string names, dts will be hard to read too, which is even worse. But again, that's only my IMHO. > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc > +#define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000 > +#define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004 > +#define PCH_CON_LHM_AXI_P_APM_PCH 0x3008 > +#define PCH_CON_LHS_AXI_D_APM_PCH 0x300c > +#define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010 > +#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014 > +#define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018 > +#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c > +#define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020 > +#define QCH_CON_APBIF_RTC_QCH 0x3024 > +#define QCH_CON_APBIF_TRTC_QCH 0x3028 > +#define QCH_CON_APM_CMU_APM_QCH 0x302c > +#define QCH_CON_APM_USI0_UART_QCH 0x3030 > +#define QCH_CON_APM_USI0_USI_QCH 0x3034 > +#define QCH_CON_APM_USI1_UART_QCH 0x3038 > +#define QCH_CON_D_TZPC_APM_QCH 0x303c > +#define QCH_CON_GPC_APM_QCH 0x3040 > +#define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044 > +#define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048 > +#define QCH_CON_INTMEM_QCH 0x304c > +#define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050 > +#define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054 > +#define QCH_CON_LHM_AXI_P_APM_QCH 0x3058 > +#define QCH_CON_LHS_AXI_D_APM_QCH 0x305c > +#define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060 > +#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064 > +#define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068 > +#define QCH_CON_MAILBOX_APM_AP_QCH 0x306c > +#define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070 > +#define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078 > +#define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c > +#define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080 > +#define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084 > +#define QCH_CON_PMU_INTR_GEN_QCH 0x3088 > +#define QCH_CON_ROM_CRC32_HOST_QCH 0x308c > +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090 > +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094 > +#define QCH_CON_SPEEDY_APM_QCH 0x3098 > +#define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c > +#define QCH_CON_SSMT_D_APM_QCH 0x30a0 > +#define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4 > +#define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8 > +#define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac > +#define QCH_CON_SYSMMU_D_APM_QCH 0x30b0 > +#define QCH_CON_SYSREG_APM_QCH 0x30b8 > +#define QCH_CON_UASC_APM_QCH 0x30bc > +#define QCH_CON_UASC_DBGCORE_QCH 0x30c0 > +#define QCH_CON_UASC_G_SWD_QCH 0x30c4 > +#define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8 > +#define QCH_CON_UASC_P_APM_QCH 0x30cc > +#define QCH_CON_WDT_APM_QCH 0x30d0 > +#define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00 > + > +static const unsigned long apm_clk_regs[] __initconst = { > + APM_CMU_APM_CONTROLLER_OPTION, > + CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, > + CLK_CON_DIV_DIV_CLK_APM_BOOST, > + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, > + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, > + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, > + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, > + CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, > + CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, > + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, > +}; > + > +PNAME(mout_apm_func_p) = { "oscclk", "mout_apm_funcsrc", > + "pad_clk_apm", "oscclk" }; > +PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", > + "pll_alv_div16_apm" }; > + > +static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { > + FRATE(CLK_APM_PLL_DIV2_APM, "pll_alv_div2_apm", NULL, 0, 393216000), > + FRATE(CLK_APM_PLL_DIV4_APM, "pll_alv_div4_apm", NULL, 0, 196608000), > + FRATE(CLK_APM_PLL_DIV16_APM, "pll_alv_div16_apm", NULL, 0, 49152000), > +}; > + > +static const struct samsung_mux_clock apm_mux_clks[] __initconst = { > + MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1), > + MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1), > +}; > + > +static const struct samsung_div_clock apm_div_clks[] __initconst = { > + DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1), > + DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7), > + DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7), > + DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7), > +}; > + > +static const struct samsung_gate_clock apm_gate_clks[] __initconst = { > + GATE(CLK_GOUT_APM_APM_CMU_APM_IPCLKPORT_PCLK, > + "gout_apm_apm_cmu_apm_ipclkport_pclk", "mout_apm_func", > + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_BUS0_BOOST_OPTION1, "gout_bus0_boost_option1", > + "dout_apm_boost", CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 21, 0, 0), > + GATE(CLK_GOUT_CMU_BOOST_OPTION1, "gout_cmu_boost_option1", > + "dout_apm_boost", CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 21, 0, 0), > + GATE(CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, "gout_core_boost_option1", > + "dout_apm_boost", CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 21, 0, 0), > + GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func", > + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0), > + GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, > + "gout_apm_gpio_alive_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, > + "gout_apm_gpio_far_alive_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, > + "gout_apm_pmu_alive_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_APBIF_RTC_IPCLKPORT_PCLK, > + "gout_apm_apbif_rtc_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_APBIF_TRTC_IPCLKPORT_PCLK, > + "gout_apm_apbif_trtc_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_APM_USI0_UART_IPCLKPORT_PCLK, > + "gout_apm_apm_usi0_uart_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLKPORT_IPCLK, > + "gout_apm_apm_usi0_usi_ipclkport_ipclk", "dout_apm_usi0_uart", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, PCLK vs IPCLK? > + 21, 0, 0), > + GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLKPORT_PCLK, > + "gout_apm_apm_usi0_usi_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, 21, 0, 0), Should it be USI0 instead of USI1? It's the same as the definition below. Also, please stick to 80 characters per line, here and below. > + GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLKPORT_IPCLK, > + "gout_apm_apm_usi1_uart_ipclkport_ipclk", "dout_apm_usi1_uart", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLKPORT_PCLK, > + "gout_apm_apm_usi1_uart_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_D_TZPC_APM_IPCLKPORT_PCLK, > + "gout_apm_d_tzpc_apm_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_GPC_APM_IPCLKPORT_PCLK, > + "gout_apm_gpc_apm_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_GREBEINTEGRATION_IPCLKPORT_HCLK, > + "gout_apm_grebeintegration", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_INTMEM_IPCLKPORT_ACLK, > + "gout_apm_uid_intmem_ipclkport_aclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_INTMEM_IPCLKPORT_PCLK, > + "gout_apm_intmem_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, > + "gout_apm_lhm_axi_g_swd_ipclkport_i_clk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, > + "gout_apm_lhm_axi_p_aocapm_ipclkport_i_clk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_LHM_AXI_P_APM_IPCLKPORT_I_CLK, > + "gout_apm_lhm_axi_p_apm_ipclkport_i_clk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_LHS_AXI_D_APM_IPCLKPORT_I_CLK, > + "gout_apm_lhs_axi_d_apm_ipclkport_i_clk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, > + "gout_apm_lhs_axi_g_dbgcore_ipclkport_i_clk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, > + "gout_apm_lhs_axi_g_scan2dram_ipclkport_i_clk", > + "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_MAILBOX_APM_AOC_IPCLKPORT_PCLK, > + "gout_apm_mailbox_apm_aoc_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_MAILBOX_APM_AP_IPCLKPORT_PCLK, > + "gout_apm_mailbox_apm_ap_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_MAILBOX_APM_GSA_IPCLKPORT_PCLK, > + "gout_apm_mailbox_apm_gsa_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_MAILBOX_APM_SWD_IPCLKPORT_PCLK, > + "gout_apm_mailbox_apm_swd_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_MAILBOX_APM_TPU_IPCLKPORT_PCLK, > + "gout_apm_mailbox_apm_tpu_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_MAILBOX_AP_AOC_IPCLKPORT_PCLK, > + "gout_apm_uid_mailbox_ap_aoc_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, > + "gout_apm_mailbox_ap_dbgcore_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_PMU_INTR_GEN_IPCLKPORT_PCLK, > + "gout_apm_pmu_intr_gen_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_ROM_CRC32_HOST_IPCLKPORT_ACLK, > + "gout_apm_rom_crc32_host_ipclkport_aclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_ROM_CRC32_HOST_IPCLKPORT_PCLK, > + "gout_apm_rom_crc32_host_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, > + "gout_apm_rstnsync_clk_cpm_bus_ipclkport_clk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, > + "gout_apm_rstnsync_clk_apm_usi0_uart_ipclkport_clk", > + "dout_apm_usi0_uart", > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, > + "gout_apm_rstnsync_clk_apm_usi0_usi_ipclkport_clk", > + "dout_apm_usi0_uart", > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, > + "gout_apm_rstnsync_clk_apm_usi1_uart_ipclkport_clk", > + "dout_apm_usi1_uart", > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_SPEEDY_APM_IPCLKPORT_PCLK, > + "gout_apm_speedy_apm_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_SPEEDY_SUB_APM_IPCLKPORT_PCLK, > + "gout_apm_speedy_sub_apm_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_SSMT_D_APM_IPCLKPORT_ACLK, > + "gout_apm_ssmt_d_apm_ipclkport_aclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_SSMT_D_APM_IPCLKPORT_PCLK, > + "gout_apm_ssmt_d_apm_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_IPCLKPORT_ACLK, > + "gout_apm_ssmt_g_dbgcore_ipclkport_aclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_IPCLKPORT_PCLK, > + "gout_apm_ssmt_g_dbgcore_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, > + "gout_apm_ss_dbgcore_ipclkport_ss_dbgcore_ipclkport_hclk", > + "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_SYSMMU_D_APM_IPCLKPORT_CLK_S2, > + "gout_apm_sysmmu_d_dpm_ipclkport_clk_s2", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_SYSREG_APM_IPCLKPORT_PCLK, > + "gout_apm_sysreg_apm_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_UASC_APM_IPCLKPORT_ACLK, > + "gout_apm_uasc_apm_ipclkport_aclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_UASC_APM_IPCLKPORT_PCLK, > + "gout_apm_uasc_apm_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_UASC_DBGCORE_IPCLKPORT_ACLK, > + "gout_apm_uasc_dbgcore_ipclkport_aclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_UASC_DBGCORE_IPCLKPORT_PCLK, > + "gout_apm_uasc_dbgcore_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_UASC_G_SWD_IPCLKPORT_ACLK, > + "gout_apm_uasc_g_swd_ipclkport_aclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_UASC_G_SWD_IPCLKPORT_PCLK, > + "gout_apm_uasc_g_swd_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), > + > + GATE(CLK_GOUT_APM_UASC_P_AOCAPM_IPCLKPORT_ACLK, > + "gout_apm_uasc_p_aocapm_ipclkport_aclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_APM_UASC_P_AOCAPM_IPCLKPORT_PCLK, > + "gout_apm_uasc_p_aocapm_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_UASC_P_APM_IPCLKPORT_ACLK, > + "gout_apm_uasc_p_apm_ipclkport_aclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_UASC_P_APM_IPCLKPORT_PCLK, > + "gout_apm_uasc_p_apm_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_WDT_APM_IPCLKPORT_PCLK, > + "gout_apm_wdt_apm_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_APM_XIU_DP_APM_IPCLKPORT_ACLK, > + "gout_apm_xiu_dp_apm_ipclkport_aclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, 0, 0), > +}; > + > +static const struct samsung_cmu_info apm_cmu_info __initconst = { > + .mux_clks = apm_mux_clks, > + .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), > + .div_clks = apm_div_clks, > + .nr_div_clks = ARRAY_SIZE(apm_div_clks), > + .gate_clks = apm_gate_clks, > + .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), > + .fixed_clks = apm_fixed_clks, > + .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), > + .nr_clk_ids = APM_NR_CLK, > + .clk_regs = apm_clk_regs, > + .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), > +}; > + > +/* ---- CMU_MISC ------------------------------------------------------------- */ Suggest adding an empty line here. > +/* Register Offset definitions for CMU_MISC (0x10010000) */ > +#define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600 > +#define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604 > +#define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610 > +#define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614 > +#define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800 > +#define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810 > +#define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000 > +#define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800 > +#define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804 Please align all values for this group at the same indentation level. > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000 > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004 > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008 > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010 Just want to give you one more example for my rant above. Look how much easier it is to understand this name (than above one): CLK_CON_GAT_MISC_OSCCLK_CLK Which also turns this (public API!): "gout_misc_rstnsync_clk_misc_oscclk_ipclkport_clk" into this: "gout_misc_oscclk_clk" > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 0x2030 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 0x2034 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 0x2038 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 0x203c > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 0x2040 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 0x2044 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 0x2048 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK 0x204c > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2050 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK 0x2054 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2058 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK 0x205c > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK 0x2060 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK 0x2064 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK 0x2068 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK 0x206c > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK 0x2070 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK 0x2074 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK 0x2078 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK 0x207c > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK 0x2080 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK 0x2084 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK 0x2088 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK 0x208c > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK 0x2090 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2094 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK 0x2098 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK 0x209c > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 0x20a0 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 0x20a4 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 0x20a8 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 0x20ac > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK 0x20b0 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK 0x20b4 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK 0x20b8 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK 0x20bc > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK 0x20c0 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK 0x20c4 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK 0x20c8 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK 0x20cc > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK 0x20d0 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK 0x20d4 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK 0x20d8 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK 0x20dc > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK 0x20e0 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK 0x20e4 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK 0x20e8 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK 0x20ec > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK 0x20f0 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 0x20f4 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 0x20f8 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK 0x20fc > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK 0x2100 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK 0x2104 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2108 > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x210c > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK 0x2110 > +#define DMYQCH_CON_PPMU_DMA_QCH 0x3000 > +#define DMYQCH_CON_PUF_QCH 0x3004 > +#define PCH_CON_LHM_AXI_D_SSS_PCH 0x300c > +#define PCH_CON_LHM_AXI_P_GIC_PCH 0x3010 > +#define PCH_CON_LHM_AXI_P_MISC_PCH 0x3014 > +#define PCH_CON_LHS_ACEL_D_MISC_PCH 0x3018 > +#define PCH_CON_LHS_AST_IRI_GICCPU_PCH 0x301c > +#define PCH_CON_LHS_AXI_D_SSS_PCH 0x3020 > +#define QCH_CON_ADM_AHB_SSS_QCH 0x3024 > +#define QCH_CON_DIT_QCH 0x3028 > +#define QCH_CON_GIC_QCH 0x3030 > +#define QCH_CON_LHM_AST_ICC_CPUGIC_QCH 0x3038 > +#define QCH_CON_LHM_AXI_D_SSS_QCH 0x303c > +#define QCH_CON_LHM_AXI_P_GIC_QCH 0x3040 > +#define QCH_CON_LHM_AXI_P_MISC_QCH 0x3044 > +#define QCH_CON_LHS_ACEL_D_MISC_QCH 0x3048 > +#define QCH_CON_LHS_AST_IRI_GICCPU_QCH 0x304c > +#define QCH_CON_LHS_AXI_D_SSS_QCH 0x3050 > +#define QCH_CON_MCT_QCH 0x3054 > +#define QCH_CON_MISC_CMU_MISC_QCH 0x3058 > +#define QCH_CON_OTP_CON_BIRA_QCH 0x305c > +#define QCH_CON_OTP_CON_BISR_QCH 0x3060 > +#define QCH_CON_OTP_CON_TOP_QCH 0x3064 > +#define QCH_CON_PDMA_QCH 0x3068 > +#define QCH_CON_PPMU_MISC_QCH 0x306c > +#define QCH_CON_QE_DIT_QCH 0x3070 > +#define QCH_CON_QE_PDMA_QCH 0x3074 > +#define QCH_CON_QE_PPMU_DMA_QCH 0x3078 > +#define QCH_CON_QE_RTIC_QCH 0x307c > +#define QCH_CON_QE_SPDMA_QCH 0x3080 > +#define QCH_CON_QE_SSS_QCH 0x3084 > +#define QCH_CON_RTIC_QCH 0x3088 > +#define QCH_CON_SPDMA_QCH 0x308c > +#define QCH_CON_SSMT_DIT_QCH 0x3090 > +#define QCH_CON_SSMT_PDMA_QCH 0x3094 > +#define QCH_CON_SSMT_PPMU_DMA_QCH 0x3098 > +#define QCH_CON_SSMT_RTIC_QCH 0x309c > +#define QCH_CON_SSMT_SPDMA_QCH 0x30a0 > +#define QCH_CON_SSMT_SSS_QCH 0x30a4 > +#define QCH_CON_SSS_QCH 0x30a8 > +#define QCH_CON_SYSMMU_MISC_QCH 0x30ac > +#define QCH_CON_SYSMMU_SSS_QCH 0x30b0 > +#define QCH_CON_SYSREG_MISC_QCH 0x30b4 > +#define QCH_CON_TMU_SUB_QCH 0x30b8 > +#define QCH_CON_TMU_TOP_QCH 0x30bc > +#define QCH_CON_WDT_CLUSTER0_QCH 0x30c0 > +#define QCH_CON_WDT_CLUSTER1_QCH 0x30c4 > +#define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC 0x3c00 > + > +static const unsigned long misc_clk_regs[] __initconst = { > + PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, > + PLL_CON1_MUX_CLKCMU_MISC_BUS_USER, > + PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, > + PLL_CON1_MUX_CLKCMU_MISC_SSS_USER, > + MISC_CMU_MISC_CONTROLLER_OPTION, > + CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0, > + CLK_CON_MUX_MUX_CLK_MISC_GIC, > + CLK_CON_DIV_DIV_CLK_MISC_BUSP, > + CLK_CON_DIV_DIV_CLK_MISC_GIC, > + CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, > + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, > + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, > + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, > + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, > + DMYQCH_CON_PPMU_DMA_QCH, > + DMYQCH_CON_PUF_QCH, > + PCH_CON_LHM_AXI_D_SSS_PCH, > + PCH_CON_LHM_AXI_P_GIC_PCH, > + PCH_CON_LHM_AXI_P_MISC_PCH, > + PCH_CON_LHS_ACEL_D_MISC_PCH, > + PCH_CON_LHS_AST_IRI_GICCPU_PCH, > + PCH_CON_LHS_AXI_D_SSS_PCH, > + QCH_CON_ADM_AHB_SSS_QCH, > + QCH_CON_DIT_QCH, > + QCH_CON_GIC_QCH, > + QCH_CON_LHM_AST_ICC_CPUGIC_QCH, > + QCH_CON_LHM_AXI_D_SSS_QCH, > + QCH_CON_LHM_AXI_P_GIC_QCH, > + QCH_CON_LHM_AXI_P_MISC_QCH, > + QCH_CON_LHS_ACEL_D_MISC_QCH, > + QCH_CON_LHS_AST_IRI_GICCPU_QCH, > + QCH_CON_LHS_AXI_D_SSS_QCH, > + QCH_CON_MCT_QCH, > + QCH_CON_MISC_CMU_MISC_QCH, > + QCH_CON_OTP_CON_BIRA_QCH, > + QCH_CON_OTP_CON_BISR_QCH, > + QCH_CON_OTP_CON_TOP_QCH, > + QCH_CON_PDMA_QCH, > + QCH_CON_PPMU_MISC_QCH, > + QCH_CON_QE_DIT_QCH, > + QCH_CON_QE_PDMA_QCH, > + QCH_CON_QE_PPMU_DMA_QCH, > + QCH_CON_QE_RTIC_QCH, > + QCH_CON_QE_SPDMA_QCH, > + QCH_CON_QE_SSS_QCH, > + QCH_CON_RTIC_QCH, > + QCH_CON_SPDMA_QCH, > + QCH_CON_SSMT_DIT_QCH, > + QCH_CON_SSMT_PDMA_QCH, > + QCH_CON_SSMT_PPMU_DMA_QCH, > + QCH_CON_SSMT_RTIC_QCH, > + QCH_CON_SSMT_SPDMA_QCH, > + QCH_CON_SSMT_SSS_QCH, > + QCH_CON_SSS_QCH, > + QCH_CON_SYSMMU_MISC_QCH, > + QCH_CON_SYSMMU_SSS_QCH, > + QCH_CON_SYSREG_MISC_QCH, > + QCH_CON_TMU_SUB_QCH, > + QCH_CON_TMU_TOP_QCH, > + QCH_CON_WDT_CLUSTER0_QCH, > + QCH_CON_WDT_CLUSTER1_QCH, > + QUEUE_CTRL_REG_BLK_MISC_CMU_MISC, > +}; > + > + /* List of parent clocks for Muxes in CMU_MISC */ > +PNAME(mout_misc_bus_user_p) = { "oscclk", "dout_cmu_misc_bus" }; > +PNAME(mout_misc_sss_user_p) = { "oscclk", "dout_cmu_misc_sss" }; > +PNAME(mout_misc_gic_p) = { "dout_misc_gic", "oscclk" }; > + > +static const struct samsung_mux_clock misc_mux_clks[] __initconst = { > + MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p, > + PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1), > + MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p, > + PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1), > + MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic", mout_misc_gic_p, > + CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 0), > +}; > + > +static const struct samsung_div_clock misc_div_clks[] __initconst = { > + DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user", > + CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3), > + DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user", > + CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3), > +}; > + > +static const struct samsung_gate_clock misc_gate_clks[] __initconst = { > + GATE(CLK_GOUT_MISC_MISC_CMU_MISC_IPCLKPORT_PCLK, > + "gout_misc_ipclkport_pclk", "dout_misc_busp", So if you want to be consistent, it should be "gout_misc_misc_misc_....". My point is -- Samsung's naming in TRM is insane. They wanted to stick to some very detailed and unified naming schema (or just generated those names from some internal clock tree data), granted. But I'm just not sure if it's the best idea to follow it in driver's code. > + CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, > + "gout_misc_otp_con_bira_ipclkport_i_oscclk", "dout_misc_busp", > + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, > + "gout_misc_otp_con_bisr_ipclkport_i_oscclk", "dout_misc_busp", > + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, > + "gout_misc_otp_con_top_ipclkport_i_oscclk", "dout_misc_busp", > + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, > + "gout_misc_rstnsync_clk_misc_oscclk_ipclkport_clk", > + "dout_misc_busp", > + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_ADM_AHB_SSS_IPCLKPORT_HCLKM, > + "gout_misc_adm_ahb_sss_ipclkport_hclkm", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_AD_APB_DIT_IPCLKPORT_PCLKM, > + "gout_misc_ad_apb_dit_ipclkport_pclkm", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_D_TZPC_MISC_IPCLKPORT_PCLK, > + "gout_misc_d_tzpc_misc_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_GIC_IPCLKPORT_GICCLK, > + "gout_misc_gic_ipclkport_gicclk", "mout_misc_gic", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_GPC_MISC_IPCLKPORT_PCLK, > + "gout_misc_gpc_misc_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, > + "gout_misc_lhm_ast_icc_gpugic_ipclkport_i_clk", "mout_misc_gic", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, > + "gout_misc_lhm_axi_d_sss_ipclkport_i_clk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, > + "gout_misc_lhm_axi_p_gic_ipclkport_i_clk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, > + "gout_misc_lhm_axi_p_misc_ipclkport_i_clk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, > + "gout_misc_lhs_acel_d_misc_ipclkport_i_clk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, > + "gout_misc_lhs_ast_iri_giccpu_ipclkport_i_clk", "mout_misc_gic", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, > + "gout_misc_lhs_axi_d_sss_ipclkport_i_clk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_MCT_IPCLKPORT_PCLK, "gout_misc_mct_ipclkport_pclk", > + "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_OTP_CON_BIRA_IPCLKPORT_PCLK, > + "gout_misc_otp_con_bira_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_OTP_CON_BISR_IPCLKPORT_PCLK, > + "gout_misc_otp_con_bisr_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_OTP_CON_TOP_IPCLKPORT_PCLK, > + "gout_misc_otp_con_top_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_PDMA_IPCLKPORT_ACLK, "gout_misc_pdma_ipclkport_aclk", > + "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_PPMU_MISC_IPCLKPORT_ACLK, > + "gout_misc_ppmu_misc_ipclkport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_PPMU_MISC_IPCLKPORT_PCLK, > + "gout_misc_ppmu_misc_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_PUF_IPCLKPORT_I_CLK, > + "gout_misc_puf_ipclkport_i_clk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_QE_DIT_IPCLKPORT_ACLK, > + "gout_misc_qe_dit_ipclkport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_QE_DIT_IPCLKPORT_PCLK, > + "gout_misc_qe_dit_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_QE_PDMA_IPCLKPORT_ACLK, > + "gout_misc_qe_pdma_ipclkport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_QE_PDMA_IPCLKPORT_PCLK, > + "gout_misc_qe_pdma_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_QE_PPMU_DMA_IPCLKPORT_ACLK, > + "gout_misc_qe_ppmu_dma_ipclkport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_QE_PPMU_DMA_IPCLKPORT_PCLK, > + "gout_misc_qe_ppmu_dma_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_QE_RTIC_IPCLKPORT_ACLK, > + "gout_misc_qe_rtic_ipclkport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_QE_RTIC_IPCLKPORT_PCLK, > + "gout_misc_qe_rtic_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_QE_SPDMA_IPCLKPORT_ACLK, > + "gout_misc_qe_spdma_ipclkport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_QE_SPDMA_IPCLKPORT_PCLK, > + "gout_misc_qe_spdma_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_QE_SSS_IPCLKPORT_ACLK, > + "gout_misc_qe_sss_ipclkport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_QE_SSS_IPCLKPORT_PCLK, > + "gout_misc_qe_sss_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, > + "gout_misc_rstnsync_clk_misc_busd_ipclkport_clk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, > + "gout_misc_rstnsync_clk_misc_busp_ipclkport_clk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, > + "gout_misc_rstnsync_clk_misc_gic_ipclkport_clk", "mout_misc_gic", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, > + "gout_misc_rstnsync_clk_misc_sss_ipclkport_clk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_RTIC_IPCLKPORT_I_ACLK, > + "gout_misc_rtic_ipclkport_i_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_RTIC_IPCLKPORT_I_PCLK, "gout_misc_rtic_ipclkport_i_pclk", 80 characters per line please. > + "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SPDMA_IPCLKPORT_ACLK, > + "gout_misc_spdma_ipclockport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSMT_DIT_IPCLKPORT_ACLK, > + "gout_misc_ssmt_dit_ipclkport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSMT_DIT_IPCLKPORT_PCLK, > + "gout_misc_ssmt_dit_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSMT_PDMA_IPCLKPORT_ACLK, > + "gout_misc_ssmt_pdma_ipclkport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSMT_PDMA_IPCLKPORT_PCLK, > + "gout_misc_ssmt_pdma_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_IPCLKPORT_ACLK, > + "gout_misc_ssmt_ppmu_dma_ipclkport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_IPCLKPORT_PCLK, > + "gout_misc_ssmt_ppmu_dma_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSMT_RTIC_IPCLKPORT_ACLK, > + "gout_misc_ssmt_rtic_ipclkport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSMT_RTIC_IPCLKPORT_PCLK, > + "gout_misc_ssmt_rtic_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSMT_SPDMA_IPCLKPORT_ACLK, > + "gout_misc_ssmt_spdma_ipclkport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSMT_SPDMA_IPCLKPORT_PCLK, > + "gout_misc_ssmt_spdma_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSMT_SSS_IPCLKPORT_ACLK, > + "gout_misc_ssmt_sss_ipclkport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSMT_SSS_IPCLKPORT_PCLK, > + "gout_misc_ssmt_sss_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSS_IPCLKPORT_I_ACLK, > + "gout_misc_sss_ipclkport_i_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSS_IPCLKPORT_I_PCLK, > + "gout_misc_sss_ipclkport_i_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SYSMMU_MISC_IPCLKPORT_CLK_S2, > + "gout_misc_sysmmu_misc_ipclkport_clk_s2", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SYSMMU_SSS_IPCLKPORT_CLK_S1, > + "gout_misc_sysmmu_sss_ipclkport_clk_s1", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_SYSREG_MISC_IPCLKPORT_PCLK, > + "gout_misc_sysreg_misc_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_TMU_SUB_IPCLKPORT_PCLK, > + "gout_misc_tmu_sub_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_TMU_TOP_IPCLKPORT_PCLK, > + "gout_misc_tmu_top_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_WDT_CLUSTER0_IPCLKPORT_PCLK, > + "gout_misc_wdt_cluster0_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_WDT_CLUSTER1_IPCLKPORT_PCLK, > + "gout_misc_wdt_cluster1_ipclkport_pclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_MISC_XIU_D_MISC_IPCLKPORT_ACLK, > + "gout_misc_xiu_d_misc_ipclkport_aclk", "dout_misc_busp", > + CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, > + 21, 0, 0), > +}; > + > +static const struct samsung_cmu_info misc_cmu_info __initconst = { > + .mux_clks = misc_mux_clks, > + .nr_mux_clks = ARRAY_SIZE(misc_mux_clks), > + .div_clks = misc_div_clks, > + .nr_div_clks = ARRAY_SIZE(misc_div_clks), > + .gate_clks = misc_gate_clks, > + .nr_gate_clks = ARRAY_SIZE(misc_gate_clks), > + .nr_clk_ids = MISC_NR_CLK, > + .clk_regs = misc_clk_regs, > + .nr_clk_regs = ARRAY_SIZE(misc_clk_regs), > + .clk_name = "dout_cmu_misc_bus", > +}; > + > +/* ---- platform_driver ----------------------------------------------------- */ > + > +static int __init gs101_cmu_probe(struct platform_device *pdev) > +{ > + const struct samsung_cmu_info *info; > + struct device *dev = &pdev->dev; > + > + info = of_device_get_match_data(dev); > + exynos_arm64_register_cmu(dev, dev->of_node, info); > + > + return 0; > +} > + > +static const struct of_device_id gs101_cmu_of_match[] = { > + { > + .compatible = "google,gs101-cmu-apm", > + .data = &apm_cmu_info, > + }, { > + .compatible = "google,gs101-cmu-misc", > + .data = &misc_cmu_info, > + }, { > + }, > +}; > + > +static struct platform_driver gs101_cmu_driver __refdata = { > + .driver = { > + .name = "gs101-cmu", > + .of_match_table = gs101_cmu_of_match, > + .suppress_bind_attrs = true, > + }, > + .probe = gs101_cmu_probe, > +}; > + > +static int __init gs101_cmu_init(void) > +{ > + return platform_driver_register(&gs101_cmu_driver); > +} > +core_initcall(gs101_cmu_init); > -- > 2.43.0.rc2.451.g8631bc7472-goog >
On 12/01/2023, Peter Griffin wrote: > Newer Exynos SoCs have a filter selection register on alive bank pins. > This allows the selection of a digital or delay filter for each pin. If > the filter selection register is not available then the default filter > (digital) is applied. > > On suspend we apply the analog filter to all pins in the bank (as the > digital filter relies on a clock). On resume the digital filter is > reapplied to all pins in the bank. The digital filter is working via > clock and has an adjustable filter delay register bitfield, whereas > the analog filter uses a fixed delay. > > The filter determines to what extent signal fluctuations received through > the pad are considered glitches. > > The code path can be exercised using > echo mem > /sys/power/state > And then wake the device using a eint gpio > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> -- I verified boot and that the pinctrl driver is probing. When I tested echo mem > /sys/power/state I wasn't able to re-wake the device (not sure how to send an eint gpio on a phone form factor). I tried with no_console_suspend but that hits a SError Interrupt (likely due to a PMU secure register access). Let me know if there's anything else I should test out. Thanks, Will > --- > drivers/pinctrl/samsung/pinctrl-exynos.c | 89 ++++++++++++++++++++++- > drivers/pinctrl/samsung/pinctrl-exynos.h | 7 ++ > drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + > drivers/pinctrl/samsung/pinctrl-samsung.h | 22 ++++++ > 4 files changed, 119 insertions(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c > index 6b58ec84e34b..56fc11a1fe2f 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c > @@ -269,6 +269,71 @@ struct exynos_eint_gpio_save { > u32 eint_mask; > }; > > +/* > + * Set the desired filter (digital or analog delay) to every pin in > + * the bank. Note the filter selection bitfield is only found on alive > + * banks. The filter determines to what extent signal fluctuations > + * received through the pad are considered glitches. > + */ > +static void exynos_eint_flt_config(struct samsung_pinctrl_drv_data *d, > + struct samsung_pin_bank *bank, int filter) > +{ > + unsigned int flt_reg, flt_con = 0; > + unsigned int val, shift; > + int i; > + int loop_cnt; > + > + /* > + * The FLTCON register has the following layout > + * > + * BitfieldName[PinNum][Bit:Bit] > + * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24] > + * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16] > + * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8] > + * FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0] > + * > + * FLT_EN 0x0 = Disable, 0x1=Enable > + * FLT_SEL 0x0 = Delay filter, 0x1 Digital filter > + * FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1 > + */ > + > + flt_con |= EXYNOS9_FLTCON_EN; > + > + if (filter) > + flt_con |= EXYNOS9_FLTCON_DIGITAL; > + > + flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset; > + > + /* > + * If nr_pins > 4, we should set FLTCON0 register fully. > + * (pin0 ~ 3). So loop 4 times in case of FLTCON0. > + */ > + if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN) > + loop_cnt = EXYNOS9_FLTCON_NR_PIN; > + else > + loop_cnt = bank->nr_pins; > + > + val = readl(d->virt_base + flt_reg); > + for (i = 0; i < loop_cnt; i++) { > + shift = i * EXYNOS9_FLTCON_LEN; > + val &= ~(EXYNOS9_FLTCON_MASK << shift); > + val |= (flt_con << shift); > + } > + writel(val, d->virt_base + flt_reg); > + > + /* Loop for FLTCON1 pin 4 ~ 7 */ > + if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN) { > + loop_cnt = (bank->nr_pins - EXYNOS9_FLTCON_NR_PIN); > + val = readl(d->virt_base + flt_reg + 0x4); > + for (i = 0; i < loop_cnt; i++) { > + shift = i * EXYNOS9_FLTCON_LEN; > + val &= ~(EXYNOS9_FLTCON_MASK << shift); > + val |= (flt_con << shift); > + } > + writel(val, d->virt_base + flt_reg + 0x4); > + } > +} > + > /* > * exynos_eint_gpio_init() - setup handling of external gpio interrupts. > * @d: driver data of samsung pinctrl driver. > @@ -321,6 +386,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) > goto err_domains; > } > > + /* Set Delay Analog Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(d, bank, > + EXYNOS9_FLTCON_DELAY); > } > > return 0; > @@ -555,6 +624,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) > if (bank->eint_type != EINT_TYPE_WKUP) > continue; > > + /* Set Digital Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(d, bank, > + EXYNOS9_FLTCON_DIGITAL); > + > bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), > GFP_KERNEL); > if (!bank->irq_chip) { > @@ -658,6 +732,7 @@ static void exynos_pinctrl_suspend_bank( > void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > { > struct samsung_pin_bank *bank = drvdata->pin_banks; > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > struct exynos_irq_chip *irq_chip = NULL; > int i; > > @@ -665,6 +740,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > if (bank->eint_type == EINT_TYPE_GPIO) > exynos_pinctrl_suspend_bank(drvdata, bank); > else if (bank->eint_type == EINT_TYPE_WKUP) { > + /* Setting Delay (Analog) Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(d, bank, > + EXYNOS9_FLTCON_DELAY); > if (!irq_chip) { > irq_chip = bank->irq_chip; > irq_chip->set_eint_wakeup_mask(drvdata, > @@ -707,11 +786,19 @@ static void exynos_pinctrl_resume_bank( > void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) > { > struct samsung_pin_bank *bank = drvdata->pin_banks; > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > int i; > > for (i = 0; i < drvdata->nr_banks; ++i, ++bank) > - if (bank->eint_type == EINT_TYPE_GPIO) > + if (bank->eint_type == EINT_TYPE_GPIO) { > exynos_pinctrl_resume_bank(drvdata, bank); > + } else if (bank->eint_type == EINT_TYPE_WKUP || > + bank->eint_type == EINT_TYPE_WKUP_MUX) { > + /* Set Digital Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(d, bank, > + EXYNOS9_FLTCON_DIGITAL); > + } > } > > static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h > index 3ac52c2cf998..e2799ff1b5e9 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos.h > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h > @@ -50,6 +50,13 @@ > > #define EXYNOS_EINT_MAX_PER_BANK 8 > #define EXYNOS_EINT_NR_WKUP_EINT > +/* EINT filter configuration */ > +#define EXYNOS9_FLTCON_EN BIT(7) > +#define EXYNOS9_FLTCON_DIGITAL BIT(6) > +#define EXYNOS9_FLTCON_DELAY (0 << 6) > +#define EXYNOS9_FLTCON_MASK 0xff > +#define EXYNOS9_FLTCON_LEN 8 > +#define EXYNOS9_FLTCON_NR_PIN 4 > > #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ > { \ > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c > index 79babbb39ced..50c360b4753a 100644 > --- a/drivers/pinctrl/samsung/pinctrl-samsung.c > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c > @@ -1105,6 +1105,8 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, > bank->eint_func = bdata->eint_func; > bank->eint_type = bdata->eint_type; > bank->eint_mask = bdata->eint_mask; > + bank->fltcon_type = bdata->fltcon_type; > + bank->fltcon_offset = bdata->fltcon_offset; > bank->eint_offset = bdata->eint_offset; > bank->name = bdata->name; > > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h > index 9b3db50adef3..5fab3885a7d7 100644 > --- a/drivers/pinctrl/samsung/pinctrl-samsung.h > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h > @@ -82,6 +82,20 @@ enum eint_type { > EINT_TYPE_WKUP_MUX, > }; > > +/** > + * enum fltcon_type - filter selection > + * @FLT_DEFAULT: filter not selectable, default digital filter > + * @FLT_SELECT: filter selectable (digital or delay) > + * > + * Some banks on newer Exynos based SoCs have a selectable filter on alive > + * banks of 'analog/delay' or 'digital'. If the filter selection register is > + * not available then the default filter is used (digital). > + */ > +enum fltcon_type { > + FLT_DEFAULT, > + FLT_SELECTABLE, > +}; > + > /* maximum length of a pin in pin descriptor (example: "gpa0-0") */ > #define PIN_NAME_LENGTH 10 > > @@ -122,6 +136,8 @@ struct samsung_pin_bank_type { > * @eint_type: type of the external interrupt supported by the bank. > * @eint_mask: bit mask of pins which support EINT function. > * @eint_offset: SoC-specific EINT register or interrupt offset of bank. > + * @fltcon_type: whether the filter (delay/digital) is selectable > + * @fltcon_offset: SoC-specific EINT filter control register offset of bank. > * @name: name to be prefixed for each pin in this pin bank. > */ > struct samsung_pin_bank_data { > @@ -133,6 +149,8 @@ struct samsung_pin_bank_data { > enum eint_type eint_type; > u32 eint_mask; > u32 eint_offset; > + enum fltcon_type fltcon_type; > + u32 fltcon_offset; > const char *name; > }; > > @@ -147,6 +165,8 @@ struct samsung_pin_bank_data { > * @eint_type: type of the external interrupt supported by the bank. > * @eint_mask: bit mask of pins which support EINT function. > * @eint_offset: SoC-specific EINT register or interrupt offset of bank. > + * @fltcon_type: whether the filter (delay/digital) is selectable > + * @fltcon_offset: SoC-specific EINT filter control register offset of bank. > * @name: name to be prefixed for each pin in this pin bank. > * @id: id of the bank, propagated to the pin range. > * @pin_base: starting pin number of the bank. > @@ -170,6 +190,8 @@ struct samsung_pin_bank { > enum eint_type eint_type; > u32 eint_mask; > u32 eint_offset; > + enum fltcon_type fltcon_type; > + u32 fltcon_offset; > const char *name; > u32 id; > > -- > 2.43.0.rc2.451.g8631bc7472-goog >
On 12/01/2023, Peter Griffin wrote: > The WDT uses the CPU core signal DBGACK to determine whether the SoC > is running in debug mode or not. If the DBGACK signal is asserted and > DBGACK_MASK bit is enabled, then WDT output and interrupt is masked > (disabled). > > Presence of the DBGACK_MASK bit is determined by adding a new > QUIRK_HAS_DBGACK_BIT quirk. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> --- I verified boot to a busybox console and that the watchdog probes. Regards, Will > --- > drivers/watchdog/s3c2410_wdt.c | 27 ++++++++++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > index 0b4bd883ff28..39f3489e41d6 100644 > --- a/drivers/watchdog/s3c2410_wdt.c > +++ b/drivers/watchdog/s3c2410_wdt.c > @@ -34,9 +34,10 @@ > > #define S3C2410_WTCNT_MAXCNT 0xffff > > -#define S3C2410_WTCON_RSTEN (1 << 0) > -#define S3C2410_WTCON_INTEN (1 << 2) > -#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_RSTEN (1 << 0) > +#define S3C2410_WTCON_INTEN (1 << 2) > +#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_DBGACK_MASK (1 << 16) > > #define S3C2410_WTCON_DIV16 (0 << 3) > #define S3C2410_WTCON_DIV32 (1 << 3) > @@ -100,12 +101,17 @@ > * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) > * with "watchdog counter enable" bit. That bit should be set to make watchdog > * counter running. > + * > + * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the > + * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. > + * Debug mode is determined by the DBGACK CPU signal. > */ > #define QUIRK_HAS_WTCLRINT_REG (1 << 0) > #define QUIRK_HAS_PMU_MASK_RESET (1 << 1) > #define QUIRK_HAS_PMU_RST_STAT (1 << 2) > #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) > #define QUIRK_HAS_PMU_CNT_EN (1 << 4) > +#define QUIRK_HAS_DBGACK_BIT (1 << 5) > > /* These quirks require that we have a PMU register map */ > #define QUIRKS_HAVE_PMUREG \ > @@ -375,6 +381,19 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) > return 0; > } > > +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt) > +{ > + unsigned long wtcon; > + > + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)) > + return; > + > + /* disable watchdog outputs if CPU is in debug mode */ > + wtcon = readl(wdt->reg_base + S3C2410_WTCON); > + wtcon |= S3C2410_WTCON_DBGACK_MASK; > + writel(wtcon, wdt->reg_base + S3C2410_WTCON); > +} > + > static int s3c2410wdt_keepalive(struct watchdog_device *wdd) > { > struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); > @@ -700,6 +719,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); > wdt->wdt_device.parent = dev; > > + s3c2410wdt_mask_dbgack(wdt); > + > /* > * If "tmr_atboot" param is non-zero, start the watchdog right now. Also > * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. > -- > 2.43.0.rc2.451.g8631bc7472-goog >
On 12/01/2023, Peter Griffin wrote: > Add serial driver data for Google Tensor gs101 SoC and a common > fifoszdt_serial_drv_data that can be used by platforms that specify the > samsung,uart-fifosize DT property. > > A corresponding dt-bindings patch updates the yaml to ensure > samsung,uart-fifosize is a required property. > > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Reviewed-by: Arnd Bergmann <arnd@arndb.de> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> --- I verified boot to a busybox console with kernel logs printed to the serial port. Regards, Will > --- > drivers/tty/serial/samsung_tty.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c > index 1b0c2b467a30..f8d98f1006de 100644 > --- a/drivers/tty/serial/samsung_tty.c > +++ b/drivers/tty/serial/samsung_tty.c > @@ -2490,14 +2490,25 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { > .fifosize = { 256, 64, 64, 64 }, > }; > > +/* > + * Common drv_data struct for platforms that specify uart,fifosize in > + * device tree. > + */ > +static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = { > + EXYNOS_COMMON_SERIAL_DRV_DATA(), > + .fifosize = { 0 }, > +}; > + > #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data) > #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data) > #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data) > +#define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data) > > #else > #define EXYNOS4210_SERIAL_DRV_DATA NULL > #define EXYNOS5433_SERIAL_DRV_DATA NULL > #define EXYNOS850_SERIAL_DRV_DATA NULL > +#define EXYNOS_FIFOSZDT_DRV_DATA NULL > #endif > > #ifdef CONFIG_ARCH_APPLE > @@ -2581,6 +2592,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = { > }, { > .name = "artpec8-uart", > .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, > + }, { > + .name = "gs101-uart", > + .driver_data = (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA, > }, > { }, > }; > @@ -2602,6 +2616,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { > .data = EXYNOS850_SERIAL_DRV_DATA }, > { .compatible = "axis,artpec8-uart", > .data = ARTPEC8_SERIAL_DRV_DATA }, > + { .compatible = "google,gs101-uart", > + .data = EXYNOS_FIFOSZDT_DRV_DATA }, > {}, > }; > MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); > -- > 2.43.0.rc2.451.g8631bc7472-goog >
On 12/01/2023, Peter Griffin wrote: > Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6, > (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile > phones. It features: > * 4xA55 little cluster > * 2xA76 Mid cluster > * 2xX1 Big cluster > > This commit adds the basic device tree for gs101 (SoC). > Further platform support will be added over time. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> -- Verified boot to a busybox console on my oriole device. Thanks, Will > --- > .../boot/dts/exynos/google/gs101-pinctrl.dtsi | 1250 +++++++++++++++++ > .../boot/dts/exynos/google/gs101-pinctrl.h | 33 + > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 476 +++++++ > 3 files changed, 1759 insertions(+) > create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi > create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > create mode 100644 arch/arm64/boot/dts/exynos/google/gs101.dtsi > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi > new file mode 100644 > index 000000000000..8c0f0cf75edb > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi > @@ -0,0 +1,1250 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * GS101 SoC pin-mux and pin-config device tree source > + * > + * Copyright 2019-2023 Google LLC > + * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> > + */ > + > +#include "gs101-pinctrl.h" > + > +&pinctrl_gpio_alive { > + gpa0: gpa0-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa1: gpa1-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa2: gpa2-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa3: gpa3-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa4: gpa4-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa5: gpa5-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa9: gpa9-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa10: gpa10-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + uart15_bus: uart15-bus-pins { > + samsung,pins = "gpa2-3", "gpa2-4"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + uart16_bus: uart16-bus-pins { > + samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + uart17_bus: uart17-bus-pins { > + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi15_bus: spi15-bus-pins { > + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi15_cs: spi15-cs-pins { > + samsung,pins = "gpa4-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > +}; > + > +&pinctrl_far_alive { > + gpa6: gpa6-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa7: gpa7-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa8: gpa8-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa11: gpa11-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > +}; > + > +&pinctrl_gsacore { > + gps0: gps0-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gps1: gps1-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gps2: gps2-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > +}; > + > +&pinctrl_gsactrl { > + gps3: gps3-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > +}; > + > +&pinctrl_hsi1 { > + gph0: gph0-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gph1: gph1-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + pcie0_clkreq: pcie0-clkreq-pins{ > + samsung,pins = "gph0-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_UP>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + samsung,pin-pud-pdn = <GS101_PIN_PULL_UP>; > + }; > + > + pcie0_perst: pcie0-perst-pins { > + samsung,pins = "gph0-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + }; > +}; > + > +&pinctrl_hsi2 { > + gph2: gph2-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gph3: gph3-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gph4: gph4-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + sd2_clk: sd2-clk-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_cmd: sd2-cmd-pins { > + samsung,pins = "gph4-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_UP>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_bus1: sd2-bus-width1-pins { > + samsung,pins = "gph4-2"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_UP>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_bus4: sd2-bus-width4-pins { > + samsung,pins = "gph4-3", "gph4-4", "gph4-5"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_UP>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + }; > + > + ufs_rst_n: ufs-rst-n-pins { > + samsung,pins = "gph3-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>; > + }; > + > + ufs_refclk_out: ufs-refclk-out-pins { > + samsung,pins = "gph3-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>; > + }; > + > + pcie1_clkreq: pcie1-clkreq-pins { > + samsung,pins = "gph2-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_UP>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + samsung,pin-pud-pdn = <GS101_PIN_PULL_UP>; > + }; > + > + pcie1_perst: pcie1-perst-pins { > + samsung,pins = "gph2-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + }; > +}; > + > +&pinctrl_peric0 { > + gpp0: gpp0-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp1: gpp1-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp2: gpp2-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp3: gpp3-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp4: gpp4-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp5: gpp5-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp6: gpp6-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp7: gpp7-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp8: gpp8-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp9: gpp9-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp10: gpp10-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp11: gpp11-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp12: gpp12-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp13: gpp13-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp14: gpp14-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp15: gpp15-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp16: gpp16-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp17: gpp17-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp18: gpp18-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp19: gpp19-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + /* USI_PERIC0_UART_DBG */ > + uart0_bus: uart0-bus-pins { > + samsung,pins = "gpp1-2", "gpp1-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + disp_te_pri_on: disp-te-pri-on-pins { > + samsung,pins = "gpp0-3"; > + samsung,pin-function = <GS101_PIN_FUNC_EINT>; > + }; > + > + disp_te_pri_off: disp-te-pri-off-pins { > + samsung,pins = "gpp0-3"; > + samsung,pin-function = <GS101_PIN_FUNC_INPUT>; > + }; > + > + disp_te_sec_on: disp-te-sec-on-pins { > + samsung,pins = "gpp0-4"; > + samsung,pin-function = <GS101_PIN_FUNC_EINT>; > + }; > + > + disp_te_sec_off: disp-te-sec-off-pins { > + samsung,pins = "gpp0-4"; > + samsung,pin-function = <GS101_PIN_FUNC_INPUT>; > + }; > + > + sensor_mclk1_out: sensor-mclk1-out-pins { > + samsung,pins = "gpp3-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk1_fn: sensor-mclk1-fn-pins { > + samsung,pins = "gpp3-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk2_out: sensor-mclk2-out-pins { > + samsung,pins = "gpp5-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk2_fn: sensor-mclk2-fn-pins { > + samsung,pins = "gpp5-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk3_out: sensor-mclk3-out-pins { > + samsung,pins = "gpp7-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk3_fn: sensor-mclk3-fn-pins { > + samsung,pins = "gpp7-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk4_out: sensor-mclk4-out-pins { > + samsung,pins = "gpp9-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk4_fn: sensor-mclk4-fn-pins { > + samsung,pins = "gpp9-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk5_out: sensor-mclk5-out-pins { > + samsung,pins = "gpp11-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk5_fn: sensor-mclk5-fn-pins { > + samsung,pins = "gpp11-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk6_out: sensor-mclk6-out-pins { > + samsung,pins = "gpp13-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk6_fn: sensor-mclk6-fn-pins { > + samsung,pins = "gpp13-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk7_out: sensor-mclk7-out-pins { > + samsung,pins = "gpp15-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk7_fn: sensor-mclk7-fn-pins { > + samsung,pins = "gpp15-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk8_out: sensor-mclk8-out-pins { > + samsung,pins = "gpp17-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk8_fn: sensor-mclk8-fn-pins { > + samsung,pins = "gpp17-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + hsi2c14_bus: hsi2c14-bus-pins { > + samsung,pins = "gpp18-0", "gpp18-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart14_bus_single: uart14-bus-pins { > + samsung,pins = "gpp18-0", "gpp18-1", > + "gpp18-2", "gpp18-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi14_bus: spi14-bus-pins { > + samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi14_cs: spi14-cs-pins { > + samsung,pins = "gpp18-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi14_cs_func: spi14-cs-func-pins { > + samsung,pins = "gpp18-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c8_bus: hsi2c8-bus-pins { > + samsung,pins = "gpp16-0", "gpp16-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + samsung,pin-pud-pdn = <GS101_PIN_PDN_OUT0>; > + }; > + > + uart8_bus_single: uart8-bus-pins { > + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2", > + "gpp16-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi8_bus: spi8-bus-pins { > + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi8_cs: spi8-cs-pins { > + samsung,pins = "gpp16-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi8_cs_func: spi8-cs-func-pins { > + samsung,pins = "gpp16-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c7_bus: hsi2c7-bus-pins { > + samsung,pins = "gpp14-0", "gpp14-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart7_bus_single: uart7-bus-pins { > + samsung,pins = "gpp14-0", "gpp14-1", > + "gpp14-2", "gpp14-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi7_bus: spi7-bus-pins { > + samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi7_cs: spi7-cs-pins { > + samsung,pins = "gpp14-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi7_cs_func: spi7-cs-func-pins { > + samsung,pins = "gpp14-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c6_bus: hsi2c6-bus-pins { > + samsung,pins = "gpp12-0", "gpp12-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart6_bus_single: uart6-bus-pins { > + samsung,pins = "gpp12-0", "gpp12-1", > + "gpp12-2", "gpp12-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi6_bus: spi6-bus-pins { > + samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi6_cs: spi6-cs-pins { > + samsung,pins = "gpp12-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi6_cs_func: spi6-cs-func-pins { > + samsung,pins = "gpp12-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c5_bus: hsi2c5-bus-pins { > + samsung,pins = "gpp10-0", "gpp10-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart5_bus_single: uart5-bus-pins { > + samsung,pins = "gpp10-0", "gpp10-1", > + "gpp10-2", "gpp10-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi5_bus: spi5-bus-pins { > + samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2"; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>; > + }; > + > + spi5_cs_func: spi5-cs-func-pins { > + samsung,pins = "gpp10-3"; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>; > + }; > + > + hsi2c4_bus: hsi2c4-bus-pins { > + samsung,pins = "gpp8-0", "gpp8-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart4_bus_single: uart4-bus-pins { > + samsung,pins = "gpp8-0", "gpp8-1", > + "gpp8-2", "gpp8-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi4_bus: spi4-bus-pins { > + samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi4_cs: spi4-cs-pins { > + samsung,pins = "gpp8-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi4_cs_func: spi4-cs-func-pins { > + samsung,pins = "gpp8-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c3_bus: hsi2c3-bus-pins { > + samsung,pins = "gpp6-0", "gpp6-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart3_bus_single: uart3-bus-pins { > + samsung,pins = "gpp6-0", "gpp6-1", > + "gpp6-2", "gpp6-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi3_bus: spi3-bus-pins { > + samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi3_cs: spi3-cs-pins { > + samsung,pins = "gpp6-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi3_cs_func: spi3-cs-func-pins { > + samsung,pins = "gpp6-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c2_bus: hsi2c2-bus-pins { > + samsung,pins = "gpp4-0", "gpp4-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart2_bus_single: uart2-bus-pins { > + samsung,pins = "gpp4-0", "gpp4-1", > + "gpp4-2", "gpp4-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi2_bus: spi2-bus-pins { > + samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi2_cs: spi2-cs-pins { > + samsung,pins = "gpp4-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi2_cs_func: spi2-cs-func-pins { > + samsung,pins = "gpp4-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c1_bus: hsi2c1-bus-pins { > + samsung,pins = "gpp2-0", "gpp2-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart1_bus_single: uart1-bus-pins { > + samsung,pins = "gpp2-0", "gpp2-1", > + "gpp2-2", "gpp2-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi1_bus: spi1-bus-pins { > + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi1_cs: spi1-cs-pins { > + samsung,pins = "gpp2-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi1_cs_func: spi1-cs-func-pins { > + samsung,pins = "gpp2-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > +}; > + > +&pinctrl_peric1 { > + gpp20: gpp20-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp21: gpp21-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp22: gpp22-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp23: gpp23-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp24: gpp24-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp25: gpp25-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp26: gpp26-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp27: gpp27-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + hsi2c13_bus: hsi2c13-bus-pins { > + samsung,pins = "gpp25-0", "gpp25-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart13_bus_single: uart13-bus-pins { > + samsung,pins = "gpp25-0", "gpp25-1", > + "gpp25-2", "gpp25-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi13_bus: spi13-bus-pins { > + samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi13_cs: spi13-cs-pins { > + samsung,pins = "gpp25-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi13_cs_func: spi13-cs-func-pins { > + samsung,pins = "gpp25-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c12_bus: hsi2c12-bus-pins { > + samsung,pins = "gpp23-4", "gpp23-5"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart12_bus_single: uart12-bus-pins { > + samsung,pins = "gpp23-4", "gpp23-5", > + "gpp23-6", "gpp23-7"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi12_bus: spi12-bus-pins { > + samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi14_cs2: spi14-cs2-pins { > + samsung,pins = "gpp23-6"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi12_cs: spi12-cs-pins { > + samsung,pins = "gpp23-7"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi12_cs_func: spi12-cs-func-pins { > + samsung,pins = "gpp23-7"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c11_bus: hsi2c11-bus-pins { > + samsung,pins = "gpp23-0", "gpp23-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart11_bus_single: uart11-bus-pins { > + samsung,pins = "gpp23-0", "gpp23-1", > + "gpp23-2", "gpp23-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi11_bus: spi11-bus-pins { > + samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi11_cs: spi11-cs-pins { > + samsung,pins = "gpp23-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi11_cs_func: spi11-cs-func-pins { > + samsung,pins = "gpp23-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c10_bus: hsi2c10-bus-pins { > + samsung,pins = "gpp21-0", "gpp21-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart10_bus_single: uart10-bus-pins { > + samsung,pins = "gpp21-0", "gpp21-1", > + "gpp21-2", "gpp21-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi10_bus: spi10-bus-pins { > + samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi10_cs: spi10-cs-pins { > + samsung,pins = "gpp21-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi10_cs_func: spi10-cs-func-pins { > + samsung,pins = "gpp21-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c9_bus: hsi2c9-bus-pins { > + samsung,pins = "gpp20-4", "gpp20-5"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart9_bus_single: uart9-bus-pins { > + samsung,pins = "gpp20-4", "gpp20-5", > + "gpp20-6", "gpp20-7"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi9_bus: spi9-bus-pins { > + samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi9_cs: spi9-cs-pins { > + samsung,pins = "gpp20-7"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi9_cs_func: spi9-cs-func-pins { > + samsung,pins = "gpp20-7"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c0_bus: hsi2c0-bus-pins { > + samsung,pins = "gpp20-0", "gpp20-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart0_bus_single: uart0-bus-pins { > + samsung,pins = "gpp20-0", "gpp20-1", > + "gpp20-2", "gpp20-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi0_bus: spi0-bus-pins { > + samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi0_cs: spi0-cs-pins { > + samsung,pins = "gpp20-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi0_cs_func: spi0-cs-func-pins { > + samsung,pins = "gpp20-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > +}; > + > diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > new file mode 100644 > index 000000000000..853505e45b60 > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > @@ -0,0 +1,33 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Pinctrl binding constants for GS101 > + * > + * Copyright (c) 2020-2023 Google, LLC. > + */ > + > +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__ > +#define __DT_BINDINGS_PINCTRL_GS101_H__ > + > +#define GS101_PIN_PULL_NONE 0 > +#define GS101_PIN_PULL_DOWN 1 > +#define GS101_PIN_PULL_UP 3 > + > +/* Pin function in power down mode */ > +#define GS101_PIN_PDN_OUT0 0 > +#define GS101_PIN_PDN_OUT1 1 > +#define GS101_PIN_PDN_INPUT 2 > +#define GS101_PIN_PDN_PREV 3 > + > +/* GS101 drive strengths */ > +#define GS101_PIN_DRV_2_5_MA 0 > +#define GS101_PIN_DRV_5_MA 1 > +#define GS101_PIN_DRV_7_5_MA 2 > +#define GS101_PIN_DRV_10_MA 3 > + > +#define GS101_PIN_FUNC_INPUT 0 > +#define GS101_PIN_FUNC_OUTPUT 1 > +#define GS101_PIN_FUNC_2 2 > +#define GS101_PIN_FUNC_3 3 > +#define GS101_PIN_FUNC_EINT 0xf > + > +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */ > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > new file mode 100644 > index 000000000000..40f6654a23f2 > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > @@ -0,0 +1,476 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * GS101 SoC > + * > + * Copyright 2019-2023 Google LLC > + * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> > + */ > + > +#include <dt-bindings/clock/google,gs101.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/soc/samsung,exynos-usi.h> > + > +/ { > + compatible = "google,gs101"; > + #address-cells = <2>; > + #size-cells = <1>; > + > + interrupt-parent = <&gic>; > + > + aliases { > + pinctrl0 = &pinctrl_gpio_alive; > + pinctrl1 = &pinctrl_far_alive; > + pinctrl2 = &pinctrl_gsacore; > + pinctrl3 = &pinctrl_gsactrl; > + pinctrl4 = &pinctrl_peric0; > + pinctrl5 = &pinctrl_peric1; > + pinctrl6 = &pinctrl_hsi1; > + pinctrl7 = &pinctrl_hsi2; > + serial0 = &serial_0; > + }; > + > + pmu-0 { > + compatible = "arm,cortex-a55-pmu"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; > + }; > + > + pmu-1 { > + compatible = "arm,cortex-a76-pmu"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; > + }; > + > + pmu-2 { > + compatible = "arm,cortex-x1-pmu"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>; > + }; > + > + pmu-3 { > + compatible = "arm,dsu-pmu"; > + interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>; > + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, > + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; > + }; > + > + /* TODO replace with CCF clock */ > + dummy_clk: oscillator { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <12345>; > + clock-output-names = "pclk"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + }; > + > + cluster2 { > + core0 { > + cpu = <&cpu6>; > + }; > + core1 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0000>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + > + cpu1: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0100>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + > + cpu2: cpu@200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0200>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + > + cpu3: cpu@300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0300>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + > + cpu4: cpu@400 { > + device_type = "cpu"; > + compatible = "arm,cortex-a76"; > + reg = <0x0400>; > + enable-method = "psci"; > + cpu-idle-states = <&ENYO_CPU_SLEEP>; > + capacity-dmips-mhz = <620>; > + dynamic-power-coefficient = <284>; > + }; > + > + cpu5: cpu@500 { > + device_type = "cpu"; > + compatible = "arm,cortex-a76"; > + reg = <0x0500>; > + enable-method = "psci"; > + cpu-idle-states = <&ENYO_CPU_SLEEP>; > + capacity-dmips-mhz = <620>; > + dynamic-power-coefficient = <284>; > + }; > + > + cpu6: cpu@600 { > + device_type = "cpu"; > + compatible = "arm,cortex-x1"; > + reg = <0x0600>; > + enable-method = "psci"; > + cpu-idle-states = <&HERA_CPU_SLEEP>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <650>; > + }; > + > + cpu7: cpu@700 { > + device_type = "cpu"; > + compatible = "arm,cortex-x1"; > + reg = <0x0700>; > + enable-method = "psci"; > + cpu-idle-states = <&HERA_CPU_SLEEP>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <650>; > + }; > + > + idle-states { > + entry-method = "psci"; > + > + ANANKE_CPU_SLEEP: cpu-ananke-sleep { > + idle-state-name = "c2"; > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010000>; > + entry-latency-us = <70>; > + exit-latency-us = <160>; > + min-residency-us = <2000>; > + }; > + > + ENYO_CPU_SLEEP: cpu-enyo-sleep { > + idle-state-name = "c2"; > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010000>; > + entry-latency-us = <150>; > + exit-latency-us = <190>; > + min-residency-us = <2500>; > + }; > + > + HERA_CPU_SLEEP: cpu-hera-sleep { > + idle-state-name = "c2"; > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010000>; > + entry-latency-us = <235>; > + exit-latency-us = <220>; > + min-residency-us = <3500>; > + }; > + }; > + }; > + > + /* ect node is required to be present by bootloader */ > + ect { > + }; > + > + ext_24_5m: clock-1 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-output-names = "oscclk"; > + }; > + > + ext_200m: clock-2 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-output-names = "ext-200m"; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + > + gsa_reserved_protected: gsa@90200000 { > + reg = <0x0 0x90200000 0x400000>; > + no-map; > + }; > + > + tpu_fw_reserved: tpu-fw@93000000 { > + reg = <0x0 0x93000000 0x1000000>; > + no-map; > + }; > + > + aoc_reserve: aoc@94000000 { > + reg = <0x0 0x94000000 0x03000000>; > + no-map; > + }; > + > + abl_reserved: abl@f8800000 { > + reg = <0x0 0xf8800000 0x02000000>; > + no-map; > + }; > + > + dss_log_reserved: dss-log-reserved@fd3f0000 { > + reg = <0x0 0xfd3f0000 0x0000e000>; > + no-map; > + }; > + > + debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 { > + reg = <0x0 0xfd3fe000 0x00001000>; > + no-map; > + }; > + > + bldr_log_reserved: bldr-log-reserved@fd800000 { > + reg = <0x0 0xfd800000 0x00100000>; > + no-map; > + }; > + > + bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { > + reg = <0x0 0xfd900000 0x00002000>; > + no-map; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = > + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; > + clock-frequency = <24576000>; > + }; > + > + soc: soc@0 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0x0 0x40000000>; > + > + cmu_misc: clock-controller@10010000 { > + compatible = "google,gs101-cmu-misc"; > + reg = <0x10010000 0x8000>; > + #clock-cells = <1>; > + clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>; > + clock-names = "oscclk", "dout_cmu_misc_bus"; > + }; > + > + watchdog_cl0: watchdog@10060000 { > + compatible = "google,gs101-wdt"; > + reg = <0x10060000 0x100>; > + interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = > + <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_IPCLKPORT_PCLK>, > + <&ext_24_5m>; > + clock-names = "watchdog", "watchdog_src"; > + samsung,syscon-phandle = <&pmu_system_controller>; > + samsung,cluster-index = <0>; > + status = "disabled"; > + }; > + > + watchdog_cl1: watchdog@10070000 { > + compatible = "google,gs101-wdt"; > + reg = <0x10070000 0x100>; > + interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = > + <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_IPCLKPORT_PCLK>, > + <&ext_24_5m>; > + clock-names = "watchdog", "watchdog_src"; > + samsung,syscon-phandle = <&pmu_system_controller>; > + samsung,cluster-index = <1>; > + status = "disabled"; > + }; > + > + gic: interrupt-controller@10400000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <4>; > + interrupt-controller; > + reg = <0x10400000 0x10000>, /* GICD */ > + <0x10440000 0x100000>;/* GICR * 8 */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; > + > + ppi-partitions { > + ppi_cluster0: interrupt-partition-0 { > + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; > + }; > + > + ppi_cluster1: interrupt-partition-1 { > + affinity = <&cpu4 &cpu5>; > + }; > + > + ppi_cluster2: interrupt-partition-2 { > + affinity = <&cpu6 &cpu7>; > + }; > + }; > + }; > + > + sysreg_peric0: syscon@10820000 { > + compatible = "google,gs101-peric0-sysreg", "syscon"; > + reg = <0x10820000 0x10000>; > + }; > + > + pinctrl_peric0: pinctrl@10840000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x10840000 0x00001000>; > + interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + usi_uart: usi@10a000c0 { > + compatible = "google,gs101-usi", > + "samsung,exynos850-usi"; > + reg = <0x10a000c0 0x20>; > + samsung,sysreg = <&sysreg_peric0 0x1020>; > + samsung,mode = <USI_V2_UART>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + clocks = <&dummy_clk>, <&dummy_clk>; > + clock-names = "pclk", "ipclk"; > + status = "disabled"; > + > + serial_0: serial@10a00000 { > + compatible = "google,gs101-uart"; > + reg = <0x10a00000 0xc0>; > + reg-io-width = <4>; > + samsung,uart-fifosize = <256>; > + interrupts = <GIC_SPI 634 > + IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&dummy_clk 0>, <&dummy_clk 0>; > + clock-names = "uart", "clk_uart_baud0"; > + status = "disabled"; > + }; > + }; > + > + pinctrl_peric1: pinctrl@10c40000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x10C40000 0x00001000>; > + interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + sysreg_peric1: syscon@10c20000 { > + compatible = "google,gs101-peric1-sysreg", "syscon"; > + reg = <0x10C20000 0x10000>; > + }; > + > + pinctrl_hsi1: pinctrl@11840000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x11840000 0x00001000>; > + interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + pinctrl_hsi2: pinctrl@14440000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x14440000 0x00001000>; > + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + cmu_apm: clock-controller@17400000 { > + compatible = "google,gs101-cmu-apm"; > + reg = <0x17400000 0x8000>; > + #clock-cells = <1>; > + > + clocks = <&ext_24_5m>; > + clock-names = "oscclk"; > + }; > + > + sysreg_apm: syscon@174204e0 { > + compatible = "google,gs101-apm-sysreg", "syscon"; > + reg = <0x174204e0 0x1000>; > + }; > + > + pmu_system_controller: system-controller@17460000 { > + compatible = "google,gs101-pmu", "syscon"; > + reg = <0x17460000 0x10000>; > + }; > + > + pinctrl_gpio_alive: pinctrl@174d0000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x174d0000 0x00001000>; > + > + wakeup-interrupt-controller { > + compatible = "google,gs101-wakeup-eint", > + "samsung,exynos850-wakeup-eint", > + "samsung,exynos7-wakeup-eint"; > + }; > + }; > + > + pinctrl_far_alive: pinctrl@174e0000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x174e0000 0x00001000>; > + > + wakeup-interrupt-controller { > + compatible = "google,gs101-wakeup-eint", > + "samsung,exynos850-wakeup-eint", > + "samsung,exynos7-wakeup-eint"; > + }; > + }; > + > + pinctrl_gsactrl: pinctrl@17940000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x17940000 0x00001000>; > + }; > + > + pinctrl_gsacore: pinctrl@17a80000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x17a80000 0x00001000>; > + }; > + > + cmu_top: clock-controller@1e080000 { > + compatible = "google,gs101-cmu-top"; > + reg = <0x1e080000 0x8000>; > + #clock-cells = <1>; > + > + clocks = <&ext_24_5m>; > + clock-names = "oscclk"; > + }; > + }; > +}; > + > +#include "gs101-pinctrl.dtsi" > -- > 2.43.0.rc2.451.g8631bc7472-goog > > -- > To unsubscribe from this group and stop receiving emails from it, send an email to kernel-team+unsubscribe@android.com. >
On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > Newer Exynos SoCs have a filter selection register on alive bank pins. > This allows the selection of a digital or delay filter for each pin. If > the filter selection register is not available then the default filter > (digital) is applied. > > On suspend we apply the analog filter to all pins in the bank (as the > digital filter relies on a clock). On resume the digital filter is > reapplied to all pins in the bank. The digital filter is working via > clock and has an adjustable filter delay register bitfield, whereas > the analog filter uses a fixed delay. > > The filter determines to what extent signal fluctuations received through > the pad are considered glitches. > > The code path can be exercised using > echo mem > /sys/power/state > And then wake the device using a eint gpio Period. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/pinctrl/samsung/pinctrl-exynos.c | 89 ++++++++++++++++++++++- > drivers/pinctrl/samsung/pinctrl-exynos.h | 7 ++ > drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + > drivers/pinctrl/samsung/pinctrl-samsung.h | 22 ++++++ > 4 files changed, 119 insertions(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c > index 6b58ec84e34b..56fc11a1fe2f 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c > @@ -269,6 +269,71 @@ struct exynos_eint_gpio_save { > u32 eint_mask; > }; > > +/* > + * Set the desired filter (digital or analog delay) to every pin in > + * the bank. Note the filter selection bitfield is only found on alive > + * banks. The filter determines to what extent signal fluctuations > + * received through the pad are considered glitches. > + */ > +static void exynos_eint_flt_config(struct samsung_pinctrl_drv_data *d, > + struct samsung_pin_bank *bank, int filter) > +{ > + unsigned int flt_reg, flt_con = 0; > + unsigned int val, shift; > + int i; > + int loop_cnt; > + > + /* > + * The FLTCON register has the following layout > + * > + * BitfieldName[PinNum][Bit:Bit] > + * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24] > + * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16] > + * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8] > + * FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0] > + * > + * FLT_EN 0x0 = Disable, 0x1=Enable > + * FLT_SEL 0x0 = Delay filter, 0x1 Digital filter > + * FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1 > + */ > + > + flt_con |= EXYNOS9_FLTCON_EN; > + > + if (filter) > + flt_con |= EXYNOS9_FLTCON_DIGITAL; > + > + flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset; > + > + /* > + * If nr_pins > 4, we should set FLTCON0 register fully. > + * (pin0 ~ 3). So loop 4 times in case of FLTCON0. > + */ > + if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN) > + loop_cnt = EXYNOS9_FLTCON_NR_PIN; > + else > + loop_cnt = bank->nr_pins; > + > + val = readl(d->virt_base + flt_reg); > + for (i = 0; i < loop_cnt; i++) { > + shift = i * EXYNOS9_FLTCON_LEN; > + val &= ~(EXYNOS9_FLTCON_MASK << shift); > + val |= (flt_con << shift); > + } > + writel(val, d->virt_base + flt_reg); > + > + /* Loop for FLTCON1 pin 4 ~ 7 */ > + if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN) { > + loop_cnt = (bank->nr_pins - EXYNOS9_FLTCON_NR_PIN); > + val = readl(d->virt_base + flt_reg + 0x4); > + for (i = 0; i < loop_cnt; i++) { > + shift = i * EXYNOS9_FLTCON_LEN; > + val &= ~(EXYNOS9_FLTCON_MASK << shift); > + val |= (flt_con << shift); > + } > + writel(val, d->virt_base + flt_reg + 0x4); > + } > +} > + This whole function needs a refactoring. Do you think below code looks better? 8<----------------------------------------------------------------->8 static void exynos_eint_update_flt_reg(void __iomem *reg, int cnt, int con) { unsigned int val, shift; int i; val = readl(reg); for (i = 0; i < cnt; i++) { shift = i * EXYNOS9_FLTCON_LEN; val &= ~(EXYNOS9_FLTCON_MASK << shift); val |= con << shift; } writel(val, reg); } /* * Set the desired filter (digital or analog delay) to every pin in the bank. * Note the filter selection bitfield is only found on alive banks. The filter * determines to what extent signal fluctuations received through the pad are * considered glitches. * * The FLTCON register has the following layout: * * BitfieldName[PinNum][Bit:Bit] * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24] * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16] * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8] * FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0] * * FLT_EN 0x0 = Disable, 0x1 = Enable * FLT_SEL 0x0 = Delay filter, 0x1 = Digital filter * FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1 */ static void exynos_eint_flt_config(struct samsung_pinctrl_drv_data *d, struct samsung_pin_bank *bank, int filter) { unsigned int off = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset; unsigned int con = EXYNOS9_FLTCON_EN | filter; void __iomem *reg = d->virt_base + off; u8 n = bank->nr_pins; if (bank->fltcon_type == FLT_DEFAULT) return; /* * If nr_pins > 4, we should set FLTCON0 register fully (pin0~3). * So loop 4 times in case of FLTCON0. Loop for FLTCON1 pin4~7. */ if (n <= 4) { exynos_eint_update_flt_reg(reg, n, con); } else { exynos_eint_update_flt_reg(reg, 4, con); exynos_eint_update_flt_reg(reg + 0x4, n - 4, con); } } 8<----------------------------------------------------------------->8 (the code is only to illustrate the idea, I never tested it). > /* > * exynos_eint_gpio_init() - setup handling of external gpio interrupts. > * @d: driver data of samsung pinctrl driver. > @@ -321,6 +386,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) > goto err_domains; > } > > + /* Set Delay Analog Filter */ The code below looks quite self-explanatory to. Maybe remove all comments like this? If you don't think exynos_eint_flt_config() is clear, maybe rename it to exynos_eint_set_filter(). > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(d, bank, > + EXYNOS9_FLTCON_DELAY); It fits the previous line just fine, no need to break the line. Also, if you use the refactored version of exynos_eint_flt_config() I mentioned above, you can drop all 'if' conditions like this. > } > > return 0; > @@ -555,6 +624,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) > if (bank->eint_type != EINT_TYPE_WKUP) > continue; > > + /* Set Digital Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(d, bank, > + EXYNOS9_FLTCON_DIGITAL); Ditto: no need to break the line, remove the comment. If you use the refactored function, you can drop 'if'. > + > bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), > GFP_KERNEL); > if (!bank->irq_chip) { > @@ -658,6 +732,7 @@ static void exynos_pinctrl_suspend_bank( > void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > { > struct samsung_pin_bank *bank = drvdata->pin_banks; > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > struct exynos_irq_chip *irq_chip = NULL; > int i; > > @@ -665,6 +740,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > if (bank->eint_type == EINT_TYPE_GPIO) > exynos_pinctrl_suspend_bank(drvdata, bank); > else if (bank->eint_type == EINT_TYPE_WKUP) { > + /* Setting Delay (Analog) Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(d, bank, > + EXYNOS9_FLTCON_DELAY); Ditto: no need to break the line, remove the comment. If you use the refactored function, you can drop 'if'. > if (!irq_chip) { > irq_chip = bank->irq_chip; > irq_chip->set_eint_wakeup_mask(drvdata, > @@ -707,11 +786,19 @@ static void exynos_pinctrl_resume_bank( > void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) > { > struct samsung_pin_bank *bank = drvdata->pin_banks; > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > int i; > > for (i = 0; i < drvdata->nr_banks; ++i, ++bank) > - if (bank->eint_type == EINT_TYPE_GPIO) > + if (bank->eint_type == EINT_TYPE_GPIO) { > exynos_pinctrl_resume_bank(drvdata, bank); > + } else if (bank->eint_type == EINT_TYPE_WKUP || > + bank->eint_type == EINT_TYPE_WKUP_MUX) { > + /* Set Digital Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(d, bank, > + EXYNOS9_FLTCON_DIGITAL); Ditto: remove the comment, and if you use the refactored function, you can drop 'if'; also there will be no need to break the line. > + } > } > > static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h > index 3ac52c2cf998..e2799ff1b5e9 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos.h > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h > @@ -50,6 +50,13 @@ > > #define EXYNOS_EINT_MAX_PER_BANK 8 > #define EXYNOS_EINT_NR_WKUP_EINT Maybe add an empty line here? > +/* EINT filter configuration */ > +#define EXYNOS9_FLTCON_EN BIT(7) > +#define EXYNOS9_FLTCON_DIGITAL BIT(6) > +#define EXYNOS9_FLTCON_DELAY (0 << 6) > +#define EXYNOS9_FLTCON_MASK 0xff > +#define EXYNOS9_FLTCON_LEN 8 > +#define EXYNOS9_FLTCON_NR_PIN 4 I'd say drop this one and just hard-code it where needed? > > #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ > { \ > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c > index 79babbb39ced..50c360b4753a 100644 > --- a/drivers/pinctrl/samsung/pinctrl-samsung.c > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c > @@ -1105,6 +1105,8 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, > bank->eint_func = bdata->eint_func; > bank->eint_type = bdata->eint_type; > bank->eint_mask = bdata->eint_mask; > + bank->fltcon_type = bdata->fltcon_type; > + bank->fltcon_offset = bdata->fltcon_offset; > bank->eint_offset = bdata->eint_offset; > bank->name = bdata->name; > > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h > index 9b3db50adef3..5fab3885a7d7 100644 > --- a/drivers/pinctrl/samsung/pinctrl-samsung.h > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h > @@ -82,6 +82,20 @@ enum eint_type { > EINT_TYPE_WKUP_MUX, > }; > > +/** > + * enum fltcon_type - filter selection > + * @FLT_DEFAULT: filter not selectable, default digital filter > + * @FLT_SELECT: filter selectable (digital or delay) > + * > + * Some banks on newer Exynos based SoCs have a selectable filter on alive > + * banks of 'analog/delay' or 'digital'. If the filter selection register is > + * not available then the default filter is used (digital). > + */ > +enum fltcon_type { > + FLT_DEFAULT, > + FLT_SELECTABLE, > +}; Is there any benefit of having this enum over replacing it with just a bool field (e.g. 'bool flt_selectable')? > + > /* maximum length of a pin in pin descriptor (example: "gpa0-0") */ > #define PIN_NAME_LENGTH 10 > > @@ -122,6 +136,8 @@ struct samsung_pin_bank_type { > * @eint_type: type of the external interrupt supported by the bank. > * @eint_mask: bit mask of pins which support EINT function. > * @eint_offset: SoC-specific EINT register or interrupt offset of bank. > + * @fltcon_type: whether the filter (delay/digital) is selectable > + * @fltcon_offset: SoC-specific EINT filter control register offset of bank. > * @name: name to be prefixed for each pin in this pin bank. > */ > struct samsung_pin_bank_data { > @@ -133,6 +149,8 @@ struct samsung_pin_bank_data { > enum eint_type eint_type; > u32 eint_mask; > u32 eint_offset; > + enum fltcon_type fltcon_type; > + u32 fltcon_offset; > const char *name; > }; > > @@ -147,6 +165,8 @@ struct samsung_pin_bank_data { > * @eint_type: type of the external interrupt supported by the bank. > * @eint_mask: bit mask of pins which support EINT function. > * @eint_offset: SoC-specific EINT register or interrupt offset of bank. > + * @fltcon_type: whether the filter (delay/digital) is selectable > + * @fltcon_offset: SoC-specific EINT filter control register offset of bank. > * @name: name to be prefixed for each pin in this pin bank. > * @id: id of the bank, propagated to the pin range. > * @pin_base: starting pin number of the bank. > @@ -170,6 +190,8 @@ struct samsung_pin_bank { > enum eint_type eint_type; > u32 eint_mask; > u32 eint_offset; > + enum fltcon_type fltcon_type; > + u32 fltcon_offset; > const char *name; > u32 id; > > -- > 2.43.0.rc2.451.g8631bc7472-goog >
On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > The WDT uses the CPU core signal DBGACK to determine whether the SoC > is running in debug mode or not. If the DBGACK signal is asserted and > DBGACK_MASK bit is enabled, then WDT output and interrupt is masked > (disabled). > > Presence of the DBGACK_MASK bit is determined by adding a new > QUIRK_HAS_DBGACK_BIT quirk. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/watchdog/s3c2410_wdt.c | 27 ++++++++++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > index 0b4bd883ff28..39f3489e41d6 100644 > --- a/drivers/watchdog/s3c2410_wdt.c > +++ b/drivers/watchdog/s3c2410_wdt.c > @@ -34,9 +34,10 @@ > > #define S3C2410_WTCNT_MAXCNT 0xffff > > -#define S3C2410_WTCON_RSTEN (1 << 0) > -#define S3C2410_WTCON_INTEN (1 << 2) > -#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_RSTEN (1 << 0) > +#define S3C2410_WTCON_INTEN (1 << 2) > +#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_DBGACK_MASK (1 << 16) Suggest using BIT() macro. Btw, checkpatch with --strict option suggests it too :) > > #define S3C2410_WTCON_DIV16 (0 << 3) > #define S3C2410_WTCON_DIV32 (1 << 3) > @@ -100,12 +101,17 @@ > * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) > * with "watchdog counter enable" bit. That bit should be set to make watchdog > * counter running. > + * > + * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the > + * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. > + * Debug mode is determined by the DBGACK CPU signal. > */ > #define QUIRK_HAS_WTCLRINT_REG (1 << 0) > #define QUIRK_HAS_PMU_MASK_RESET (1 << 1) > #define QUIRK_HAS_PMU_RST_STAT (1 << 2) > #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) > #define QUIRK_HAS_PMU_CNT_EN (1 << 4) > +#define QUIRK_HAS_DBGACK_BIT (1 << 5) > > /* These quirks require that we have a PMU register map */ > #define QUIRKS_HAVE_PMUREG \ > @@ -375,6 +381,19 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) > return 0; > } > > +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt) > +{ > + unsigned long wtcon; > + > + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)) > + return; > + > + /* disable watchdog outputs if CPU is in debug mode */ Double whitespace in the comment. Also, I'd move this comment up to the function declaration. Other than that: Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > + wtcon = readl(wdt->reg_base + S3C2410_WTCON); > + wtcon |= S3C2410_WTCON_DBGACK_MASK; > + writel(wtcon, wdt->reg_base + S3C2410_WTCON); > +} > + > static int s3c2410wdt_keepalive(struct watchdog_device *wdd) > { > struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); > @@ -700,6 +719,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); > wdt->wdt_device.parent = dev; > > + s3c2410wdt_mask_dbgack(wdt); > + > /* > * If "tmr_atboot" param is non-zero, start the watchdog right now. Also > * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. > -- > 2.43.0.rc2.451.g8631bc7472-goog >
On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > Add serial driver data for Google Tensor gs101 SoC and a common > fifoszdt_serial_drv_data that can be used by platforms that specify the > samsung,uart-fifosize DT property. > > A corresponding dt-bindings patch updates the yaml to ensure > samsung,uart-fifosize is a required property. > > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Reviewed-by: Arnd Bergmann <arnd@arndb.de> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/tty/serial/samsung_tty.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c > index 1b0c2b467a30..f8d98f1006de 100644 > --- a/drivers/tty/serial/samsung_tty.c > +++ b/drivers/tty/serial/samsung_tty.c > @@ -2490,14 +2490,25 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { > .fifosize = { 256, 64, 64, 64 }, > }; > > +/* > + * Common drv_data struct for platforms that specify uart,fifosize in > + * device tree. Isn't it "samsung,uart-fifosize"? Or it was intended this way? Other than this, LGTM (my R-b tag is already present in this patch). > + */ > +static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = { > + EXYNOS_COMMON_SERIAL_DRV_DATA(), > + .fifosize = { 0 }, > +}; > + > #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data) > #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data) > #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data) > +#define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data) > > #else > #define EXYNOS4210_SERIAL_DRV_DATA NULL > #define EXYNOS5433_SERIAL_DRV_DATA NULL > #define EXYNOS850_SERIAL_DRV_DATA NULL > +#define EXYNOS_FIFOSZDT_DRV_DATA NULL > #endif > > #ifdef CONFIG_ARCH_APPLE > @@ -2581,6 +2592,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = { > }, { > .name = "artpec8-uart", > .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, > + }, { > + .name = "gs101-uart", > + .driver_data = (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA, > }, > { }, > }; > @@ -2602,6 +2616,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { > .data = EXYNOS850_SERIAL_DRV_DATA }, > { .compatible = "axis,artpec8-uart", > .data = ARTPEC8_SERIAL_DRV_DATA }, > + { .compatible = "google,gs101-uart", > + .data = EXYNOS_FIFOSZDT_DRV_DATA }, > {}, > }; > MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); > -- > 2.43.0.rc2.451.g8631bc7472-goog >
On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6, > (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile > phones. It features: > * 4xA55 little cluster > * 2xA76 Mid cluster > * 2xX1 Big cluster > > This commit adds the basic device tree for gs101 (SoC). > Further platform support will be added over time. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > .../boot/dts/exynos/google/gs101-pinctrl.dtsi | 1250 +++++++++++++++++ > .../boot/dts/exynos/google/gs101-pinctrl.h | 33 + > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 476 +++++++ > 3 files changed, 1759 insertions(+) > create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi > create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > create mode 100644 arch/arm64/boot/dts/exynos/google/gs101.dtsi > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi > new file mode 100644 > index 000000000000..8c0f0cf75edb > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi > @@ -0,0 +1,1250 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * GS101 SoC pin-mux and pin-config device tree source > + * > + * Copyright 2019-2023 Google LLC > + * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> > + */ > + > +#include "gs101-pinctrl.h" > + > +&pinctrl_gpio_alive { > + gpa0: gpa0-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa1: gpa1-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa2: gpa2-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa3: gpa3-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa4: gpa4-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa5: gpa5-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa9: gpa9-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa10: gpa10-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + uart15_bus: uart15-bus-pins { > + samsung,pins = "gpa2-3", "gpa2-4"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + uart16_bus: uart16-bus-pins { > + samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + uart17_bus: uart17-bus-pins { > + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi15_bus: spi15-bus-pins { > + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi15_cs: spi15-cs-pins { > + samsung,pins = "gpa4-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > +}; > + > +&pinctrl_far_alive { > + gpa6: gpa6-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa7: gpa7-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa8: gpa8-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + gpa11: gpa11-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > +}; > + > +&pinctrl_gsacore { > + gps0: gps0-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gps1: gps1-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gps2: gps2-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > +}; > + > +&pinctrl_gsactrl { > + gps3: gps3-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > +}; > + > +&pinctrl_hsi1 { > + gph0: gph0-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gph1: gph1-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + pcie0_clkreq: pcie0-clkreq-pins{ > + samsung,pins = "gph0-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_UP>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + samsung,pin-pud-pdn = <GS101_PIN_PULL_UP>; > + }; > + > + pcie0_perst: pcie0-perst-pins { > + samsung,pins = "gph0-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + }; > +}; > + > +&pinctrl_hsi2 { > + gph2: gph2-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gph3: gph3-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gph4: gph4-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + sd2_clk: sd2-clk-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_cmd: sd2-cmd-pins { > + samsung,pins = "gph4-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_UP>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_bus1: sd2-bus-width1-pins { > + samsung,pins = "gph4-2"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_UP>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_bus4: sd2-bus-width4-pins { > + samsung,pins = "gph4-3", "gph4-4", "gph4-5"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_UP>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; > + }; > + > + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins { > + samsung,pins = "gph4-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + }; > + > + ufs_rst_n: ufs-rst-n-pins { > + samsung,pins = "gph3-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>; > + }; > + > + ufs_refclk_out: ufs-refclk-out-pins { > + samsung,pins = "gph3-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>; > + }; > + > + pcie1_clkreq: pcie1-clkreq-pins { > + samsung,pins = "gph2-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_UP>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + samsung,pin-pud-pdn = <GS101_PIN_PULL_UP>; > + }; > + > + pcie1_perst: pcie1-perst-pins { > + samsung,pins = "gph2-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + }; > +}; > + > +&pinctrl_peric0 { > + gpp0: gpp0-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp1: gpp1-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp2: gpp2-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp3: gpp3-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp4: gpp4-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp5: gpp5-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp6: gpp6-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp7: gpp7-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp8: gpp8-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp9: gpp9-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp10: gpp10-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp11: gpp11-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp12: gpp12-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp13: gpp13-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp14: gpp14-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp15: gpp15-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp16: gpp16-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp17: gpp17-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp18: gpp18-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp19: gpp19-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + /* USI_PERIC0_UART_DBG */ > + uart0_bus: uart0-bus-pins { > + samsung,pins = "gpp1-2", "gpp1-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + disp_te_pri_on: disp-te-pri-on-pins { > + samsung,pins = "gpp0-3"; > + samsung,pin-function = <GS101_PIN_FUNC_EINT>; > + }; > + > + disp_te_pri_off: disp-te-pri-off-pins { > + samsung,pins = "gpp0-3"; > + samsung,pin-function = <GS101_PIN_FUNC_INPUT>; > + }; > + > + disp_te_sec_on: disp-te-sec-on-pins { > + samsung,pins = "gpp0-4"; > + samsung,pin-function = <GS101_PIN_FUNC_EINT>; > + }; > + > + disp_te_sec_off: disp-te-sec-off-pins { > + samsung,pins = "gpp0-4"; > + samsung,pin-function = <GS101_PIN_FUNC_INPUT>; > + }; > + > + sensor_mclk1_out: sensor-mclk1-out-pins { > + samsung,pins = "gpp3-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk1_fn: sensor-mclk1-fn-pins { > + samsung,pins = "gpp3-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk2_out: sensor-mclk2-out-pins { > + samsung,pins = "gpp5-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk2_fn: sensor-mclk2-fn-pins { > + samsung,pins = "gpp5-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk3_out: sensor-mclk3-out-pins { > + samsung,pins = "gpp7-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk3_fn: sensor-mclk3-fn-pins { > + samsung,pins = "gpp7-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk4_out: sensor-mclk4-out-pins { > + samsung,pins = "gpp9-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk4_fn: sensor-mclk4-fn-pins { > + samsung,pins = "gpp9-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk5_out: sensor-mclk5-out-pins { > + samsung,pins = "gpp11-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk5_fn: sensor-mclk5-fn-pins { > + samsung,pins = "gpp11-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk6_out: sensor-mclk6-out-pins { > + samsung,pins = "gpp13-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk6_fn: sensor-mclk6-fn-pins { > + samsung,pins = "gpp13-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk7_out: sensor-mclk7-out-pins { > + samsung,pins = "gpp15-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk7_fn: sensor-mclk7-fn-pins { > + samsung,pins = "gpp15-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk8_out: sensor-mclk8-out-pins { > + samsung,pins = "gpp17-0"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_DOWN>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + sensor_mclk8_fn: sensor-mclk8-fn-pins { > + samsung,pins = "gpp17-0"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; > + }; > + > + hsi2c14_bus: hsi2c14-bus-pins { > + samsung,pins = "gpp18-0", "gpp18-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart14_bus_single: uart14-bus-pins { > + samsung,pins = "gpp18-0", "gpp18-1", > + "gpp18-2", "gpp18-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi14_bus: spi14-bus-pins { > + samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi14_cs: spi14-cs-pins { > + samsung,pins = "gpp18-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi14_cs_func: spi14-cs-func-pins { > + samsung,pins = "gpp18-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c8_bus: hsi2c8-bus-pins { > + samsung,pins = "gpp16-0", "gpp16-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + samsung,pin-pud-pdn = <GS101_PIN_PDN_OUT0>; > + }; > + > + uart8_bus_single: uart8-bus-pins { > + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2", > + "gpp16-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi8_bus: spi8-bus-pins { > + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi8_cs: spi8-cs-pins { > + samsung,pins = "gpp16-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi8_cs_func: spi8-cs-func-pins { > + samsung,pins = "gpp16-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c7_bus: hsi2c7-bus-pins { > + samsung,pins = "gpp14-0", "gpp14-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart7_bus_single: uart7-bus-pins { > + samsung,pins = "gpp14-0", "gpp14-1", > + "gpp14-2", "gpp14-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi7_bus: spi7-bus-pins { > + samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi7_cs: spi7-cs-pins { > + samsung,pins = "gpp14-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi7_cs_func: spi7-cs-func-pins { > + samsung,pins = "gpp14-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c6_bus: hsi2c6-bus-pins { > + samsung,pins = "gpp12-0", "gpp12-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart6_bus_single: uart6-bus-pins { > + samsung,pins = "gpp12-0", "gpp12-1", > + "gpp12-2", "gpp12-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi6_bus: spi6-bus-pins { > + samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi6_cs: spi6-cs-pins { > + samsung,pins = "gpp12-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi6_cs_func: spi6-cs-func-pins { > + samsung,pins = "gpp12-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c5_bus: hsi2c5-bus-pins { > + samsung,pins = "gpp10-0", "gpp10-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart5_bus_single: uart5-bus-pins { > + samsung,pins = "gpp10-0", "gpp10-1", > + "gpp10-2", "gpp10-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi5_bus: spi5-bus-pins { > + samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2"; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>; > + }; > + > + spi5_cs_func: spi5-cs-func-pins { > + samsung,pins = "gpp10-3"; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>; > + samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>; > + }; > + > + hsi2c4_bus: hsi2c4-bus-pins { > + samsung,pins = "gpp8-0", "gpp8-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart4_bus_single: uart4-bus-pins { > + samsung,pins = "gpp8-0", "gpp8-1", > + "gpp8-2", "gpp8-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi4_bus: spi4-bus-pins { > + samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi4_cs: spi4-cs-pins { > + samsung,pins = "gpp8-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi4_cs_func: spi4-cs-func-pins { > + samsung,pins = "gpp8-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c3_bus: hsi2c3-bus-pins { > + samsung,pins = "gpp6-0", "gpp6-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart3_bus_single: uart3-bus-pins { > + samsung,pins = "gpp6-0", "gpp6-1", > + "gpp6-2", "gpp6-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi3_bus: spi3-bus-pins { > + samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi3_cs: spi3-cs-pins { > + samsung,pins = "gpp6-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi3_cs_func: spi3-cs-func-pins { > + samsung,pins = "gpp6-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c2_bus: hsi2c2-bus-pins { > + samsung,pins = "gpp4-0", "gpp4-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart2_bus_single: uart2-bus-pins { > + samsung,pins = "gpp4-0", "gpp4-1", > + "gpp4-2", "gpp4-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi2_bus: spi2-bus-pins { > + samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi2_cs: spi2-cs-pins { > + samsung,pins = "gpp4-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi2_cs_func: spi2-cs-func-pins { > + samsung,pins = "gpp4-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c1_bus: hsi2c1-bus-pins { > + samsung,pins = "gpp2-0", "gpp2-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart1_bus_single: uart1-bus-pins { > + samsung,pins = "gpp2-0", "gpp2-1", > + "gpp2-2", "gpp2-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi1_bus: spi1-bus-pins { > + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi1_cs: spi1-cs-pins { > + samsung,pins = "gpp2-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi1_cs_func: spi1-cs-func-pins { > + samsung,pins = "gpp2-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > +}; > + > +&pinctrl_peric1 { > + gpp20: gpp20-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp21: gpp21-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp22: gpp22-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp23: gpp23-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp24: gpp24-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp25: gpp25-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp26: gpp26-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpp27: gpp27-gpio-bank { > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + hsi2c13_bus: hsi2c13-bus-pins { > + samsung,pins = "gpp25-0", "gpp25-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart13_bus_single: uart13-bus-pins { > + samsung,pins = "gpp25-0", "gpp25-1", > + "gpp25-2", "gpp25-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi13_bus: spi13-bus-pins { > + samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi13_cs: spi13-cs-pins { > + samsung,pins = "gpp25-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi13_cs_func: spi13-cs-func-pins { > + samsung,pins = "gpp25-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c12_bus: hsi2c12-bus-pins { > + samsung,pins = "gpp23-4", "gpp23-5"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart12_bus_single: uart12-bus-pins { > + samsung,pins = "gpp23-4", "gpp23-5", > + "gpp23-6", "gpp23-7"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi12_bus: spi12-bus-pins { > + samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi14_cs2: spi14-cs2-pins { > + samsung,pins = "gpp23-6"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi12_cs: spi12-cs-pins { > + samsung,pins = "gpp23-7"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi12_cs_func: spi12-cs-func-pins { > + samsung,pins = "gpp23-7"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c11_bus: hsi2c11-bus-pins { > + samsung,pins = "gpp23-0", "gpp23-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart11_bus_single: uart11-bus-pins { > + samsung,pins = "gpp23-0", "gpp23-1", > + "gpp23-2", "gpp23-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi11_bus: spi11-bus-pins { > + samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi11_cs: spi11-cs-pins { > + samsung,pins = "gpp23-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi11_cs_func: spi11-cs-func-pins { > + samsung,pins = "gpp23-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c10_bus: hsi2c10-bus-pins { > + samsung,pins = "gpp21-0", "gpp21-1"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart10_bus_single: uart10-bus-pins { > + samsung,pins = "gpp21-0", "gpp21-1", > + "gpp21-2", "gpp21-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi10_bus: spi10-bus-pins { > + samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi10_cs: spi10-cs-pins { > + samsung,pins = "gpp21-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi10_cs_func: spi10-cs-func-pins { > + samsung,pins = "gpp21-3"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c9_bus: hsi2c9-bus-pins { > + samsung,pins = "gpp20-4", "gpp20-5"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart9_bus_single: uart9-bus-pins { > + samsung,pins = "gpp20-4", "gpp20-5", > + "gpp20-6", "gpp20-7"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi9_bus: spi9-bus-pins { > + samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi9_cs: spi9-cs-pins { > + samsung,pins = "gpp20-7"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi9_cs_func: spi9-cs-func-pins { > + samsung,pins = "gpp20-7"; > + samsung,pin-function = <GS101_PIN_FUNC_2>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + hsi2c0_bus: hsi2c0-bus-pins { > + samsung,pins = "gpp20-0", "gpp20-1"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + uart0_bus_single: uart0-bus-pins { > + samsung,pins = "gpp20-0", "gpp20-1", > + "gpp20-2", "gpp20-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + }; > + > + spi0_bus: spi0-bus-pins { > + samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi0_cs: spi0-cs-pins { > + samsung,pins = "gpp20-3"; > + samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + spi0_cs_func: spi0-cs-func-pins { > + samsung,pins = "gpp20-3"; > + samsung,pin-function = <GS101_PIN_FUNC_3>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > +}; > + Nitpick: this empty line is not needed. > diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > new file mode 100644 > index 000000000000..853505e45b60 > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > @@ -0,0 +1,33 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Pinctrl binding constants for GS101 > + * > + * Copyright (c) 2020-2023 Google, LLC. > + */ > + > +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__ > +#define __DT_BINDINGS_PINCTRL_GS101_H__ > + > +#define GS101_PIN_PULL_NONE 0 > +#define GS101_PIN_PULL_DOWN 1 > +#define GS101_PIN_PULL_UP 3 > + > +/* Pin function in power down mode */ > +#define GS101_PIN_PDN_OUT0 0 > +#define GS101_PIN_PDN_OUT1 1 > +#define GS101_PIN_PDN_INPUT 2 > +#define GS101_PIN_PDN_PREV 3 > + > +/* GS101 drive strengths */ > +#define GS101_PIN_DRV_2_5_MA 0 > +#define GS101_PIN_DRV_5_MA 1 > +#define GS101_PIN_DRV_7_5_MA 2 > +#define GS101_PIN_DRV_10_MA 3 > + > +#define GS101_PIN_FUNC_INPUT 0 > +#define GS101_PIN_FUNC_OUTPUT 1 > +#define GS101_PIN_FUNC_2 2 > +#define GS101_PIN_FUNC_3 3 > +#define GS101_PIN_FUNC_EINT 0xf > + Still feels fishy to me that it was decided to have this file instead of re-using existing Exynos constants. For example, in Exynos850 I used common constants and it was ok, but it's not ok for this SoC, althought they look *identical* in a sense of pinctrl. And all those constants already exist, also identical. So I wonder why something like this shouldn't be done for Exynos850 as well. But ok. > +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */ > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > new file mode 100644 > index 000000000000..40f6654a23f2 > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > @@ -0,0 +1,476 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * GS101 SoC > + * > + * Copyright 2019-2023 Google LLC > + * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> > + */ > + > +#include <dt-bindings/clock/google,gs101.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/soc/samsung,exynos-usi.h> > + > +/ { > + compatible = "google,gs101"; > + #address-cells = <2>; > + #size-cells = <1>; > + > + interrupt-parent = <&gic>; > + > + aliases { > + pinctrl0 = &pinctrl_gpio_alive; > + pinctrl1 = &pinctrl_far_alive; > + pinctrl2 = &pinctrl_gsacore; > + pinctrl3 = &pinctrl_gsactrl; > + pinctrl4 = &pinctrl_peric0; > + pinctrl5 = &pinctrl_peric1; > + pinctrl6 = &pinctrl_hsi1; > + pinctrl7 = &pinctrl_hsi2; > + serial0 = &serial_0; Please check commit f4324583cd4d ("arm64: dts: exynos: move aliases to board in Exynos850"). At least for Exynos850 the serial alias was moved to the board dts by Krzysztof. > + }; > + > + pmu-0 { > + compatible = "arm,cortex-a55-pmu"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; > + }; > + > + pmu-1 { > + compatible = "arm,cortex-a76-pmu"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; > + }; > + > + pmu-2 { > + compatible = "arm,cortex-x1-pmu"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>; > + }; > + > + pmu-3 { > + compatible = "arm,dsu-pmu"; > + interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>; > + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, > + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; > + }; > + > + /* TODO replace with CCF clock */ > + dummy_clk: oscillator { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <12345>; > + clock-output-names = "pclk"; > + }; Don't you already have real USI/UART clocks implemented in your clock driver? > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + }; > + > + cluster2 { > + core0 { > + cpu = <&cpu6>; > + }; > + core1 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0000>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + > + cpu1: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0100>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + > + cpu2: cpu@200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0200>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + > + cpu3: cpu@300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0300>; > + enable-method = "psci"; > + cpu-idle-states = <&ANANKE_CPU_SLEEP>; > + capacity-dmips-mhz = <250>; > + dynamic-power-coefficient = <70>; > + }; > + > + cpu4: cpu@400 { > + device_type = "cpu"; > + compatible = "arm,cortex-a76"; > + reg = <0x0400>; > + enable-method = "psci"; > + cpu-idle-states = <&ENYO_CPU_SLEEP>; > + capacity-dmips-mhz = <620>; > + dynamic-power-coefficient = <284>; > + }; > + > + cpu5: cpu@500 { > + device_type = "cpu"; > + compatible = "arm,cortex-a76"; > + reg = <0x0500>; > + enable-method = "psci"; > + cpu-idle-states = <&ENYO_CPU_SLEEP>; > + capacity-dmips-mhz = <620>; > + dynamic-power-coefficient = <284>; > + }; > + > + cpu6: cpu@600 { > + device_type = "cpu"; > + compatible = "arm,cortex-x1"; > + reg = <0x0600>; > + enable-method = "psci"; > + cpu-idle-states = <&HERA_CPU_SLEEP>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <650>; > + }; > + > + cpu7: cpu@700 { > + device_type = "cpu"; > + compatible = "arm,cortex-x1"; > + reg = <0x0700>; > + enable-method = "psci"; > + cpu-idle-states = <&HERA_CPU_SLEEP>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <650>; > + }; > + > + idle-states { > + entry-method = "psci"; > + > + ANANKE_CPU_SLEEP: cpu-ananke-sleep { > + idle-state-name = "c2"; > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010000>; > + entry-latency-us = <70>; > + exit-latency-us = <160>; > + min-residency-us = <2000>; > + }; > + > + ENYO_CPU_SLEEP: cpu-enyo-sleep { > + idle-state-name = "c2"; > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010000>; > + entry-latency-us = <150>; > + exit-latency-us = <190>; > + min-residency-us = <2500>; > + }; > + > + HERA_CPU_SLEEP: cpu-hera-sleep { > + idle-state-name = "c2"; > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010000>; > + entry-latency-us = <235>; > + exit-latency-us = <220>; > + min-residency-us = <3500>; > + }; > + }; > + }; > + > + /* ect node is required to be present by bootloader */ > + ect { > + }; > + > + ext_24_5m: clock-1 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-output-names = "oscclk"; > + }; > + > + ext_200m: clock-2 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-output-names = "ext-200m"; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + > + gsa_reserved_protected: gsa@90200000 { > + reg = <0x0 0x90200000 0x400000>; > + no-map; > + }; > + > + tpu_fw_reserved: tpu-fw@93000000 { > + reg = <0x0 0x93000000 0x1000000>; > + no-map; > + }; > + > + aoc_reserve: aoc@94000000 { > + reg = <0x0 0x94000000 0x03000000>; > + no-map; > + }; > + > + abl_reserved: abl@f8800000 { > + reg = <0x0 0xf8800000 0x02000000>; > + no-map; > + }; > + > + dss_log_reserved: dss-log-reserved@fd3f0000 { > + reg = <0x0 0xfd3f0000 0x0000e000>; > + no-map; > + }; > + > + debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 { > + reg = <0x0 0xfd3fe000 0x00001000>; > + no-map; > + }; > + > + bldr_log_reserved: bldr-log-reserved@fd800000 { > + reg = <0x0 0xfd800000 0x00100000>; > + no-map; > + }; > + > + bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { > + reg = <0x0 0xfd900000 0x00002000>; > + no-map; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = > + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; > + clock-frequency = <24576000>; > + }; > + > + soc: soc@0 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0x0 0x40000000>; > + > + cmu_misc: clock-controller@10010000 { > + compatible = "google,gs101-cmu-misc"; > + reg = <0x10010000 0x8000>; > + #clock-cells = <1>; > + clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>; > + clock-names = "oscclk", "dout_cmu_misc_bus"; > + }; > + > + watchdog_cl0: watchdog@10060000 { > + compatible = "google,gs101-wdt"; > + reg = <0x10060000 0x100>; > + interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = > + <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_IPCLKPORT_PCLK>, > + <&ext_24_5m>; > + clock-names = "watchdog", "watchdog_src"; > + samsung,syscon-phandle = <&pmu_system_controller>; > + samsung,cluster-index = <0>; > + status = "disabled"; > + }; Krzysztof, can you please advice which scheme is preferred right now: sorting by name or by address? I saw your patch for dts style doc, but just want to know the current state of affairs. > + > + watchdog_cl1: watchdog@10070000 { > + compatible = "google,gs101-wdt"; > + reg = <0x10070000 0x100>; > + interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = > + <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_IPCLKPORT_PCLK>, > + <&ext_24_5m>; > + clock-names = "watchdog", "watchdog_src"; > + samsung,syscon-phandle = <&pmu_system_controller>; > + samsung,cluster-index = <1>; > + status = "disabled"; > + }; > + > + gic: interrupt-controller@10400000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <4>; > + interrupt-controller; > + reg = <0x10400000 0x10000>, /* GICD */ > + <0x10440000 0x100000>;/* GICR * 8 */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; > + > + ppi-partitions { > + ppi_cluster0: interrupt-partition-0 { > + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; > + }; > + > + ppi_cluster1: interrupt-partition-1 { > + affinity = <&cpu4 &cpu5>; > + }; > + > + ppi_cluster2: interrupt-partition-2 { > + affinity = <&cpu6 &cpu7>; > + }; > + }; > + }; > + > + sysreg_peric0: syscon@10820000 { > + compatible = "google,gs101-peric0-sysreg", "syscon"; > + reg = <0x10820000 0x10000>; > + }; > + > + pinctrl_peric0: pinctrl@10840000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x10840000 0x00001000>; > + interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + usi_uart: usi@10a000c0 { > + compatible = "google,gs101-usi", I can't see this compatible in USI driver. Does it make sense to add it there? > + "samsung,exynos850-usi"; > + reg = <0x10a000c0 0x20>; > + samsung,sysreg = <&sysreg_peric0 0x1020>; > + samsung,mode = <USI_V2_UART>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + clocks = <&dummy_clk>, <&dummy_clk>; The same concern as above. I think I saw those clocks already implemented in gs101 clock driver. > + clock-names = "pclk", "ipclk"; > + status = "disabled"; > + > + serial_0: serial@10a00000 { > + compatible = "google,gs101-uart"; > + reg = <0x10a00000 0xc0>; > + reg-io-width = <4>; > + samsung,uart-fifosize = <256>; > + interrupts = <GIC_SPI 634 > + IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&dummy_clk 0>, <&dummy_clk 0>; Ditto. > + clock-names = "uart", "clk_uart_baud0"; > + status = "disabled"; > + }; > + }; > + > + pinctrl_peric1: pinctrl@10c40000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x10C40000 0x00001000>; > + interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + sysreg_peric1: syscon@10c20000 { > + compatible = "google,gs101-peric1-sysreg", "syscon"; > + reg = <0x10C20000 0x10000>; > + }; > + > + pinctrl_hsi1: pinctrl@11840000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x11840000 0x00001000>; > + interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + pinctrl_hsi2: pinctrl@14440000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x14440000 0x00001000>; > + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + > + cmu_apm: clock-controller@17400000 { > + compatible = "google,gs101-cmu-apm"; > + reg = <0x17400000 0x8000>; > + #clock-cells = <1>; > + > + clocks = <&ext_24_5m>; > + clock-names = "oscclk"; Doesn't CMU_APM take any clocks from CMU_TOP? > + }; > + > + sysreg_apm: syscon@174204e0 { > + compatible = "google,gs101-apm-sysreg", "syscon"; > + reg = <0x174204e0 0x1000>; > + }; > + > + pmu_system_controller: system-controller@17460000 { > + compatible = "google,gs101-pmu", "syscon"; > + reg = <0x17460000 0x10000>; > + }; Just a suggestion: it might be relatively simple to add syscon-reboot node in pmu_system_controller, and it might just work. One more feature for free! :) > + > + pinctrl_gpio_alive: pinctrl@174d0000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x174d0000 0x00001000>; > + > + wakeup-interrupt-controller { > + compatible = "google,gs101-wakeup-eint", > + "samsung,exynos850-wakeup-eint", > + "samsung,exynos7-wakeup-eint"; > + }; > + }; > + > + pinctrl_far_alive: pinctrl@174e0000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x174e0000 0x00001000>; > + > + wakeup-interrupt-controller { > + compatible = "google,gs101-wakeup-eint", > + "samsung,exynos850-wakeup-eint", > + "samsung,exynos7-wakeup-eint"; > + }; > + }; > + > + pinctrl_gsactrl: pinctrl@17940000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x17940000 0x00001000>; > + }; > + > + pinctrl_gsacore: pinctrl@17a80000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x17a80000 0x00001000>; > + }; > + > + cmu_top: clock-controller@1e080000 { > + compatible = "google,gs101-cmu-top"; > + reg = <0x1e080000 0x8000>; > + #clock-cells = <1>; > + > + clocks = <&ext_24_5m>; > + clock-names = "oscclk"; > + }; > + }; > +}; > + > +#include "gs101-pinctrl.dtsi" > -- > 2.43.0.rc2.451.g8631bc7472-goog >
Hi Sam, Thanks for the review. On Fri, 1 Dec 2023 at 20:11, Sam Protsenko <semen.protsenko@linaro.org> wrote: > > On Fri, Dec 1, 2023 at 10:10 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > > > Provide dt-schema documentation for Google gs101 SoC clock controller. > > Currently this adds support for cmu_top, cmu_misc and cmu_apm. > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > Except for my nitpicks below (very minor, can be ignored): > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Thanks! If a v6 is required I will fixup these nitpicks as well. > > > .../bindings/clock/google,gs101-clock.yaml | 110 +++++ > > include/dt-bindings/clock/google,gs101.h | 392 ++++++++++++++++++ > > 2 files changed, 502 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml > > create mode 100644 include/dt-bindings/clock/google,gs101.h > > > > diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml > > new file mode 100644 > > index 000000000000..4612886fcc15 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml > > @@ -0,0 +1,110 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Google GS101 SoC clock controller > > + > > +maintainers: > > + - Peter Griffin <peter.griffin@linaro.org> > > + > > +description: | > > + Google GS101 clock controller is comprised of several CMU units, generating > > + clocks for different domains. Those CMU units are modeled as separate device > > + tree nodes, and might depend on each other. The root clock in that clock tree > > + is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate > > + clock in dts. > > + > > + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and > > + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. > > + > > + Each clock is assigned an identifier and client nodes can use this identifier > > + to specify the clock which they consume. All clocks available for usage > > + in clock consumer nodes are defined as preprocessor macros in > > + 'dt-bindings/clock/gs101.h' header. > > + > > +properties: > > + compatible: > > + enum: > > + - google,gs101-cmu-top > > + - google,gs101-cmu-apm > > + - google,gs101-cmu-misc > > + > > + clocks: > > + minItems: 1 > > + maxItems: 2 > > + > > + clock-names: > > + minItems: 1 > > + maxItems: 2 > > + > > + "#clock-cells": > > + const: 1 > > + > > + reg: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - "#clock-cells" > > + - clocks > > + - clock-names > > + - reg > > + > > +allOf: > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - google,gs101-cmu-top > > + - google,gs101-cmu-apm > > + then: > > + properties: > > + clocks: > > + items: > > + - description: External reference clock (24.576 MHz) > > + > > + clock-names: > > + items: > > + - const: oscclk > > + > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: google,gs101-cmu-misc > > + > > + then: > > + properties: > > + clocks: > > + items: > > + - description: External reference clock (24.576 MHz) > > + - description: Misc bus clock (from CMU_TOP) > > + > > + clock-names: > > + items: > > + - const: oscclk > > + - const: dout_cmu_misc_bus > > + > > +additionalProperties: false > > + > > +examples: > > + # Clock controller node for CMU_TOP > > + - | > > + #include <dt-bindings/clock/google,gs101.h> > > Not really needed for the particular example below, but I guess it's > ok to have it here for the reference. > > > + soc { > > + #address-cells = <2>; > > + #size-cells = <1>; > > + > > + cmu_top: clock-controller@1e080000 { > > + compatible = "google,gs101-cmu-top"; > > + reg = <0x0 0x1e080000 0x8000>; > > Having 0x0 here doesn't match how it's done in gs101.dtsi in this > series. If you remove it, then above soc node and its properties can > be removed too. Good spot! Seems I forgot to update the example when switching to address-cells = <1> > > > + #clock-cells = <1>; > > + clocks = <&ext_24_5m>; > > + clock-names = "oscclk"; > > + }; > > + }; > > + > > +... > > diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h > > new file mode 100644 > > index 000000000000..9f280f74578a > > --- /dev/null > > +++ b/include/dt-bindings/clock/google,gs101.h > > @@ -0,0 +1,392 @@ > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > > +/* > > + * Copyright (C) 2023 Linaro Ltd. > > + * Author: Peter Griffin <peter.griffin@linaro.org> > > + * > > + * Device Tree binding constants for Google gs101 clock controller. > > + */ > > + > > +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H > > +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H > > + > > +/* CMU_TOP PLL */ > > +#define CLK_FOUT_SHARED0_PLL 1 > > +#define CLK_FOUT_SHARED1_PLL 2 > > +#define CLK_FOUT_SHARED2_PLL 3 > > +#define CLK_FOUT_SHARED3_PLL 4 > > +#define CLK_FOUT_SPARE_PLL 5 > > + > > +/* CMU_TOP MUX */ > > +#define CLK_MOUT_SHARED0_PLL 6 > > +#define CLK_MOUT_SHARED1_PLL 7 > > +#define CLK_MOUT_SHARED2_PLL 8 > > +#define CLK_MOUT_SHARED3_PLL 9 > > +#define CLK_MOUT_SPARE_PLL 10 > > +#define CLK_MOUT_BO_BUS 11 > > +#define CLK_MOUT_BUS0_BUS 12 > > +#define CLK_MOUT_BUS1_BUS 13 > > +#define CLK_MOUT_BUS2_BUS 14 > > +#define CLK_MOUT_CIS_CLK0 15 > > +#define CLK_MOUT_CIS_CLK1 16 > > +#define CLK_MOUT_CIS_CLK2 17 > > +#define CLK_MOUT_CIS_CLK3 18 > > +#define CLK_MOUT_CIS_CLK4 19 > > +#define CLK_MOUT_CIS_CLK5 20 > > +#define CLK_MOUT_CIS_CLK6 21 > > +#define CLK_MOUT_CIS_CLK7 22 > > +#define CLK_MOUT_CMU_BOOST 23 > > +#define CLK_MOUT_BOOST_OPTION1 24 > > +#define CLK_MOUT_CORE_BUS 25 > > +#define CLK_MOUT_CPUCL0_DBG 26 > > +#define CLK_MOUT_CPUCL0_SWITCH 27 > > +#define CLK_MOUT_CPUCL1_SWITCH 28 > > +#define CLK_MOUT_CPUCL2_SWITCH 29 > > +#define CLK_MOUT_CSIS_BUS 30 > > +#define CLK_MOUT_DISP_BUS 31 > > +#define CLK_MOUT_DNS_BUS 32 > > +#define CLK_MOUT_DPU_BUS 33 > > +#define CLK_MOUT_EH_BUS 34 > > +#define CLK_MOUT_G2D_G2D 35 > > +#define CLK_MOUT_G2D_MSCL 36 > > +#define CLK_MOUT_G3AA_G3AA 37 > > +#define CLK_MOUT_G3D_BUSD 38 > > +#define CLK_MOUT_G3D_GLB 39 > > +#define CLK_MOUT_G3D_SWITCH 40 > > +#define CLK_MOUT_GDC_GDC0 41 > > +#define CLK_MOUT_GDC_GDC1 42 > > +#define CLK_MOUT_GDC_SCSC 43 > > +#define CLK_MOUT_CMU_HPM 44 > > +#define CLK_MOUT_HSI0_BUS 45 > > +#define CLK_MOUT_HSI0_DPGTC 46 > > +#define CLK_MOUT_HSI0_USB31DRD 47 > > +#define CLK_MOUT_HSI0_USBDPDGB 48 > > +#define CLK_MOUT_HSI1_BUS 49 > > +#define CLK_MOUT_HSI1_PCIE 50 > > +#define CLK_MOUT_HSI2_BUS 51 > > +#define CLK_MOUT_HSI2_MMC_CARD 52 > > +#define CLK_MOUT_HSI2_PCIE 53 > > +#define CLK_MOUT_HSI2_UFS_EMBD 54 > > +#define CLK_MOUT_IPP_BUS 55 > > +#define CLK_MOUT_ITP_BUS 56 > > +#define CLK_MOUT_MCSC_ITSC 57 > > +#define CLK_MOUT_MCSC_MCSC 58 > > +#define CLK_MOUT_MFC_MFC 59 > > +#define CLK_MOUT_MIF_BUSP 60 > > +#define CLK_MOUT_MIF_SWITCH 61 > > +#define CLK_MOUT_MISC_BUS 62 > > +#define CLK_MOUT_MISC_SSS 63 > > +#define CLK_MOUT_PDP_BUS 64 > > +#define CLK_MOUT_PDP_VRA 65 > > +#define CLK_MOUT_PERIC0_BUS 66 > > +#define CLK_MOUT_PERIC0_IP 67 > > +#define CLK_MOUT_PERIC1_BUS 68 > > +#define CLK_MOUT_PERIC1_IP 69 > > +#define CLK_MOUT_TNR_BUS 70 > > +#define CLK_MOUT_TOP_BOOST_OPTION1 71 > > +#define CLK_MOUT_TOP_CMUREF 72 > > +#define CLK_MOUT_TPU_BUS 73 > > +#define CLK_MOUT_TPU_TPU 74 > > +#define CLK_MOUT_TPU_TPUCTL 75 > > +#define CLK_MOUT_TPU_UART 76 > > +#define CLK_MOUT_CMU_CMUREF 77 > > + > > +/* CMU_TOP Dividers */ > > +#define CLK_DOUT_BO_BUS 78 > > +#define CLK_DOUT_BUS0_BUS 79 > > +#define CLK_DOUT_BUS1_BUS 80 > > +#define CLK_DOUT_BUS2_BUS 81 > > +#define CLK_DOUT_CIS_CLK0 82 > > +#define CLK_DOUT_CIS_CLK1 83 > > +#define CLK_DOUT_CIS_CLK2 84 > > +#define CLK_DOUT_CIS_CLK3 85 > > +#define CLK_DOUT_CIS_CLK4 86 > > +#define CLK_DOUT_CIS_CLK5 87 > > +#define CLK_DOUT_CIS_CLK6 88 > > +#define CLK_DOUT_CIS_CLK7 89 > > +#define CLK_DOUT_CORE_BUS 90 > > +#define CLK_DOUT_CPUCL0_DBG 91 > > +#define CLK_DOUT_CPUCL0_SWITCH 92 > > +#define CLK_DOUT_CPUCL1_SWITCH 93 > > +#define CLK_DOUT_CPUCL2_SWITCH 94 > > +#define CLK_DOUT_CSIS_BUS 95 > > +#define CLK_DOUT_DISP_BUS 96 > > +#define CLK_DOUT_DNS_BUS 97 > > +#define CLK_DOUT_DPU_BUS 98 > > +#define CLK_DOUT_EH_BUS 99 > > +#define CLK_DOUT_G2D_G2D 100 > > +#define CLK_DOUT_G2D_MSCL 101 > > +#define CLK_DOUT_G3AA_G3AA 102 > > +#define CLK_DOUT_G3D_BUSD 103 > > +#define CLK_DOUT_G3D_GLB 104 > > +#define CLK_DOUT_G3D_SWITCH 105 > > +#define CLK_DOUT_GDC_GDC0 106 > > +#define CLK_DOUT_GDC_GDC1 107 > > +#define CLK_DOUT_GDC_SCSC 108 > > +#define CLK_DOUT_CMU_HPM 109 > > +#define CLK_DOUT_HSI0_BUS 110 > > +#define CLK_DOUT_HSI0_DPGTC 111 > > +#define CLK_DOUT_HSI0_USB31DRD 112 > > +#define CLK_DOUT_HSI0_USBDPDGB 113 > > +#define CLK_DOUT_HSI1_BUS 114 > > +#define CLK_DOUT_HSI1_PCIE 115 > > +#define CLK_DOUT_HSI2_BUS 116 > > +#define CLK_DOUT_HSI2_MMC_CARD 117 > > +#define CLK_DOUT_HSI2_PCIE 118 > > +#define CLK_DOUT_HSI2_UFS_EMBD 119 > > +#define CLK_DOUT_IPP_BUS 107 > > +#define CLK_DOUT_ITP_BUS 108 > > +#define CLK_DOUT_MCSC_ITSC 109 > > +#define CLK_DOUT_MCSC_MCSC 110 > > +#define CLK_DOUT_MFC_MFC 111 > > +#define CLK_DOUT_MIF_BUSP 112 > > +#define CLK_DOUT_MISC_BUS 113 > > +#define CLK_DOUT_MISC_SSS 114 > > +#define CLK_DOUT_PDP_BUS 115 > > +#define CLK_DOUT_PDP_VRA 116 > > +#define CLK_DOUT_PERIC0_BUS 117 > > +#define CLK_DOUT_PERIC0_IP 118 > > +#define CLK_DOUT_PERIC1_BUS 119 > > +#define CLK_DOUT_PERIC1_IP 120 > > +#define CLK_DOUT_TNR_BUS 121 > > +#define CLK_DOUT_TPU_BUS 122 > > +#define CLK_DOUT_TPU_TPU 123 > > +#define CLK_DOUT_TPU_TPUCTL 124 > > +#define CLK_DOUT_TPU_UART 125 > > +#define CLK_DOUT_CMU_BOOST 126 > > +#define CLK_DOUT_CMU_CMUREF 127 > > +#define CLK_DOUT_SHARED0_DIV2 128 > > +#define CLK_DOUT_SHARED0_DIV3 129 > > +#define CLK_DOUT_SHARED0_DIV4 130 > > +#define CLK_DOUT_SHARED0_DIV5 131 > > +#define CLK_DOUT_SHARED1_DIV2 132 > > +#define CLK_DOUT_SHARED1_DIV3 133 > > +#define CLK_DOUT_SHARED1_DIV4 134 > > +#define CLK_DOUT_SHARED2_DIV2 135 > > +#define CLK_DOUT_SHARED3_DIV2 136 > > + > > +/* CMU_TOP Gates */ > > +#define CLK_GOUT_BUS0_BOOST 137 > > +#define CLK_GOUT_BUS1_BOOST 138 > > +#define CLK_GOUT_BUS2_BOOST 139 > > +#define CLK_GOUT_CORE_BOOST 140 > > +#define CLK_GOUT_CPUCL0_BOOST 141 > > +#define CLK_GOUT_CPUCL1_BOOST 142 > > +#define CLK_GOUT_CPUCL2_BOOST 143 > > +#define CLK_GOUT_MIF_BOOST 144 > > +#define CLK_GOUT_MIF_SWITCH 145 > > +#define CLK_GOUT_BO_BUS 146 > > +#define CLK_GOUT_BUS0_BUS 147 > > +#define CLK_GOUT_BUS1_BUS 148 > > +#define CLK_GOUT_BUS2_BUS 149 > > +#define CLK_GOUT_CIS_CLK0 150 > > +#define CLK_GOUT_CIS_CLK1 151 > > +#define CLK_GOUT_CIS_CLK2 152 > > +#define CLK_GOUT_CIS_CLK3 153 > > +#define CLK_GOUT_CIS_CLK4 154 > > +#define CLK_GOUT_CIS_CLK5 155 > > +#define CLK_GOUT_CIS_CLK6 156 > > +#define CLK_GOUT_CIS_CLK7 157 > > +#define CLK_GOUT_CMU_BOOST 158 > > +#define CLK_GOUT_CORE_BUS 159 > > +#define CLK_GOUT_CPUCL0_DBG 160 > > +#define CLK_GOUT_CPUCL0_SWITCH 161 > > +#define CLK_GOUT_CPUCL1_SWITCH 162 > > +#define CLK_GOUT_CPUCL2_SWITCH 163 > > +#define CLK_GOUT_CSIS_BUS 164 > > +#define CLK_GOUT_DISP_BUS 165 > > +#define CLK_GOUT_DNS_BUS 166 > > +#define CLK_GOUT_DPU_BUS 167 > > +#define CLK_GOUT_EH_BUS 168 > > +#define CLK_GOUT_G2D_G2D 169 > > +#define CLK_GOUT_G2D_MSCL 170 > > +#define CLK_GOUT_G3AA_G3AA 171 > > +#define CLK_GOUT_G3D_BUSD 172 > > +#define CLK_GOUT_G3D_GLB 173 > > +#define CLK_GOUT_G3D_SWITCH 174 > > +#define CLK_GOUT_GDC_GDC0 175 > > +#define CLK_GOUT_GDC_GDC1 176 > > +#define CLK_GOUT_GDC_SCSC 177 > > +#define CLK_GOUT_CMU_HPM 178 > > +#define CLK_GOUT_HSI0_BUS 179 > > +#define CLK_GOUT_HSI0_DPGTC 180 > > +#define CLK_GOUT_HSI0_USB31DRD 181 > > +#define CLK_GOUT_HSI0_USBDPDGB 182 > > +#define CLK_GOUT_HSI1_BUS 183 > > +#define CLK_GOUT_HSI1_PCIE 184 > > +#define CLK_GOUT_HSI2_BUS 185 > > +#define CLK_GOUT_HSI2_MMC_CARD 186 > > +#define CLK_GOUT_HSI2_PCIE 187 > > +#define CLK_GOUT_HSI2_UFS_EMBD 188 > > +#define CLK_GOUT_IPP_BUS 189 > > +#define CLK_GOUT_ITP_BUS 190 > > +#define CLK_GOUT_MCSC_ITSC 191 > > +#define CLK_GOUT_MCSC_MCSC 192 > > +#define CLK_GOUT_MFC_MFC 193 > > +#define CLK_GOUT_MIF_BUSP 194 > > +#define CLK_GOUT_MISC_BUS 195 > > +#define CLK_GOUT_MISC_SSS 196 > > +#define CLK_GOUT_PDP_BUS 197 > > +#define CLK_GOUT_PDP_VRA 298 > > +#define CLK_GOUT_G3AA 299 > > +#define CLK_GOUT_PERIC0_BUS 200 > > +#define CLK_GOUT_PERIC0_IP 201 > > +#define CLK_GOUT_PERIC1_BUS 202 > > +#define CLK_GOUT_PERIC1_IP 203 > > +#define CLK_GOUT_TNR_BUS 204 > > +#define CLK_GOUT_TOP_CMUREF 205 > > +#define CLK_GOUT_TPU_BUS 206 > > +#define CLK_GOUT_TPU_TPU 207 > > +#define CLK_GOUT_TPU_TPUCTL 208 > > +#define CLK_GOUT_TPU_UART 209 > > + > > +/* CMU_APM */ > > +#define CLK_MOUT_APM_FUNC 1 > > +#define CLK_MOUT_APM_FUNCSRC 2 > > +#define CLK_DOUT_APM_BOOST 3 > > +#define CLK_DOUT_APM_USI0_UART 4 > > +#define CLK_DOUT_APM_USI0_USI 5 > > +#define CLK_DOUT_APM_USI1_UART 6 > > +#define CLK_GOUT_APM_APM_CMU_APM_IPCLKPORT_PCLK 7 > > +#define CLK_GOUT_BUS0_BOOST_OPTION1 8 > > +#define CLK_GOUT_CMU_BOOST_OPTION1 9 > > +#define CLK_GOUT_CORE_BOOST_OPTION1 10 > > +#define CLK_GOUT_APM_FUNC 11 > > +#define CLK_GOUT_APM_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 12 > > +#define CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 13 > > +#define CLK_GOUT_APM_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 14 > > +#define CLK_GOUT_APM_APBIF_RTC_IPCLKPORT_PCLK 15 > > +#define CLK_GOUT_APM_APBIF_TRTC_IPCLKPORT_PCLK 16 > > +#define CLK_GOUT_APM_APM_USI0_UART_IPCLKPORT_IPCLK 17 > > +#define CLK_GOUT_APM_APM_USI0_UART_IPCLKPORT_PCLK 18 > > +#define CLK_GOUT_APM_APM_USI0_USI_IPCLKPORT_IPCLK 19 > > +#define CLK_GOUT_APM_APM_USI0_USI_IPCLKPORT_PCLK 20 > > +#define CLK_GOUT_APM_APM_USI1_UART_IPCLKPORT_IPCLK 21 > > +#define CLK_GOUT_APM_APM_USI1_UART_IPCLKPORT_PCLK 22 > > +#define CLK_GOUT_APM_D_TZPC_APM_IPCLKPORT_PCLK 23 > > +#define CLK_GOUT_APM_GPC_APM_IPCLKPORT_PCLK 24 > > +#define CLK_GOUT_APM_GREBEINTEGRATION_IPCLKPORT_HCLK 25 > > +#define CLK_GOUT_APM_INTMEM_IPCLKPORT_ACLK 26 > > +#define CLK_GOUT_APM_INTMEM_IPCLKPORT_PCLK 27 > > +#define CLK_GOUT_APM_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 28 > > +#define CLK_GOUT_APM_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 29 > > +#define CLK_GOUT_APM_LHM_AXI_P_APM_IPCLKPORT_I_CLK 30 > > +#define CLK_GOUT_APM_LHS_AXI_D_APM_IPCLKPORT_I_CLK 31 > > +#define CLK_GOUT_APM_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 32 > > +#define CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 33 > > +#define CLK_GOUT_APM_MAILBOX_APM_AOC_IPCLKPORT_PCLK 34 > > +#define CLK_GOUT_APM_MAILBOX_APM_AP_IPCLKPORT_PCLK 35 > > +#define CLK_GOUT_APM_MAILBOX_APM_GSA_IPCLKPORT_PCLK 36 > > +#define CLK_GOUT_APM_MAILBOX_APM_SWD_IPCLKPORT_PCLK 37 > > +#define CLK_GOUT_APM_MAILBOX_APM_TPU_IPCLKPORT_PCLK 38 > > +#define CLK_GOUT_APM_MAILBOX_AP_AOC_IPCLKPORT_PCLK 39 > > +#define CLK_GOUT_APM_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 40 > > This value (40) is not aligned with the rest of values. Will fix > > > +#define CLK_GOUT_APM_PMU_INTR_GEN_IPCLKPORT_PCLK 41 > > +#define CLK_GOUT_APM_ROM_CRC32_HOST_IPCLKPORT_ACLK 42 > > +#define CLK_GOUT_APM_ROM_CRC32_HOST_IPCLKPORT_PCLK 43 > > +#define CLK_GOUT_APM_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 44 > > +#define CLK_GOUT_APM_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 45 > > +#define CLK_GOUT_APM_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 46 > > +#define CLK_GOUT_APM_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 47 > > +#define CLK_GOUT_APM_SPEEDY_APM_IPCLKPORT_PCLK 48 > > +#define CLK_GOUT_APM_SPEEDY_SUB_APM_IPCLKPORT_PCLK 49 > > +#define CLK_GOUT_APM_SSMT_D_APM_IPCLKPORT_ACLK 50 > > +#define CLK_GOUT_APM_SSMT_D_APM_IPCLKPORT_PCLK 51 > > +#define CLK_GOUT_APM_SSMT_G_DBGCORE_IPCLKPORT_ACLK 52 > > +#define CLK_GOUT_APM_SSMT_G_DBGCORE_IPCLKPORT_PCLK 53 > > +#define CLK_GOUT_APM_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 54 > > +#define CLK_GOUT_APM_SYSMMU_D_APM_IPCLKPORT_CLK_S2 55 > > +#define CLK_GOUT_APM_SYSREG_APM_IPCLKPORT_PCLK 56 > > +#define CLK_GOUT_APM_UASC_APM_IPCLKPORT_ACLK 57 > > +#define CLK_GOUT_APM_UASC_APM_IPCLKPORT_PCLK 58 > > +#define CLK_GOUT_APM_UASC_DBGCORE_IPCLKPORT_ACLK 59 > > +#define CLK_GOUT_APM_UASC_DBGCORE_IPCLKPORT_PCLK 60 > > +#define CLK_GOUT_APM_UASC_G_SWD_IPCLKPORT_ACLK 61 > > +#define CLK_GOUT_APM_UASC_G_SWD_IPCLKPORT_PCLK 62 > > +#define CLK_GOUT_APM_UASC_P_AOCAPM_IPCLKPORT_ACLK 63 > > +#define CLK_GOUT_APM_UASC_P_AOCAPM_IPCLKPORT_PCLK 64 > > +#define CLK_GOUT_APM_UASC_P_APM_IPCLKPORT_ACLK 65 > > +#define CLK_GOUT_APM_UASC_P_APM_IPCLKPORT_PCLK 66 > > +#define CLK_GOUT_APM_WDT_APM_IPCLKPORT_PCLK 67 > > +#define CLK_GOUT_APM_XIU_DP_APM_IPCLKPORT_ACLK 68 > > +#define CLK_APM_PLL_DIV2_APM 69 > > +#define CLK_APM_PLL_DIV4_APM 70 > > +#define CLK_APM_PLL_DIV16_APM 71 > > + > > +/* CMU_MISC */ > > + > > This empty line can be removed, for consistency with the rest of > similar comments in this file. Will fix regards, Peter. > > > +#define CLK_MOUT_MISC_BUS_USER 1 > > +#define CLK_MOUT_MISC_SSS_USER 2 > > +#define CLK_MOUT_MISC_GIC 3 > > +#define CLK_DOUT_MISC_BUSP 4 > > +#define CLK_DOUT_MISC_GIC 5 > > +#define CLK_GOUT_MISC_MISC_CMU_MISC_IPCLKPORT_PCLK 6 > > +#define CLK_GOUT_MISC_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 7 > > +#define CLK_GOUT_MISC_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 8 > > +#define CLK_GOUT_MISC_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 9 > > +#define CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 10 > > +#define CLK_GOUT_MISC_ADM_AHB_SSS_IPCLKPORT_HCLKM 11 > > +#define CLK_GOUT_MISC_AD_APB_DIT_IPCLKPORT_PCLKM 12 > > +#define CLK_GOUT_MISC_AD_APB_PUF_IPCLKPORT_PCLKM 13 > > +#define CLK_GOUT_MISC_DIT_IPCLKPORT_ICLKL2A 14 > > +#define CLK_GOUT_MISC_D_TZPC_MISC_IPCLKPORT_PCLK 15 > > +#define CLK_GOUT_MISC_GIC_IPCLKPORT_GICCLK 16 > > +#define CLK_GOUT_MISC_GPC_MISC_IPCLKPORT_PCLK 17 > > +#define CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 18 > > +#define CLK_GOUT_MISC_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 19 > > +#define CLK_GOUT_MISC_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 20 > > +#define CLK_GOUT_MISC_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 21 > > +#define CLK_GOUT_MISC_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 22 > > +#define CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 23 > > +#define CLK_GOUT_MISC_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 24 > > +#define CLK_GOUT_MISC_MCT_IPCLKPORT_PCLK 25 > > +#define CLK_GOUT_MISC_OTP_CON_BIRA_IPCLKPORT_PCLK 26 > > +#define CLK_GOUT_MISC_OTP_CON_BISR_IPCLKPORT_PCLK 27 > > +#define CLK_GOUT_MISC_OTP_CON_TOP_IPCLKPORT_PCLK 28 > > +#define CLK_GOUT_MISC_PDMA_IPCLKPORT_ACLK 29 > > +#define CLK_GOUT_MISC_PPMU_DMA_IPCLKPORT_ACLK 30 > > +#define CLK_GOUT_MISC_PPMU_MISC_IPCLKPORT_ACLK 31 > > +#define CLK_GOUT_MISC_PPMU_MISC_IPCLKPORT_PCLK 32 > > +#define CLK_GOUT_MISC_PUF_IPCLKPORT_I_CLK 33 > > +#define CLK_GOUT_MISC_QE_DIT_IPCLKPORT_ACLK 34 > > +#define CLK_GOUT_MISC_QE_DIT_IPCLKPORT_PCLK 35 > > +#define CLK_GOUT_MISC_QE_PDMA_IPCLKPORT_ACLK 36 > > +#define CLK_GOUT_MISC_QE_PDMA_IPCLKPORT_PCLK 37 > > +#define CLK_GOUT_MISC_QE_PPMU_DMA_IPCLKPORT_ACLK 38 > > +#define CLK_GOUT_MISC_QE_PPMU_DMA_IPCLKPORT_PCLK 39 > > +#define CLK_GOUT_MISC_QE_RTIC_IPCLKPORT_ACLK 40 > > +#define CLK_GOUT_MISC_QE_RTIC_IPCLKPORT_PCLK 41 > > +#define CLK_GOUT_MISC_QE_SPDMA_IPCLKPORT_ACLK 42 > > +#define CLK_GOUT_MISC_QE_SPDMA_IPCLKPORT_PCLK 43 > > +#define CLK_GOUT_MISC_QE_SSS_IPCLKPORT_ACLK 44 > > +#define CLK_GOUT_MISC_QE_SSS_IPCLKPORT_PCLK 45 > > +#define CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 46 > > +#define CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 47 > > +#define CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 48 > > +#define CLK_GOUT_MISC_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 49 > > +#define CLK_GOUT_MISC_RTIC_IPCLKPORT_I_ACLK 50 > > +#define CLK_GOUT_MISC_RTIC_IPCLKPORT_I_PCLK 51 > > +#define CLK_GOUT_MISC_SPDMA_IPCLKPORT_ACLK 52 > > +#define CLK_GOUT_MISC_SSMT_DIT_IPCLKPORT_ACLK 53 > > +#define CLK_GOUT_MISC_SSMT_DIT_IPCLKPORT_PCLK 54 > > +#define CLK_GOUT_MISC_SSMT_PDMA_IPCLKPORT_ACLK 55 > > +#define CLK_GOUT_MISC_SSMT_PDMA_IPCLKPORT_PCLK 56 > > +#define CLK_GOUT_MISC_SSMT_PPMU_DMA_IPCLKPORT_ACLK 57 > > +#define CLK_GOUT_MISC_SSMT_PPMU_DMA_IPCLKPORT_PCLK 58 > > +#define CLK_GOUT_MISC_SSMT_RTIC_IPCLKPORT_ACLK 59 > > +#define CLK_GOUT_MISC_SSMT_RTIC_IPCLKPORT_PCLK 60 > > +#define CLK_GOUT_MISC_SSMT_SPDMA_IPCLKPORT_ACLK 61 > > +#define CLK_GOUT_MISC_SSMT_SPDMA_IPCLKPORT_PCLK 62 > > +#define CLK_GOUT_MISC_SSMT_SSS_IPCLKPORT_ACLK 63 > > +#define CLK_GOUT_MISC_SSMT_SSS_IPCLKPORT_PCLK 64 > > +#define CLK_GOUT_MISC_SSS_IPCLKPORT_I_ACLK 65 > > +#define CLK_GOUT_MISC_SSS_IPCLKPORT_I_PCLK 66 > > +#define CLK_GOUT_MISC_SYSMMU_MISC_IPCLKPORT_CLK_S2 67 > > +#define CLK_GOUT_MISC_SYSMMU_SSS_IPCLKPORT_CLK_S1 68 > > +#define CLK_GOUT_MISC_SYSREG_MISC_IPCLKPORT_PCLK 69 > > +#define CLK_GOUT_MISC_TMU_SUB_IPCLKPORT_PCLK 70 > > +#define CLK_GOUT_MISC_TMU_TOP_IPCLKPORT_PCLK 71 > > +#define CLK_GOUT_MISC_WDT_CLUSTER0_IPCLKPORT_PCLK 72 > > +#define CLK_GOUT_MISC_WDT_CLUSTER1_IPCLKPORT_PCLK 73 > > +#define CLK_GOUT_MISC_XIU_D_MISC_IPCLKPORT_ACLK 74 > > + > > +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ > > -- > > 2.43.0.rc2.451.g8631bc7472-goog > >
On 02/12/2023 02:54, Sam Protsenko wrote: > On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: >> >> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6, >> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile >> phones. It features: >> * 4xA55 little cluster >> * 2xA76 Mid cluster >> * 2xX1 Big cluster >> >> This commit adds the basic device tree for gs101 (SoC). >> Further platform support will be added over time. >> >> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> >> --- ... >> + >> + watchdog_cl0: watchdog@10060000 { >> + compatible = "google,gs101-wdt"; >> + reg = <0x10060000 0x100>; >> + interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>; >> + clocks = >> + <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_IPCLKPORT_PCLK>, >> + <&ext_24_5m>; >> + clock-names = "watchdog", "watchdog_src"; >> + samsung,syscon-phandle = <&pmu_system_controller>; >> + samsung,cluster-index = <0>; >> + status = "disabled"; >> + }; > > Krzysztof, can you please advice which scheme is preferred right now: > sorting by name or by address? I saw your patch for dts style doc, but > just want to know the current state of affairs. Use coding style, so sorting by unit address in DTSI and by label/phandle of overrides in DTS. Coding style was not yet applied, but I don't see any objections to it so it is just a matter of days. Best regards, Krzysztof
Hi Sam, On Fri, 2023-12-01 at 16:40 -0600, Sam Protsenko wrote: > On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > > > [...] > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8 > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0 > > As I understand, all those parts like IPCLKPORT, BLK, UID (RSTNSYNC > probably too) -- they don't really mean anything in the context of the > driver, just noise. And if you remove those -- there won't be any > conflicts with other names, because those bits are not the unique > parts. Following the TRM letter for letter in this case just makes > things extremely long without adding any value IMHO. For example, that > name above might be: > > CLK_CON_GAT_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK > > or even > > CLK_CON_GAT_GOUT_APM_SS_DBGCORE_HCLK > > would be fine. > > In clk-exynos850 driver I removed all those parts, because they make > it pretty much impossible to read both the driver and dts. And yeah, > because those names consequenty lead to very long string names, dts > will be hard to read too, which is even worse. But again, that's only > my IMHO. The advantage of keeping the same name as in the data sheet is that then it's easy to correlate between driver and hardware and future / other hardware. By arbitrarily diverging from the TRM you make life much harder for yourself when you have to look at this again in 12 months time after you've forgotten your name mangling approach; you also make it harder for everybody to review the driver or to use the driver as a reference in the future for other hardware, as nobody except you knows what kind of name-mangling was applied and which register (or clock in this case) is really meant. Cheers, Andre'
Hi Sam, Thanks for your review. On Sat, 2 Dec 2023 at 00:22, Sam Protsenko <semen.protsenko@linaro.org> wrote: > > On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > > > Newer Exynos SoCs have a filter selection register on alive bank pins. > > This allows the selection of a digital or delay filter for each pin. If > > the filter selection register is not available then the default filter > > (digital) is applied. > > > > On suspend we apply the analog filter to all pins in the bank (as the > > digital filter relies on a clock). On resume the digital filter is > > reapplied to all pins in the bank. The digital filter is working via > > clock and has an adjustable filter delay register bitfield, whereas > > the analog filter uses a fixed delay. > > > > The filter determines to what extent signal fluctuations received through > > the pad are considered glitches. > > > > The code path can be exercised using > > echo mem > /sys/power/state > > And then wake the device using a eint gpio > > Period. Will fix > > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > drivers/pinctrl/samsung/pinctrl-exynos.c | 89 ++++++++++++++++++++++- > > drivers/pinctrl/samsung/pinctrl-exynos.h | 7 ++ > > drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + > > drivers/pinctrl/samsung/pinctrl-samsung.h | 22 ++++++ > > 4 files changed, 119 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c > > index 6b58ec84e34b..56fc11a1fe2f 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c > > @@ -269,6 +269,71 @@ struct exynos_eint_gpio_save { > > u32 eint_mask; > > }; > > > > +/* > > + * Set the desired filter (digital or analog delay) to every pin in > > + * the bank. Note the filter selection bitfield is only found on alive > > + * banks. The filter determines to what extent signal fluctuations > > + * received through the pad are considered glitches. > > + */ > > +static void exynos_eint_flt_config(struct samsung_pinctrl_drv_data *d, > > + struct samsung_pin_bank *bank, int filter) > > +{ > > + unsigned int flt_reg, flt_con = 0; > > + unsigned int val, shift; > > + int i; > > + int loop_cnt; > > + > > + /* > > + * The FLTCON register has the following layout > > + * > > + * BitfieldName[PinNum][Bit:Bit] > > + * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24] > > + * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16] > > + * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8] > > + * FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0] > > + * > > + * FLT_EN 0x0 = Disable, 0x1=Enable > > + * FLT_SEL 0x0 = Delay filter, 0x1 Digital filter > > + * FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1 > > + */ > > + > > + flt_con |= EXYNOS9_FLTCON_EN; > > + > > + if (filter) > > + flt_con |= EXYNOS9_FLTCON_DIGITAL; > > + > > + flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset; > > + > > + /* > > + * If nr_pins > 4, we should set FLTCON0 register fully. > > + * (pin0 ~ 3). So loop 4 times in case of FLTCON0. > > + */ > > + if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN) > > + loop_cnt = EXYNOS9_FLTCON_NR_PIN; > > + else > > + loop_cnt = bank->nr_pins; > > + > > + val = readl(d->virt_base + flt_reg); > > + for (i = 0; i < loop_cnt; i++) { > > + shift = i * EXYNOS9_FLTCON_LEN; > > + val &= ~(EXYNOS9_FLTCON_MASK << shift); > > + val |= (flt_con << shift); > > + } > > + writel(val, d->virt_base + flt_reg); > > + > > + /* Loop for FLTCON1 pin 4 ~ 7 */ > > + if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN) { > > + loop_cnt = (bank->nr_pins - EXYNOS9_FLTCON_NR_PIN); > > + val = readl(d->virt_base + flt_reg + 0x4); > > + for (i = 0; i < loop_cnt; i++) { > > + shift = i * EXYNOS9_FLTCON_LEN; > > + val &= ~(EXYNOS9_FLTCON_MASK << shift); > > + val |= (flt_con << shift); > > + } > > + writel(val, d->virt_base + flt_reg + 0x4); > > + } > > +} > > + > > This whole function needs a refactoring. Do you think below code looks better? Yes it does! > > 8<----------------------------------------------------------------->8 > static void exynos_eint_update_flt_reg(void __iomem *reg, int cnt, int con) > { > unsigned int val, shift; > int i; > > val = readl(reg); > for (i = 0; i < cnt; i++) { > shift = i * EXYNOS9_FLTCON_LEN; > val &= ~(EXYNOS9_FLTCON_MASK << shift); > val |= con << shift; > } > writel(val, reg); > } > > /* > * Set the desired filter (digital or analog delay) to every pin in the bank. > * Note the filter selection bitfield is only found on alive banks. The filter > * determines to what extent signal fluctuations received through the pad are > * considered glitches. > * > * The FLTCON register has the following layout: > * > * BitfieldName[PinNum][Bit:Bit] > * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24] > * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16] > * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8] > * FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0] > * > * FLT_EN 0x0 = Disable, 0x1 = Enable > * FLT_SEL 0x0 = Delay filter, 0x1 = Digital filter > * FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1 > */ > static void exynos_eint_flt_config(struct samsung_pinctrl_drv_data *d, > struct samsung_pin_bank *bank, int filter) > { > unsigned int off = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset; > unsigned int con = EXYNOS9_FLTCON_EN | filter; > void __iomem *reg = d->virt_base + off; > u8 n = bank->nr_pins; > > if (bank->fltcon_type == FLT_DEFAULT) > return; > > /* > * If nr_pins > 4, we should set FLTCON0 register fully (pin0~3). > * So loop 4 times in case of FLTCON0. Loop for FLTCON1 pin4~7. > */ > if (n <= 4) { > exynos_eint_update_flt_reg(reg, n, con); > } else { > exynos_eint_update_flt_reg(reg, 4, con); > exynos_eint_update_flt_reg(reg + 0x4, n - 4, con); > } > } > 8<----------------------------------------------------------------->8 > > (the code is only to illustrate the idea, I never tested it). I can refactor it along those lines. > > > /* > > * exynos_eint_gpio_init() - setup handling of external gpio interrupts. > > * @d: driver data of samsung pinctrl driver. > > @@ -321,6 +386,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) > > goto err_domains; > > } > > > > + /* Set Delay Analog Filter */ > > The code below looks quite self-explanatory to. Maybe remove all > comments like this? If you don't think exynos_eint_flt_config() is > clear, maybe rename it to exynos_eint_set_filter(). Ok, I will update the function name to exynos_eint_set_filter() and remove the comments. > > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(d, bank, > > + EXYNOS9_FLTCON_DELAY); > > It fits the previous line just fine, no need to break the line. > > Also, if you use the refactored version of exynos_eint_flt_config() I > mentioned above, you can drop all 'if' conditions like this. Will fix > > > } > > > > return 0; > > @@ -555,6 +624,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) > > if (bank->eint_type != EINT_TYPE_WKUP) > > continue; > > > > + /* Set Digital Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(d, bank, > > + EXYNOS9_FLTCON_DIGITAL); > > Ditto: no need to break the line, remove the comment. If you use the > refactored function, you can drop 'if'. will fix > > > + > > bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), > > GFP_KERNEL); > > if (!bank->irq_chip) { > > @@ -658,6 +732,7 @@ static void exynos_pinctrl_suspend_bank( > > void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > > { > > struct samsung_pin_bank *bank = drvdata->pin_banks; > > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > > struct exynos_irq_chip *irq_chip = NULL; > > int i; > > > > @@ -665,6 +740,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > > if (bank->eint_type == EINT_TYPE_GPIO) > > exynos_pinctrl_suspend_bank(drvdata, bank); > > else if (bank->eint_type == EINT_TYPE_WKUP) { > > + /* Setting Delay (Analog) Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(d, bank, > > + EXYNOS9_FLTCON_DELAY); > > Ditto: no need to break the line, remove the comment. If you use the > refactored function, you can drop 'if'. Will fix > > > if (!irq_chip) { > > irq_chip = bank->irq_chip; > > irq_chip->set_eint_wakeup_mask(drvdata, > > @@ -707,11 +786,19 @@ static void exynos_pinctrl_resume_bank( > > void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) > > { > > struct samsung_pin_bank *bank = drvdata->pin_banks; > > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > > int i; > > > > for (i = 0; i < drvdata->nr_banks; ++i, ++bank) > > - if (bank->eint_type == EINT_TYPE_GPIO) > > + if (bank->eint_type == EINT_TYPE_GPIO) { > > exynos_pinctrl_resume_bank(drvdata, bank); > > + } else if (bank->eint_type == EINT_TYPE_WKUP || > > + bank->eint_type == EINT_TYPE_WKUP_MUX) { > > + /* Set Digital Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(d, bank, > > + EXYNOS9_FLTCON_DIGITAL); > > Ditto: remove the comment, and if you use the refactored function, you > can drop 'if'; also there will be no need to break the line. Will fix > > > + } > > } > > > > static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h > > index 3ac52c2cf998..e2799ff1b5e9 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-exynos.h > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h > > @@ -50,6 +50,13 @@ > > > > #define EXYNOS_EINT_MAX_PER_BANK 8 > > #define EXYNOS_EINT_NR_WKUP_EINT > > Maybe add an empty line here? Will fix > > > +/* EINT filter configuration */ > > +#define EXYNOS9_FLTCON_EN BIT(7) > > +#define EXYNOS9_FLTCON_DIGITAL BIT(6) > > +#define EXYNOS9_FLTCON_DELAY (0 << 6) > > +#define EXYNOS9_FLTCON_MASK 0xff > > +#define EXYNOS9_FLTCON_LEN 8 > > +#define EXYNOS9_FLTCON_NR_PIN 4 > > I'd say drop this one and just hard-code it where needed? Ok, will drop. > > > > > #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ > > { \ > > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c > > index 79babbb39ced..50c360b4753a 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-samsung.c > > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c > > @@ -1105,6 +1105,8 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, > > bank->eint_func = bdata->eint_func; > > bank->eint_type = bdata->eint_type; > > bank->eint_mask = bdata->eint_mask; > > + bank->fltcon_type = bdata->fltcon_type; > > + bank->fltcon_offset = bdata->fltcon_offset; > > bank->eint_offset = bdata->eint_offset; > > bank->name = bdata->name; > > > > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h > > index 9b3db50adef3..5fab3885a7d7 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-samsung.h > > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h > > @@ -82,6 +82,20 @@ enum eint_type { > > EINT_TYPE_WKUP_MUX, > > }; > > > > +/** > > + * enum fltcon_type - filter selection > > + * @FLT_DEFAULT: filter not selectable, default digital filter > > + * @FLT_SELECT: filter selectable (digital or delay) > > + * > > + * Some banks on newer Exynos based SoCs have a selectable filter on alive > > + * banks of 'analog/delay' or 'digital'. If the filter selection register is > > + * not available then the default filter is used (digital). > > + */ > > +enum fltcon_type { > > + FLT_DEFAULT, > > + FLT_SELECTABLE, > > +}; > > Is there any benefit of having this enum over replacing it with just a > bool field (e.g. 'bool flt_selectable')? I thought it made it clearer at the callee sites which filter was being set, but I can update to a bool if that's what you prefer. regards, Peter. > > > + > > /* maximum length of a pin in pin descriptor (example: "gpa0-0") */ > > #define PIN_NAME_LENGTH 10 > > > > @@ -122,6 +136,8 @@ struct samsung_pin_bank_type { > > * @eint_type: type of the external interrupt supported by the bank. > > * @eint_mask: bit mask of pins which support EINT function. > > * @eint_offset: SoC-specific EINT register or interrupt offset of bank. > > + * @fltcon_type: whether the filter (delay/digital) is selectable > > + * @fltcon_offset: SoC-specific EINT filter control register offset of bank. > > * @name: name to be prefixed for each pin in this pin bank. > > */ > > struct samsung_pin_bank_data { > > @@ -133,6 +149,8 @@ struct samsung_pin_bank_data { > > enum eint_type eint_type; > > u32 eint_mask; > > u32 eint_offset; > > + enum fltcon_type fltcon_type; > > + u32 fltcon_offset; > > const char *name; > > }; > > > > @@ -147,6 +165,8 @@ struct samsung_pin_bank_data { > > * @eint_type: type of the external interrupt supported by the bank. > > * @eint_mask: bit mask of pins which support EINT function. > > * @eint_offset: SoC-specific EINT register or interrupt offset of bank. > > + * @fltcon_type: whether the filter (delay/digital) is selectable > > + * @fltcon_offset: SoC-specific EINT filter control register offset of bank. > > * @name: name to be prefixed for each pin in this pin bank. > > * @id: id of the bank, propagated to the pin range. > > * @pin_base: starting pin number of the bank. > > @@ -170,6 +190,8 @@ struct samsung_pin_bank { > > enum eint_type eint_type; > > u32 eint_mask; > > u32 eint_offset; > > + enum fltcon_type fltcon_type; > > + u32 fltcon_offset; > > const char *name; > > u32 id; > > > > -- > > 2.43.0.rc2.451.g8631bc7472-goog > >
Hi Sam, On Tue, 5 Dec 2023 at 11:34, Peter Griffin <peter.griffin@linaro.org> wrote: > > Hi Sam, > > Thanks for your review. > > On Sat, 2 Dec 2023 at 00:22, Sam Protsenko <semen.protsenko@linaro.org> wrote: > > > > On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > > > > > Newer Exynos SoCs have a filter selection register on alive bank pins. > > > This allows the selection of a digital or delay filter for each pin. If > > > the filter selection register is not available then the default filter > > > (digital) is applied. > > > > > > On suspend we apply the analog filter to all pins in the bank (as the > > > digital filter relies on a clock). On resume the digital filter is > > > reapplied to all pins in the bank. The digital filter is working via > > > clock and has an adjustable filter delay register bitfield, whereas > > > the analog filter uses a fixed delay. > > > > > > The filter determines to what extent signal fluctuations received through > > > the pad are considered glitches. > > > > > > The code path can be exercised using > > > echo mem > /sys/power/state > > > And then wake the device using a eint gpio > > > > Period. > > Will fix > > > > > > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > > --- > > > drivers/pinctrl/samsung/pinctrl-exynos.c | 89 ++++++++++++++++++++++- > > > drivers/pinctrl/samsung/pinctrl-exynos.h | 7 ++ > > > drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + > > > drivers/pinctrl/samsung/pinctrl-samsung.h | 22 ++++++ > > > 4 files changed, 119 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c > > > index 6b58ec84e34b..56fc11a1fe2f 100644 > > > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c > > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c > > > @@ -269,6 +269,71 @@ struct exynos_eint_gpio_save { > > > u32 eint_mask; > > > }; > > > > > > +/* > > > + * Set the desired filter (digital or analog delay) to every pin in > > > + * the bank. Note the filter selection bitfield is only found on alive > > > + * banks. The filter determines to what extent signal fluctuations > > > + * received through the pad are considered glitches. > > > + */ > > > +static void exynos_eint_flt_config(struct samsung_pinctrl_drv_data *d, > > > + struct samsung_pin_bank *bank, int filter) > > > +{ > > > + unsigned int flt_reg, flt_con = 0; > > > + unsigned int val, shift; > > > + int i; > > > + int loop_cnt; > > > + > > > + /* > > > + * The FLTCON register has the following layout > > > + * > > > + * BitfieldName[PinNum][Bit:Bit] > > > + * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24] > > > + * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16] > > > + * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8] > > > + * FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0] > > > + * > > > + * FLT_EN 0x0 = Disable, 0x1=Enable > > > + * FLT_SEL 0x0 = Delay filter, 0x1 Digital filter > > > + * FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1 > > > + */ > > > + > > > + flt_con |= EXYNOS9_FLTCON_EN; > > > + > > > + if (filter) > > > + flt_con |= EXYNOS9_FLTCON_DIGITAL; > > > + > > > + flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset; > > > + > > > + /* > > > + * If nr_pins > 4, we should set FLTCON0 register fully. > > > + * (pin0 ~ 3). So loop 4 times in case of FLTCON0. > > > + */ > > > + if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN) > > > + loop_cnt = EXYNOS9_FLTCON_NR_PIN; > > > + else > > > + loop_cnt = bank->nr_pins; > > > + > > > + val = readl(d->virt_base + flt_reg); > > > + for (i = 0; i < loop_cnt; i++) { > > > + shift = i * EXYNOS9_FLTCON_LEN; > > > + val &= ~(EXYNOS9_FLTCON_MASK << shift); > > > + val |= (flt_con << shift); > > > + } > > > + writel(val, d->virt_base + flt_reg); > > > + > > > + /* Loop for FLTCON1 pin 4 ~ 7 */ > > > + if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN) { > > > + loop_cnt = (bank->nr_pins - EXYNOS9_FLTCON_NR_PIN); > > > + val = readl(d->virt_base + flt_reg + 0x4); > > > + for (i = 0; i < loop_cnt; i++) { > > > + shift = i * EXYNOS9_FLTCON_LEN; > > > + val &= ~(EXYNOS9_FLTCON_MASK << shift); > > > + val |= (flt_con << shift); > > > + } > > > + writel(val, d->virt_base + flt_reg + 0x4); > > > + } > > > +} > > > + > > > > This whole function needs a refactoring. Do you think below code looks better? > > Yes it does! > > > > 8<----------------------------------------------------------------->8 > > static void exynos_eint_update_flt_reg(void __iomem *reg, int cnt, int con) > > { > > unsigned int val, shift; > > int i; > > > > val = readl(reg); > > for (i = 0; i < cnt; i++) { > > shift = i * EXYNOS9_FLTCON_LEN; > > val &= ~(EXYNOS9_FLTCON_MASK << shift); > > val |= con << shift; > > } > > writel(val, reg); > > } > > > > /* > > * Set the desired filter (digital or analog delay) to every pin in the bank. > > * Note the filter selection bitfield is only found on alive banks. The filter > > * determines to what extent signal fluctuations received through the pad are > > * considered glitches. > > * > > * The FLTCON register has the following layout: > > * > > * BitfieldName[PinNum][Bit:Bit] > > * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24] > > * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16] > > * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8] > > * FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0] > > * > > * FLT_EN 0x0 = Disable, 0x1 = Enable > > * FLT_SEL 0x0 = Delay filter, 0x1 = Digital filter > > * FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1 > > */ > > static void exynos_eint_flt_config(struct samsung_pinctrl_drv_data *d, > > struct samsung_pin_bank *bank, int filter) > > { > > unsigned int off = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset; > > unsigned int con = EXYNOS9_FLTCON_EN | filter; > > void __iomem *reg = d->virt_base + off; > > u8 n = bank->nr_pins; > > > > if (bank->fltcon_type == FLT_DEFAULT) > > return; > > > > /* > > * If nr_pins > 4, we should set FLTCON0 register fully (pin0~3). > > * So loop 4 times in case of FLTCON0. Loop for FLTCON1 pin4~7. > > */ > > if (n <= 4) { > > exynos_eint_update_flt_reg(reg, n, con); > > } else { > > exynos_eint_update_flt_reg(reg, 4, con); > > exynos_eint_update_flt_reg(reg + 0x4, n - 4, con); > > } > > } > > 8<----------------------------------------------------------------->8 > > > > (the code is only to illustrate the idea, I never tested it). > > I can refactor it along those lines. > > > > > > /* > > > * exynos_eint_gpio_init() - setup handling of external gpio interrupts. > > > * @d: driver data of samsung pinctrl driver. > > > @@ -321,6 +386,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) > > > goto err_domains; > > > } > > > > > > + /* Set Delay Analog Filter */ > > > > The code below looks quite self-explanatory to. Maybe remove all > > comments like this? If you don't think exynos_eint_flt_config() is > > clear, maybe rename it to exynos_eint_set_filter(). > > Ok, I will update the function name to exynos_eint_set_filter() and > remove the comments. > > > > > > + if (bank->fltcon_type != FLT_DEFAULT) > > > + exynos_eint_flt_config(d, bank, > > > + EXYNOS9_FLTCON_DELAY); > > > > It fits the previous line just fine, no need to break the line. > > > > Also, if you use the refactored version of exynos_eint_flt_config() I > > mentioned above, you can drop all 'if' conditions like this. > > Will fix > > > > > > } > > > > > > return 0; > > > @@ -555,6 +624,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) > > > if (bank->eint_type != EINT_TYPE_WKUP) > > > continue; > > > > > > + /* Set Digital Filter */ > > > + if (bank->fltcon_type != FLT_DEFAULT) > > > + exynos_eint_flt_config(d, bank, > > > + EXYNOS9_FLTCON_DIGITAL); > > > > Ditto: no need to break the line, remove the comment. If you use the > > refactored function, you can drop 'if'. > > will fix > > > > > > + > > > bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), > > > GFP_KERNEL); > > > if (!bank->irq_chip) { > > > @@ -658,6 +732,7 @@ static void exynos_pinctrl_suspend_bank( > > > void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > > > { > > > struct samsung_pin_bank *bank = drvdata->pin_banks; > > > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > > > struct exynos_irq_chip *irq_chip = NULL; > > > int i; > > > > > > @@ -665,6 +740,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > > > if (bank->eint_type == EINT_TYPE_GPIO) > > > exynos_pinctrl_suspend_bank(drvdata, bank); > > > else if (bank->eint_type == EINT_TYPE_WKUP) { > > > + /* Setting Delay (Analog) Filter */ > > > + if (bank->fltcon_type != FLT_DEFAULT) > > > + exynos_eint_flt_config(d, bank, > > > + EXYNOS9_FLTCON_DELAY); > > > > Ditto: no need to break the line, remove the comment. If you use the > > refactored function, you can drop 'if'. > > Will fix > > > > > if (!irq_chip) { > > > irq_chip = bank->irq_chip; > > > irq_chip->set_eint_wakeup_mask(drvdata, > > > @@ -707,11 +786,19 @@ static void exynos_pinctrl_resume_bank( > > > void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) > > > { > > > struct samsung_pin_bank *bank = drvdata->pin_banks; > > > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > > > int i; > > > > > > for (i = 0; i < drvdata->nr_banks; ++i, ++bank) > > > - if (bank->eint_type == EINT_TYPE_GPIO) > > > + if (bank->eint_type == EINT_TYPE_GPIO) { > > > exynos_pinctrl_resume_bank(drvdata, bank); > > > + } else if (bank->eint_type == EINT_TYPE_WKUP || > > > + bank->eint_type == EINT_TYPE_WKUP_MUX) { > > > + /* Set Digital Filter */ > > > + if (bank->fltcon_type != FLT_DEFAULT) > > > + exynos_eint_flt_config(d, bank, > > > + EXYNOS9_FLTCON_DIGITAL); > > > > Ditto: remove the comment, and if you use the refactored function, you > > can drop 'if'; also there will be no need to break the line. > > Will fix > > > > > + } > > > } > > > > > > static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) > > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h > > > index 3ac52c2cf998..e2799ff1b5e9 100644 > > > --- a/drivers/pinctrl/samsung/pinctrl-exynos.h > > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h > > > @@ -50,6 +50,13 @@ > > > > > > #define EXYNOS_EINT_MAX_PER_BANK 8 > > > #define EXYNOS_EINT_NR_WKUP_EINT > > > > Maybe add an empty line here? > > Will fix > > > > > +/* EINT filter configuration */ > > > +#define EXYNOS9_FLTCON_EN BIT(7) > > > +#define EXYNOS9_FLTCON_DIGITAL BIT(6) > > > +#define EXYNOS9_FLTCON_DELAY (0 << 6) > > > +#define EXYNOS9_FLTCON_MASK 0xff > > > +#define EXYNOS9_FLTCON_LEN 8 > > > +#define EXYNOS9_FLTCON_NR_PIN 4 > > > > I'd say drop this one and just hard-code it where needed? > > Ok, will drop. > > > > > > > > > #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ > > > { \ > > > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c > > > index 79babbb39ced..50c360b4753a 100644 > > > --- a/drivers/pinctrl/samsung/pinctrl-samsung.c > > > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c > > > @@ -1105,6 +1105,8 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, > > > bank->eint_func = bdata->eint_func; > > > bank->eint_type = bdata->eint_type; > > > bank->eint_mask = bdata->eint_mask; > > > + bank->fltcon_type = bdata->fltcon_type; > > > + bank->fltcon_offset = bdata->fltcon_offset; > > > bank->eint_offset = bdata->eint_offset; > > > bank->name = bdata->name; > > > > > > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h > > > index 9b3db50adef3..5fab3885a7d7 100644 > > > --- a/drivers/pinctrl/samsung/pinctrl-samsung.h > > > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h > > > @@ -82,6 +82,20 @@ enum eint_type { > > > EINT_TYPE_WKUP_MUX, > > > }; > > > > > > +/** > > > + * enum fltcon_type - filter selection > > > + * @FLT_DEFAULT: filter not selectable, default digital filter > > > + * @FLT_SELECT: filter selectable (digital or delay) > > > + * > > > + * Some banks on newer Exynos based SoCs have a selectable filter on alive > > > + * banks of 'analog/delay' or 'digital'. If the filter selection register is > > > + * not available then the default filter is used (digital). > > > + */ > > > +enum fltcon_type { > > > + FLT_DEFAULT, > > > + FLT_SELECTABLE, > > > +}; > > > > Is there any benefit of having this enum over replacing it with just a > > bool field (e.g. 'bool flt_selectable')? > > I thought it made it clearer at the callee sites which filter was > being set, but I can update to a bool if that's what you prefer. Actually that was a previous version. We actually pass EXYNOS9_FLTCON_DELAY and EXYNOS9_FLTCON_DIGITAL now so yes enum is no longer required. Peter > > regards, > > Peter. > > > > > > + > > > /* maximum length of a pin in pin descriptor (example: "gpa0-0") */ > > > #define PIN_NAME_LENGTH 10 > > > > > > @@ -122,6 +136,8 @@ struct samsung_pin_bank_type { > > > * @eint_type: type of the external interrupt supported by the bank. > > > * @eint_mask: bit mask of pins which support EINT function. > > > * @eint_offset: SoC-specific EINT register or interrupt offset of bank. > > > + * @fltcon_type: whether the filter (delay/digital) is selectable > > > + * @fltcon_offset: SoC-specific EINT filter control register offset of bank. > > > * @name: name to be prefixed for each pin in this pin bank. > > > */ > > > struct samsung_pin_bank_data { > > > @@ -133,6 +149,8 @@ struct samsung_pin_bank_data { > > > enum eint_type eint_type; > > > u32 eint_mask; > > > u32 eint_offset; > > > + enum fltcon_type fltcon_type; > > > + u32 fltcon_offset; > > > const char *name; > > > }; > > > > > > @@ -147,6 +165,8 @@ struct samsung_pin_bank_data { > > > * @eint_type: type of the external interrupt supported by the bank. > > > * @eint_mask: bit mask of pins which support EINT function. > > > * @eint_offset: SoC-specific EINT register or interrupt offset of bank. > > > + * @fltcon_type: whether the filter (delay/digital) is selectable > > > + * @fltcon_offset: SoC-specific EINT filter control register offset of bank. > > > * @name: name to be prefixed for each pin in this pin bank. > > > * @id: id of the bank, propagated to the pin range. > > > * @pin_base: starting pin number of the bank. > > > @@ -170,6 +190,8 @@ struct samsung_pin_bank { > > > enum eint_type eint_type; > > > u32 eint_mask; > > > u32 eint_offset; > > > + enum fltcon_type fltcon_type; > > > + u32 fltcon_offset; > > > const char *name; > > > u32 id; > > > > > > -- > > > 2.43.0.rc2.451.g8631bc7472-goog > > >
Hi Will, Thanks for testing! On Fri, 1 Dec 2023 at 23:55, William McVicker <willmcvicker@google.com> wrote: > > On 12/01/2023, Peter Griffin wrote: > > Newer Exynos SoCs have a filter selection register on alive bank pins. > > This allows the selection of a digital or delay filter for each pin. If > > the filter selection register is not available then the default filter > > (digital) is applied. > > > > On suspend we apply the analog filter to all pins in the bank (as the > > digital filter relies on a clock). On resume the digital filter is > > reapplied to all pins in the bank. The digital filter is working via > > clock and has an adjustable filter delay register bitfield, whereas > > the analog filter uses a fixed delay. > > > > The filter determines to what extent signal fluctuations received through > > the pad are considered glitches. > > > > The code path can be exercised using > > echo mem > /sys/power/state > > And then wake the device using a eint gpio > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > Tested-by: Will McVicker <willmcvicker@google.com> > > -- > > I verified boot and that the pinctrl driver is probing. When I tested > > echo mem > /sys/power/state > > I wasn't able to re-wake the device (not sure how to send an eint gpio on > a phone form factor). I tried with no_console_suspend but that hits a SError > Interrupt (likely due to a PMU secure register access). Let me know if there's > anything else I should test out. Yes you're correct that SError is caused by the PMU secure register access. Thanks, Peter. > > Thanks, > Will > > > --- > > drivers/pinctrl/samsung/pinctrl-exynos.c | 89 ++++++++++++++++++++++- > > drivers/pinctrl/samsung/pinctrl-exynos.h | 7 ++ > > drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + > > drivers/pinctrl/samsung/pinctrl-samsung.h | 22 ++++++ > > 4 files changed, 119 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c > > index 6b58ec84e34b..56fc11a1fe2f 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c > > @@ -269,6 +269,71 @@ struct exynos_eint_gpio_save { > > u32 eint_mask; > > }; > > > > +/* > > + * Set the desired filter (digital or analog delay) to every pin in > > + * the bank. Note the filter selection bitfield is only found on alive > > + * banks. The filter determines to what extent signal fluctuations > > + * received through the pad are considered glitches. > > + */ > > +static void exynos_eint_flt_config(struct samsung_pinctrl_drv_data *d, > > + struct samsung_pin_bank *bank, int filter) > > +{ > > + unsigned int flt_reg, flt_con = 0; > > + unsigned int val, shift; > > + int i; > > + int loop_cnt; > > + > > + /* > > + * The FLTCON register has the following layout > > + * > > + * BitfieldName[PinNum][Bit:Bit] > > + * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24] > > + * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16] > > + * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8] > > + * FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0] > > + * > > + * FLT_EN 0x0 = Disable, 0x1=Enable > > + * FLT_SEL 0x0 = Delay filter, 0x1 Digital filter > > + * FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1 > > + */ > > + > > + flt_con |= EXYNOS9_FLTCON_EN; > > + > > + if (filter) > > + flt_con |= EXYNOS9_FLTCON_DIGITAL; > > + > > + flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset; > > + > > + /* > > + * If nr_pins > 4, we should set FLTCON0 register fully. > > + * (pin0 ~ 3). So loop 4 times in case of FLTCON0. > > + */ > > + if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN) > > + loop_cnt = EXYNOS9_FLTCON_NR_PIN; > > + else > > + loop_cnt = bank->nr_pins; > > + > > + val = readl(d->virt_base + flt_reg); > > + for (i = 0; i < loop_cnt; i++) { > > + shift = i * EXYNOS9_FLTCON_LEN; > > + val &= ~(EXYNOS9_FLTCON_MASK << shift); > > + val |= (flt_con << shift); > > + } > > + writel(val, d->virt_base + flt_reg); > > + > > + /* Loop for FLTCON1 pin 4 ~ 7 */ > > + if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN) { > > + loop_cnt = (bank->nr_pins - EXYNOS9_FLTCON_NR_PIN); > > + val = readl(d->virt_base + flt_reg + 0x4); > > + for (i = 0; i < loop_cnt; i++) { > > + shift = i * EXYNOS9_FLTCON_LEN; > > + val &= ~(EXYNOS9_FLTCON_MASK << shift); > > + val |= (flt_con << shift); > > + } > > + writel(val, d->virt_base + flt_reg + 0x4); > > + } > > +} > > + > > /* > > * exynos_eint_gpio_init() - setup handling of external gpio interrupts. > > * @d: driver data of samsung pinctrl driver. > > @@ -321,6 +386,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) > > goto err_domains; > > } > > > > + /* Set Delay Analog Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(d, bank, > > + EXYNOS9_FLTCON_DELAY); > > } > > > > return 0; > > @@ -555,6 +624,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) > > if (bank->eint_type != EINT_TYPE_WKUP) > > continue; > > > > + /* Set Digital Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(d, bank, > > + EXYNOS9_FLTCON_DIGITAL); > > + > > bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), > > GFP_KERNEL); > > if (!bank->irq_chip) { > > @@ -658,6 +732,7 @@ static void exynos_pinctrl_suspend_bank( > > void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > > { > > struct samsung_pin_bank *bank = drvdata->pin_banks; > > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > > struct exynos_irq_chip *irq_chip = NULL; > > int i; > > > > @@ -665,6 +740,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > > if (bank->eint_type == EINT_TYPE_GPIO) > > exynos_pinctrl_suspend_bank(drvdata, bank); > > else if (bank->eint_type == EINT_TYPE_WKUP) { > > + /* Setting Delay (Analog) Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(d, bank, > > + EXYNOS9_FLTCON_DELAY); > > if (!irq_chip) { > > irq_chip = bank->irq_chip; > > irq_chip->set_eint_wakeup_mask(drvdata, > > @@ -707,11 +786,19 @@ static void exynos_pinctrl_resume_bank( > > void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) > > { > > struct samsung_pin_bank *bank = drvdata->pin_banks; > > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > > int i; > > > > for (i = 0; i < drvdata->nr_banks; ++i, ++bank) > > - if (bank->eint_type == EINT_TYPE_GPIO) > > + if (bank->eint_type == EINT_TYPE_GPIO) { > > exynos_pinctrl_resume_bank(drvdata, bank); > > + } else if (bank->eint_type == EINT_TYPE_WKUP || > > + bank->eint_type == EINT_TYPE_WKUP_MUX) { > > + /* Set Digital Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(d, bank, > > + EXYNOS9_FLTCON_DIGITAL); > > + } > > } > > > > static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h > > index 3ac52c2cf998..e2799ff1b5e9 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-exynos.h > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h > > @@ -50,6 +50,13 @@ > > > > #define EXYNOS_EINT_MAX_PER_BANK 8 > > #define EXYNOS_EINT_NR_WKUP_EINT > > +/* EINT filter configuration */ > > +#define EXYNOS9_FLTCON_EN BIT(7) > > +#define EXYNOS9_FLTCON_DIGITAL BIT(6) > > +#define EXYNOS9_FLTCON_DELAY (0 << 6) > > +#define EXYNOS9_FLTCON_MASK 0xff > > +#define EXYNOS9_FLTCON_LEN 8 > > +#define EXYNOS9_FLTCON_NR_PIN 4 > > > > #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ > > { \ > > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c > > index 79babbb39ced..50c360b4753a 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-samsung.c > > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c > > @@ -1105,6 +1105,8 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, > > bank->eint_func = bdata->eint_func; > > bank->eint_type = bdata->eint_type; > > bank->eint_mask = bdata->eint_mask; > > + bank->fltcon_type = bdata->fltcon_type; > > + bank->fltcon_offset = bdata->fltcon_offset; > > bank->eint_offset = bdata->eint_offset; > > bank->name = bdata->name; > > > > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h > > index 9b3db50adef3..5fab3885a7d7 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-samsung.h > > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h > > @@ -82,6 +82,20 @@ enum eint_type { > > EINT_TYPE_WKUP_MUX, > > }; > > > > +/** > > + * enum fltcon_type - filter selection > > + * @FLT_DEFAULT: filter not selectable, default digital filter > > + * @FLT_SELECT: filter selectable (digital or delay) > > + * > > + * Some banks on newer Exynos based SoCs have a selectable filter on alive > > + * banks of 'analog/delay' or 'digital'. If the filter selection register is > > + * not available then the default filter is used (digital). > > + */ > > +enum fltcon_type { > > + FLT_DEFAULT, > > + FLT_SELECTABLE, > > +}; > > + > > /* maximum length of a pin in pin descriptor (example: "gpa0-0") */ > > #define PIN_NAME_LENGTH 10 > > > > @@ -122,6 +136,8 @@ struct samsung_pin_bank_type { > > * @eint_type: type of the external interrupt supported by the bank. > > * @eint_mask: bit mask of pins which support EINT function. > > * @eint_offset: SoC-specific EINT register or interrupt offset of bank. > > + * @fltcon_type: whether the filter (delay/digital) is selectable > > + * @fltcon_offset: SoC-specific EINT filter control register offset of bank. > > * @name: name to be prefixed for each pin in this pin bank. > > */ > > struct samsung_pin_bank_data { > > @@ -133,6 +149,8 @@ struct samsung_pin_bank_data { > > enum eint_type eint_type; > > u32 eint_mask; > > u32 eint_offset; > > + enum fltcon_type fltcon_type; > > + u32 fltcon_offset; > > const char *name; > > }; > > > > @@ -147,6 +165,8 @@ struct samsung_pin_bank_data { > > * @eint_type: type of the external interrupt supported by the bank. > > * @eint_mask: bit mask of pins which support EINT function. > > * @eint_offset: SoC-specific EINT register or interrupt offset of bank. > > + * @fltcon_type: whether the filter (delay/digital) is selectable > > + * @fltcon_offset: SoC-specific EINT filter control register offset of bank. > > * @name: name to be prefixed for each pin in this pin bank. > > * @id: id of the bank, propagated to the pin range. > > * @pin_base: starting pin number of the bank. > > @@ -170,6 +190,8 @@ struct samsung_pin_bank { > > enum eint_type eint_type; > > u32 eint_mask; > > u32 eint_offset; > > + enum fltcon_type fltcon_type; > > + u32 fltcon_offset; > > const char *name; > > u32 id; > > > > -- > > 2.43.0.rc2.451.g8631bc7472-goog > >
Hi Sam, On Sat, 2 Dec 2023 at 00:53, Sam Protsenko <semen.protsenko@linaro.org> wrote: > > On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > > > The WDT uses the CPU core signal DBGACK to determine whether the SoC > > is running in debug mode or not. If the DBGACK signal is asserted and > > DBGACK_MASK bit is enabled, then WDT output and interrupt is masked > > (disabled). > > > > Presence of the DBGACK_MASK bit is determined by adding a new > > QUIRK_HAS_DBGACK_BIT quirk. > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > drivers/watchdog/s3c2410_wdt.c | 27 ++++++++++++++++++++++++--- > > 1 file changed, 24 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > > index 0b4bd883ff28..39f3489e41d6 100644 > > --- a/drivers/watchdog/s3c2410_wdt.c > > +++ b/drivers/watchdog/s3c2410_wdt.c > > @@ -34,9 +34,10 @@ > > > > #define S3C2410_WTCNT_MAXCNT 0xffff > > > > -#define S3C2410_WTCON_RSTEN (1 << 0) > > -#define S3C2410_WTCON_INTEN (1 << 2) > > -#define S3C2410_WTCON_ENABLE (1 << 5) > > +#define S3C2410_WTCON_RSTEN (1 << 0) > > +#define S3C2410_WTCON_INTEN (1 << 2) > > +#define S3C2410_WTCON_ENABLE (1 << 5) > > +#define S3C2410_WTCON_DBGACK_MASK (1 << 16) > > Suggest using BIT() macro. Btw, checkpatch with --strict option > suggests it too :) Yes indeed. I was somewhat reluctant to include changes that had nothing to do with the DBGACK feature but I will update to use the BIT macro in v6. > > > > > #define S3C2410_WTCON_DIV16 (0 << 3) > > #define S3C2410_WTCON_DIV32 (1 << 3) > > @@ -100,12 +101,17 @@ > > * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) > > * with "watchdog counter enable" bit. That bit should be set to make watchdog > > * counter running. > > + * > > + * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the > > + * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. > > + * Debug mode is determined by the DBGACK CPU signal. > > */ > > #define QUIRK_HAS_WTCLRINT_REG (1 << 0) > > #define QUIRK_HAS_PMU_MASK_RESET (1 << 1) > > #define QUIRK_HAS_PMU_RST_STAT (1 << 2) > > #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) > > #define QUIRK_HAS_PMU_CNT_EN (1 << 4) > > +#define QUIRK_HAS_DBGACK_BIT (1 << 5) > > > > /* These quirks require that we have a PMU register map */ > > #define QUIRKS_HAVE_PMUREG \ > > @@ -375,6 +381,19 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) > > return 0; > > } > > > > +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt) > > +{ > > + unsigned long wtcon; > > + > > + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)) > > + return; > > + > > + /* disable watchdog outputs if CPU is in debug mode */ > > Double whitespace in the comment. Also, I'd move this comment up to > the function declaration. Will fix > > Other than that: > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Thanks, Peter > > > + wtcon = readl(wdt->reg_base + S3C2410_WTCON); > > + wtcon |= S3C2410_WTCON_DBGACK_MASK; > > + writel(wtcon, wdt->reg_base + S3C2410_WTCON); > > +} > > + > > static int s3c2410wdt_keepalive(struct watchdog_device *wdd) > > { > > struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); > > @@ -700,6 +719,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > > wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); > > wdt->wdt_device.parent = dev; > > > > + s3c2410wdt_mask_dbgack(wdt); > > + > > /* > > * If "tmr_atboot" param is non-zero, start the watchdog right now. Also > > * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. > > -- > > 2.43.0.rc2.451.g8631bc7472-goog > >
Hi Sam, On Sat, 2 Dec 2023 at 01:09, Sam Protsenko <semen.protsenko@linaro.org> wrote: > > On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > > > Add serial driver data for Google Tensor gs101 SoC and a common > > fifoszdt_serial_drv_data that can be used by platforms that specify the > > samsung,uart-fifosize DT property. > > > > A corresponding dt-bindings patch updates the yaml to ensure > > samsung,uart-fifosize is a required property. > > > > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > > Reviewed-by: Arnd Bergmann <arnd@arndb.de> > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > drivers/tty/serial/samsung_tty.c | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c > > index 1b0c2b467a30..f8d98f1006de 100644 > > --- a/drivers/tty/serial/samsung_tty.c > > +++ b/drivers/tty/serial/samsung_tty.c > > @@ -2490,14 +2490,25 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { > > .fifosize = { 256, 64, 64, 64 }, > > }; > > > > +/* > > + * Common drv_data struct for platforms that specify uart,fifosize in > > + * device tree. > > Isn't it "samsung,uart-fifosize"? Or it was intended this way? The comment should read "samsung,uart-fifosize". Will update. Thanks, Peter. > > Other than this, LGTM (my R-b tag is already present in this patch). > > > + */ > > +static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = { > > + EXYNOS_COMMON_SERIAL_DRV_DATA(), > > + .fifosize = { 0 }, > > +}; > > + > > #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data) > > #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data) > > #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data) > > +#define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data) > > > > #else > > #define EXYNOS4210_SERIAL_DRV_DATA NULL > > #define EXYNOS5433_SERIAL_DRV_DATA NULL > > #define EXYNOS850_SERIAL_DRV_DATA NULL > > +#define EXYNOS_FIFOSZDT_DRV_DATA NULL > > #endif > > > > #ifdef CONFIG_ARCH_APPLE > > @@ -2581,6 +2592,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = { > > }, { > > .name = "artpec8-uart", > > .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, > > + }, { > > + .name = "gs101-uart", > > + .driver_data = (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA, > > }, > > { }, > > }; > > @@ -2602,6 +2616,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { > > .data = EXYNOS850_SERIAL_DRV_DATA }, > > { .compatible = "axis,artpec8-uart", > > .data = ARTPEC8_SERIAL_DRV_DATA }, > > + { .compatible = "google,gs101-uart", > > + .data = EXYNOS_FIFOSZDT_DRV_DATA }, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); > > -- > > 2.43.0.rc2.451.g8631bc7472-goog > >
Hi Will, On Sat, 2 Dec 2023 at 00:01, William McVicker <willmcvicker@google.com> wrote: > > On 12/01/2023, Peter Griffin wrote: > > Add serial driver data for Google Tensor gs101 SoC and a common > > fifoszdt_serial_drv_data that can be used by platforms that specify the > > samsung,uart-fifosize DT property. > > > > A corresponding dt-bindings patch updates the yaml to ensure > > samsung,uart-fifosize is a required property. > > > > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > > Reviewed-by: Arnd Bergmann <arnd@arndb.de> > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > Tested-by: Will McVicker <willmcvicker@google.com> > > --- > > I verified boot to a busybox console with kernel logs printed to the serial > port. Thanks for testing :) I've added your Tested-by tags to the various patches apart from the pinctrl ones that have been refactored a bit. Thanks, Peter. > > Regards, > Will > > > --- > > drivers/tty/serial/samsung_tty.c | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c > > index 1b0c2b467a30..f8d98f1006de 100644 > > --- a/drivers/tty/serial/samsung_tty.c > > +++ b/drivers/tty/serial/samsung_tty.c > > @@ -2490,14 +2490,25 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { > > .fifosize = { 256, 64, 64, 64 }, > > }; > > > > +/* > > + * Common drv_data struct for platforms that specify uart,fifosize in > > + * device tree. > > + */ > > +static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = { > > + EXYNOS_COMMON_SERIAL_DRV_DATA(), > > + .fifosize = { 0 }, > > +}; > > + > > #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data) > > #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data) > > #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data) > > +#define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data) > > > > #else > > #define EXYNOS4210_SERIAL_DRV_DATA NULL > > #define EXYNOS5433_SERIAL_DRV_DATA NULL > > #define EXYNOS850_SERIAL_DRV_DATA NULL > > +#define EXYNOS_FIFOSZDT_DRV_DATA NULL > > #endif > > > > #ifdef CONFIG_ARCH_APPLE > > @@ -2581,6 +2592,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = { > > }, { > > .name = "artpec8-uart", > > .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, > > + }, { > > + .name = "gs101-uart", > > + .driver_data = (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA, > > }, > > { }, > > }; > > @@ -2602,6 +2616,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { > > .data = EXYNOS850_SERIAL_DRV_DATA }, > > { .compatible = "axis,artpec8-uart", > > .data = ARTPEC8_SERIAL_DRV_DATA }, > > + { .compatible = "google,gs101-uart", > > + .data = EXYNOS_FIFOSZDT_DRV_DATA }, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); > > -- > > 2.43.0.rc2.451.g8631bc7472-goog > >
Hi Sam, Thanks for your review. I've trimmed the non relevant parts of the email a bit at Krzysztofs request. On Fri, 1 Dec 2023 at 22:40, Sam Protsenko <semen.protsenko@linaro.org> wrote: > > On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > > > cmu_top is the top level clock management unit which contains PLLs, muxes, > > dividers and gates that feed the other clock management units. > > > > cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the > > APM module. > > > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com> > > Tested-by: Will McVicker <willmcvicker@google.com> > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > drivers/clk/samsung/Makefile | 1 + > > drivers/clk/samsung/clk-gs101.c | 2495 +++++++++++++++++++++++++++++++ > > 2 files changed, 2496 insertions(+) > > create mode 100644 drivers/clk/samsung/clk-gs101.c > > > > diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile > > index ebbeacabe88f..3056944a5a54 100644 > > --- a/drivers/clk/samsung/Makefile > > +++ b/drivers/clk/samsung/Makefile > > @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o > > +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o > > obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o > > obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o > > obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o > > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c > > new file mode 100644 > > index 000000000000..6bd233a7ab63 > > --- /dev/null > > +++ b/drivers/clk/samsung/clk-gs101.c > > @@ -0,0 +1,2495 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > +/* > > + * Copyright (C) 2023 Linaro Ltd. > > + * Author: Peter Griffin <peter.griffin@linaro.org> > > + * > > + * Common Clock Framework support for GS101. > > + */ > > + > > +#include <linux/clk.h> > > +#include <linux/clk-provider.h> > > +#include <linux/of.h> > > +#include <linux/of_device.h> > > +#include <linux/platform_device.h> > > + > > +#include <dt-bindings/clock/google,gs101.h> > > + > > +#include "clk.h" > > +#include "clk-exynos-arm64.h" > > + > > +/* NOTE: Must be equal to the last clock ID increased by one */ > > +#define TOP_NR_CLK (CLK_GOUT_TPU_UART + 1) > > +#define APM_NR_CLK (CLK_APM_PLL_DIV16_APM + 1) > > +#define MISC_NR_CLK (CLK_GOUT_MISC_XIU_D_MISC_IPCLKPORT_ACLK + 1) > > + > > Suggest using CLKS_NR_* naming, to follow other drivers for consistency. Will fix > > > +/* ---- CMU_TOP ------------------------------------------------------------- */ > > + > > +/* Register Offset definitions for CMU_TOP (0x1e080000) */ > > + > > +#define PLL_LOCKTIME_PLL_SHARED0 0x0000 > > +#define PLL_LOCKTIME_PLL_SHARED1 0x0004 > > +#define PLL_LOCKTIME_PLL_SHARED2 0x0008 > > +#define PLL_LOCKTIME_PLL_SHARED3 0x000c <cut> > > + DIV(CLK_DOUT_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc", > > + CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4), > > + DIV(CLK_DOUT_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp", > > + CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4), > > + DIV(CLK_DOUT_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus", > > + CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4), > > + DIV(CLK_DOUT_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss", > > + CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4), > > + /* CLK_CON_DIV_CLKCMU_OTP lower bits reserved*/ > > Why the above clock where bits are reserved is declared, but this one > is not? Also, above comment is marked as TODO, but this one is not. > And there is no space before */. Good spot! These two dividers with reserved lower bits should be fixed factor clocks. I've fixed in v6. > > > + DIV(CLK_DOUT_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus", > > + CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4), > > + DIV(CLK_DOUT_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra", > > + CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4), > > + DIV(CLK_DOUT_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus", > > + CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4), <cut> > > + DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", > > + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), > > + DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", > > + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), > > + DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "mout_shared1_pll", > > + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), > > + DIV(CLK_DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll", > > + CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), > > + DIV(CLK_DOUT_SHARED3_DIV2, "dout_shared3_div2", "mout_shared3_pll", > > + CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1), > > +}; > > + > > +static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = { > > + GATE(CLK_GOUT_BUS0_BOOST, "gout_cmu_bus0_boost", "mout_cmu_boost_option1", > > Please stick to 80 characters length, here and below. Will fix. > > > + CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0), > > + GATE(CLK_GOUT_BUS1_BOOST, "gout_cmu_bus1_boost", "mout_cmu_boost_option1", > > + CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0), > > + GATE(CLK_GOUT_BUS2_BOOST, "gout_cmu_bus2_boost", "mout_cmu_boost_option1", > > + CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0), > > + GATE(CLK_GOUT_CORE_BOOST, "gout_cmu_core_boost", "mout_cmu_boost_option1", > > + CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0), > > +static void __init gs101_cmu_top_init(struct device_node *np) > > +{ > > + exynos_arm64_register_cmu(NULL, np, &top_cmu_info); > > +} > > + > > +/* Register CMU_TOP early, as it's a dependency for other early domains */ > > +CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top", > > + gs101_cmu_top_init); > > + > > +/* ---- CMU_APM ------------------------------------------------------------- */ > > Suggest adding an empty line here. Will fix > > > +/* Register Offset definitions for CMU_APM (0x17400000) */ > > +#define APM_CMU_APM_CONTROLLER_OPTION 0x0800 > > +#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810 > > +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000 > > +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004 > > +#define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800 > > +#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804 > > +#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808 > > +#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c > > +#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000 > > +#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004 > > +#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008 > > +#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c <cut> > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8 > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0 > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4 > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8 > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0 > > As I understand, all those parts like IPCLKPORT, BLK, UID (RSTNSYNC > probably too) -- they don't really mean anything in the context of the > driver, just noise. And if you remove those -- there won't be any > conflicts with other names, because those bits are not the unique > parts. Following the TRM letter for letter in this case just makes > things extremely long without adding any value IMHO. For example, that > name above might be: > > CLK_CON_GAT_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK > > or even > > CLK_CON_GAT_GOUT_APM_SS_DBGCORE_HCLK > > would be fine. > > In clk-exynos850 driver I removed all those parts, because they make > it pretty much impossible to read both the driver and dts. And yeah, > because those names consequenty lead to very long string names, dts > will be hard to read too, which is even worse. But again, that's only > my IMHO. I would like to keep the register names unmodified, as I mentioned previously mangling them makes checking with the datasheet much harder. As the name in the header and string are already mangled a bit I'm OK with mangling that a bit more. With that in mind I've done the following mangling in v6: - Register name: CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK Replace `CLK_CON_GAT_GOUT_BLK_<blockname>_UID_` with `CLK_GOUT_<blockname>_` Replace ` _IPCLKPORT` with nothing Replace `_RSTNSYNC` with nothing So you end up with: GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, "gout_apm_apbif_gpio_alive_pclk", "gout_apm_func", CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 21, 0, 0), That still enables cross referencing with the datasheet via the unmodified register name, but the dt binding define and string are slightly shorter like you wanted. The mangling described above the vast majority of clock names look fine. There are a couple of anomalies though like `CLK_GOUT_MISC_MISC_CMU_MISC_PCLK` and `CLK_GOUT_APM_APM_CMU_APM_PCLK`. I think it is a *really* bad idea to do custom mangling on these specific names though. > > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4 > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0 > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4 > > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8 <cut> > > + GATE(CLK_GOUT_APM_APBIF_RTC_IPCLKPORT_PCLK, > > + "gout_apm_apbif_rtc_ipclkport_pclk", "gout_apm_func", > > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 21, 0, 0), > > + GATE(CLK_GOUT_APM_APBIF_TRTC_IPCLKPORT_PCLK, > > + "gout_apm_apbif_trtc_ipclkport_pclk", "gout_apm_func", > > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 21, 0, 0), > > + GATE(CLK_GOUT_APM_APM_USI0_UART_IPCLKPORT_PCLK, > > + "gout_apm_apm_usi0_uart_ipclkport_pclk", "gout_apm_func", > > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, > > + 21, 0, 0), > > + GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLKPORT_IPCLK, > > + "gout_apm_apm_usi0_usi_ipclkport_ipclk", "dout_apm_usi0_uart", > > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, > > PCLK vs IPCLK? Will fix. The order here should match the register offsets CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, > > > + 21, 0, 0), > > + GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLKPORT_PCLK, > > + "gout_apm_apm_usi0_usi_ipclkport_pclk", "gout_apm_func", > > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, 21, 0, 0), > > Should it be USI0 instead of USI1? It's the same as the definition > below. Also, please stick to 80 characters per line, here and below. I've revisited the 6 clock gates described above to ensure they are in register offset order. > > > + GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLKPORT_IPCLK, > > + "gout_apm_apm_usi1_uart_ipclkport_ipclk", "dout_apm_usi1_uart", > > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, 21, 0, 0), > > + GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLKPORT_PCLK, > > + "gout_apm_apm_usi1_uart_ipclkport_pclk", "gout_apm_func", <cut> > > +static const struct samsung_cmu_info apm_cmu_info __initconst = { > > + .mux_clks = apm_mux_clks, > > + .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), > > + .div_clks = apm_div_clks, > > + .nr_div_clks = ARRAY_SIZE(apm_div_clks), > > + .gate_clks = apm_gate_clks, > > + .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), > > + .fixed_clks = apm_fixed_clks, > > + .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), > > + .nr_clk_ids = APM_NR_CLK, > > + .clk_regs = apm_clk_regs, > > + .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), > > +}; > > + > > +/* ---- CMU_MISC ------------------------------------------------------------- */ > > Suggest adding an empty line here. Will fix > > > +/* Register Offset definitions for CMU_MISC (0x10010000) */ > > +#define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600 > > +#define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604 > > +#define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610 > > +#define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614 > > +#define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800 > > +#define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810 > > +#define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000 > > +#define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800 > > +#define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804 > > Please align all values for this group at the same indentation level. Will fix > > > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000 > > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004 > > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008 > > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c > > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010 > > Just want to give you one more example for my rant above. Look how > much easier it is to understand this name (than above one): > > CLK_CON_GAT_MISC_OSCCLK_CLK > > Which also turns this (public API!): > > "gout_misc_rstnsync_clk_misc_oscclk_ipclkport_clk" > > into this: > > "gout_misc_oscclk_clk" In v6 this becomes GATE(CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK, "gout_misc_clk_misc_oscclk_clk", "dout_misc_busp", CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, 21, 0, 0), <cut> > > > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014 > > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018 > > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c > > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020 > > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024 > > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028 > > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c <cut> > > +static const struct samsung_div_clock misc_div_clks[] __initconst = { > > + DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user", > > + CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3), > > + DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user", > > + CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3), > > +}; > > + > > +static const struct samsung_gate_clock misc_gate_clks[] __initconst = { > > + GATE(CLK_GOUT_MISC_MISC_CMU_MISC_IPCLKPORT_PCLK, > > + "gout_misc_ipclkport_pclk", "dout_misc_busp", > > So if you want to be consistent, it should be > "gout_misc_misc_misc_....". My point is -- Samsung's naming in TRM is > insane. They wanted to stick to some very detailed and unified naming > schema (or just generated those names from some internal clock tree > data), granted. But I'm just not sure if it's the best idea to follow > it in driver's code. With the naming described above it becomes "gout_misc_misc_cmu_misc_pclk". Not ideal, and this is one of the clocks I mentioned above. The overwhelming majority of the clock names don't have such repetition in their name though. If we start doing custom mangling on specific clocks it is going to become a nightmare to track. As I mentioned previously there are thousands of clocks in the SoC. Most upstream platforms only seem to implement a small subset of clocks in each CMU which maybe makes it easier to track. Our goal though is to have full functionality upstream. > > > + CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, > > + 21, 0, 0), > > + GATE(CLK_GOUT_MISC_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, > > + "gout_misc_otp_con_bira_ipclkport_i_oscclk", "dout_misc_busp", > > + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, > > + 21, 0, 0), > > + GATE(CLK_GOUT_MISC_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, > > + "gout_misc_otp_con_bisr_ipclkport_i_oscclk", "dout_misc_busp", > > + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, > > + 21, 0, 0), <snip> > > + GATE(CLK_GOUT_MISC_RTIC_IPCLKPORT_I_ACLK, > > + "gout_misc_rtic_ipclkport_i_aclk", "dout_misc_busp", > > + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, > > + 21, 0, 0), > > + GATE(CLK_GOUT_MISC_RTIC_IPCLKPORT_I_PCLK, "gout_misc_rtic_ipclkport_i_pclk", > > 80 characters per line please. Will fix regards, Peter
Hi Sam, On Sat, 2 Dec 2023 at 01:54, Sam Protsenko <semen.protsenko@linaro.org> wrote: > > On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > > > Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6, > > (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile > > phones. It features: > > * 4xA55 little cluster > > * 2xA76 Mid cluster > > * 2xX1 Big cluster > > > > This commit adds the basic device tree for gs101 (SoC). > > Further platform support will be added over time. [cut] > > + spi0_cs_func: spi0-cs-func-pins { > > + samsung,pins = "gpp20-3"; > > + samsung,pin-function = <GS101_PIN_FUNC_3>; > > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > > + }; > > +}; > > + > > Nitpick: this empty line is not needed. Ok will fix [cut] > > + > > + aliases { > > + pinctrl0 = &pinctrl_gpio_alive; > > + pinctrl1 = &pinctrl_far_alive; > > + pinctrl2 = &pinctrl_gsacore; > > + pinctrl3 = &pinctrl_gsactrl; > > + pinctrl4 = &pinctrl_peric0; > > + pinctrl5 = &pinctrl_peric1; > > + pinctrl6 = &pinctrl_hsi1; > > + pinctrl7 = &pinctrl_hsi2; > > + serial0 = &serial_0; > > Please check commit f4324583cd4d ("arm64: dts: exynos: move aliases to > board in Exynos850"). At least for Exynos850 the serial alias was > moved to the board dts by Krzysztof. Ok will fix > > > + }; > > + > > + pmu-0 { > > + compatible = "arm,cortex-a55-pmu"; > > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; > > + }; > > + > > + pmu-1 { > > + compatible = "arm,cortex-a76-pmu"; > > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; > > + }; > > + > > + pmu-2 { > > + compatible = "arm,cortex-x1-pmu"; > > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>; > > + }; > > + > > + pmu-3 { > > + compatible = "arm,dsu-pmu"; > > + interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>; > > + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, > > + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; > > + }; > > + > > + /* TODO replace with CCF clock */ > > + dummy_clk: oscillator { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <12345>; > > + clock-output-names = "pclk"; > > + }; > > Don't you already have real USI/UART clocks implemented in your clock driver? No, not yet, hence the dummy clock. [cut] > > + > > + usi_uart: usi@10a000c0 { > > + compatible = "google,gs101-usi", > > I can't see this compatible in USI driver. Does it make sense to add it there? It is not required at the moment, as it is compatible with samsung,exynos850-usi. I don't want to keep adding more patches to this series, and then having an endless cycle of nits. > > > + "samsung,exynos850-usi"; > > + reg = <0x10a000c0 0x20>; > > + samsung,sysreg = <&sysreg_peric0 0x1020>; > > + samsung,mode = <USI_V2_UART>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > + clocks = <&dummy_clk>, <&dummy_clk>; > > The same concern as above. I think I saw those clocks already > implemented in gs101 clock driver. No, these clocks have not been implemented yet, hence the dummy clock. There is no support for cmu_peric0 bank yet in the clock driver. > > > + clock-names = "pclk", "ipclk"; > > + status = "disabled"; > > + > > + serial_0: serial@10a00000 { > > + compatible = "google,gs101-uart"; > > + reg = <0x10a00000 0xc0>; > > + reg-io-width = <4>; > > + samsung,uart-fifosize = <256>; > > + interrupts = <GIC_SPI 634 > > + IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = <&dummy_clk 0>, <&dummy_clk 0>; > > Ditto. See above > > > + clock-names = "uart", "clk_uart_baud0"; > > + status = "disabled"; > > + }; > > + }; > > + > > + pinctrl_peric1: pinctrl@10c40000 { > > + compatible = "google,gs101-pinctrl"; > > + reg = <0x10C40000 0x00001000>; > > + interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; > > + }; > > + > > + sysreg_peric1: syscon@10c20000 { > > + compatible = "google,gs101-peric1-sysreg", "syscon"; > > + reg = <0x10C20000 0x10000>; > > + }; > > + > > + pinctrl_hsi1: pinctrl@11840000 { > > + compatible = "google,gs101-pinctrl"; > > + reg = <0x11840000 0x00001000>; > > + interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; > > + }; > > + > > + pinctrl_hsi2: pinctrl@14440000 { > > + compatible = "google,gs101-pinctrl"; > > + reg = <0x14440000 0x00001000>; > > + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; > > + }; > > + > > + cmu_apm: clock-controller@17400000 { > > + compatible = "google,gs101-cmu-apm"; > > + reg = <0x17400000 0x8000>; > > + #clock-cells = <1>; > > + > > + clocks = <&ext_24_5m>; > > + clock-names = "oscclk"; > > Doesn't CMU_APM take any clocks from CMU_TOP? No it doesn't. > > > + }; > > + > > + sysreg_apm: syscon@174204e0 { > > + compatible = "google,gs101-apm-sysreg", "syscon"; > > + reg = <0x174204e0 0x1000>; > > + }; > > + > > + pmu_system_controller: system-controller@17460000 { > > + compatible = "google,gs101-pmu", "syscon"; > > + reg = <0x17460000 0x10000>; > > + }; > > Just a suggestion: it might be relatively simple to add syscon-reboot > node in pmu_system_controller, and it might just work. One more > feature for free! :) Thanks for the suggestion. I tried that previously and it is not included here deliberately because it relies on more than that to be functional. Although the register offsets are the same, the PMU registers are protected from the kernel and are only write accessible via SMC call on this platform. I have patches ready to send out as a RFC for that once this initial series is merged and we can discuss that then. regards, Peter.
Hi folks, Thanks to everyone who reviewed the previous rounds. V5 incorporates the review feedback received so far, and is rebased onto linux-next as per Krzysztof request to incorporate all his dt-binding changes for exynos. As this series spans multiple subsytems the expectation is that Krzysztof will apply the whole series through the Samsung SoC tree. If the relevant subsystem maintainers can give a acked-by or reviewed-by on the relevant patches that would be most appreciated! This series adds initial SoC support for the GS101 SoC and also initial board support for Pixel 6 phone (Oriole). The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven) phones. Currently DT is added for the gs101 SoC and Oriole. As you can see from the patches the SoC is based on a Samsung Exynos SoC, and therefore lots of the low level Exynos drivers can be re-used. The support added in this series consists of: * cpus * pinctrl * CCF implementation of cmu_top, cmu_misc & cmu_apm * watchdog * USI uart * gpio This is enough to boot through to a busybox initramfs and shell using an upstream kernel though :) More platform support will be added over the following weeks and months. For further information on how to build and flash the upstream kernel on your Pixel 6, with a prebuilt busybox initramfs please refer to the script and README.md here: https://git.codelinaro.org/linaro/googlelt/pixelscripts Note: Booting without a dtbo works with some versions of the bootloader but crashes on others. Later versions aren't necessarily better. You can get the bootloader version with `fastboot getvar version-bootloader` Known good bootloader versions are: - - slider-1.3-11000330 - slider-1.2-9152140 Known to crash without dtbo - slider-1.3-10780582 kind regards, Peter. lore v4: https://lore.kernel.org/linux-arm-kernel/20231120212037.911774-1-peter.griffin@linaro.org/T/ pw v3: https://patchwork.kernel.org/project/linux-samsung-soc/cover/20231011184823.443959-1-peter.griffin@linaro.org/ lore v2: https://lore.kernel.org/all/20231010224928.2296997-1-peter.griffin@linaro.org/ lore v1: https://lore.kernel.org/linux-arm-kernel/20231005155618.700312-1-peter.griffin@linaro.org/ Changes since v4: - clk-gs101: order cmu_top by register address, fix incorrect mux widths, add missing mux/div/gates (Andre) - google,gs101.h: add missing space in comment (Andre) - ckl-gs101:google,gs101.h add all remaining gates for cmu_misc and cmu_apm - update pmu dt labels (Krzysztof) - Remove uart16 rts/tx gpio definitions (Krzysztof) - Fixup various dts cosmetic nits (using consts, alignments, names) (Sam/Krzysztof) - Add more specific compatibles for arm cpu's and pmu (Sam) - Use address-cells 1 and ranges property for SoC addresses (Sam) - Encapsulate uart node in USI node (Sam) - Remove earlycon from bootargs - s3c2410_wdt: Reword QUIRK_HAS_DBGACK_BIT docs and add comment (Guenter) - s3c2410_wdt: Reorder DBGACK_MASK functionality first, gs101 SoC second (Sam/Krzysztof) Changes since v3: - Add reviewed-by and tested-by tags - google,gs101-clock.yaml: move Required to before Allof, enum for cmu*top/misc (Krzysztof) - samsung-wdt.yaml: stick to 80chars (Sam) - google.yaml - remove new line - samsung,pinctrl-wakeup-interrupt: sort alphabetically (RobH) - gs101-oriole.dts: update gpio-keys pinctrl-0 phandle for keys (Stephen) - samsung,exynos-sysreg.yaml - Alphabetical order (RobH) - pinctrl-exynos: update/move comments, slight cosmetic changes (Sam) - samsung_tty.c: update to generic drv_data name/macro (Arnd) - samsung_uart.yaml: make samsung,uart-fifosize required for gs101-uart (Arnd) - pinctrl-exynos: Remove eint irqs from alive pin controller node (Peter/Rob) - Fixup kernel test robot unused const variable warnings - clk-gs101: Update to mout_cmu_eh_bus to CLK_CON_MUX_MUX_CLKCMU_EH_BUS (Chanwoo) - clk-gs101: Update g3aa gout/dout/mout names to g3aa_g3aa for consistency (Chanwoo) - Remove .eint_gpio_init() cb on alive, alive_far, gsacore & gsactrl banks (Sam) - s3c2410_wdt: Drop windowed watchdog mode for now (Peter) - s3c2410_wdt: Separate gs101 SoC support from dbgack feature (Sam) - Move dts to arch/arm64/boot/dts/exynos/google directory (Krzysztof) Changes since v2: - Fixup pinctrl@174d0000: interrupts: [..] is too long DTC warning (Tudor) - Add missing windowed watchdog code (Guenter) - Fixup UART YAML bindings error (Krzysztof) - gs101.dtsi add missing serial_0 alias (me) - samsung_tty.c: fixup gs101_serial_drv_data so fifosize is obtained from DT Changes since v1: - Remove irq/gs101.h and replace macros with irq numbers globally - exynos-pmu - keep alphabetical order - add cmu_apm to clock bindings documentation - sysreg bindings - remove superfluous `google,gs101-sysreg` - watchdog bindings - Alphanumerical order, update gs201 comment - samsung,pinctrl.yaml - add new "if:then:else:" to narrow for google SoC - samsung,pinctrl-wakeup-interrupt.yaml - Alphanumerical order - samsung,pinctrl- add google,gs101-wakeup-eint compatible - clk-pll: fixup typos - clk-gs101: fix kernel test robot warnings (add 2 new clocks,dividers,gate) - clk-gs101: fix alphabetical order - clk-gs101: cmu_apm: fixup typo and missing empty entry - clk-gs101: cmu_misc: remove clocks that were being registered twice - pinctrl: filter sel: rename/reorder variables, add comment for FLTCON bitfield - pinctrl: filter sel: avoid setting reserved bits by loop over FLTCON1 pins as well - pinctrl: gs101: rename bank_type_6/7 structs to be more specific, split from filter - watchdog: s3c2410_wdt: remove dev_info prints - gs101.dtsi/oriole.dts: order by unit node, remove underscores from node name, blank lines add SoC node, split dts and dtsi into separate patches, remove 'DVT' suffix - gs101-oriole.dtso: Remove overlay until board_id is documented properly - Add GS101_PIN_* macros to gs101-pinctrl.h instead of using Exynos ones - gpio-keys: update linux,code to use input-event-code macros - add dedicated gs101-uart compatible Peter Griffin (19): dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible dt-bindings: clock: Add Google gs101 clock management unit bindings dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 dt-bindings: watchdog: Document Google gs101 watchdog bindings dt-bindings: arm: google: Add bindings for Google ARM platforms dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible dt-bindings: serial: samsung: Add google-gs101-uart compatible dt-bindings: serial: samsung: Make samsung,uart-fifosize required property clk: samsung: clk-pll: Add support for pll_{0516,0517,518} clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support pinctrl: samsung: Add filter selection support for alive banks pinctrl: samsung: Add gs101 SoC pinctrl configuration watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit watchdog: s3c2410_wdt: Add support for Google gs101 SoC tty: serial: samsung: Add gs101 compatible and common fifoszdt_serial_drv_data arm64: dts: exynos: google: Add initial Google gs101 SoC support arm64: dts: exynos: google: Add initial Oriole/pixel 6 board support MAINTAINERS: add entry for Google Tensor SoC Tudor Ambarus (1): dt-bindings: soc: samsung: usi: add google,gs101-usi compatible .../devicetree/bindings/arm/google.yaml | 53 + .../bindings/clock/google,gs101-clock.yaml | 110 + .../samsung,pinctrl-wakeup-interrupt.yaml | 2 + .../bindings/pinctrl/samsung,pinctrl.yaml | 1 + .../bindings/serial/samsung_uart.yaml | 11 + .../bindings/soc/samsung/exynos-pmu.yaml | 2 + .../bindings/soc/samsung/exynos-usi.yaml | 3 + .../soc/samsung/samsung,exynos-sysreg.yaml | 6 + .../bindings/watchdog/samsung-wdt.yaml | 8 +- MAINTAINERS | 10 + arch/arm64/boot/dts/exynos/Makefile | 2 + arch/arm64/boot/dts/exynos/google/Makefile | 4 + .../boot/dts/exynos/google/gs101-oriole.dts | 105 + .../boot/dts/exynos/google/gs101-pinctrl.dtsi | 1250 +++++++++ .../boot/dts/exynos/google/gs101-pinctrl.h | 33 + arch/arm64/boot/dts/exynos/google/gs101.dtsi | 476 ++++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-gs101.c | 2495 +++++++++++++++++ drivers/clk/samsung/clk-pll.c | 6 + drivers/clk/samsung/clk-pll.h | 3 + .../pinctrl/samsung/pinctrl-exynos-arm64.c | 159 ++ drivers/pinctrl/samsung/pinctrl-exynos.c | 91 +- drivers/pinctrl/samsung/pinctrl-exynos.h | 41 + drivers/pinctrl/samsung/pinctrl-samsung.c | 4 + drivers/pinctrl/samsung/pinctrl-samsung.h | 23 + drivers/tty/serial/samsung_tty.c | 16 + drivers/watchdog/s3c2410_wdt.c | 74 +- include/dt-bindings/clock/google,gs101.h | 392 +++ 28 files changed, 5370 insertions(+), 11 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/google.yaml create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml create mode 100644 arch/arm64/boot/dts/exynos/google/Makefile create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-oriole.dts create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h create mode 100644 arch/arm64/boot/dts/exynos/google/gs101.dtsi create mode 100644 drivers/clk/samsung/clk-gs101.c create mode 100644 include/dt-bindings/clock/google,gs101.h