| Message ID | 20231231171237.3322376-3-quic_jprakash@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | iio: adc: Add support for QCOM SPMI PMIC5 Gen3 ADC | expand |
On Sun, 31 Dec 2023 at 19:13, Jishnu Prakash <quic_jprakash@quicinc.com> wrote: > > For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the > following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. > > It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs > going through PBS(Programmable Boot Sequence) firmware through a single > register interface. This interface is implemented on an SDAM (Shared > Direct Access Memory) peripheral on the master PMIC PMK8550 rather > than a dedicated ADC peripheral. > > Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC > channels and virtual channels (combination of ADC channel number and > PMIC SID number) per PMIC, to be used by clients of this device. > > Changes since v2: > - Moved ADC5 Gen3 documentation into a separate new file. > > Changes since v1: > - Updated properties separately for all compatibles to clarify usage > of new properties and updates in usage of old properties for ADC5 Gen3. > - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment > mentioning this convention. > - Used predefined channel IDs in individual PMIC channel definitions > instead of numeric IDs. > - Addressed other comments from reviewers. > > Co-developed-by: Anjelique Melendez <quic_amelende@quicinc.com> > Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com> > Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> > --- > .../bindings/iio/adc/qcom,spmi-adc5-gen3.yaml | 212 ++++++++++++++++++ > .../iio/adc/qcom,spmi-adc5-gen3-pm8550.h | 50 +++++ > .../iio/adc/qcom,spmi-adc5-gen3-pm8550b.h | 89 ++++++++ > .../iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h | 22 ++ > .../iio/adc/qcom,spmi-adc5-gen3-pmk8550.h | 56 +++++ > .../iio/adc/qcom,spmi-adc7-pmr735b.h | 2 +- > .../iio/adc/qcom,spmi-adc7-smb139x.h | 2 +- > include/dt-bindings/iio/adc/qcom,spmi-vadc.h | 81 +++++++ > 8 files changed, 512 insertions(+), 2 deletions(-) > create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml > create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h > create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h > create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h > create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h > > diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml > new file mode 100644 > index 000000000000..ed5bb53e7628 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml > @@ -0,0 +1,212 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm's SPMI PMIC ADC5 Gen3 > + > +maintainers: > + - Jishnu Prakash <quic_jprakash@quicinc.com> > + > +description: | > + SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to > + clients to read voltage. It is a 16-bit sigma-delta ADC. > + It also performs the same thermal monitoring function as > + the existing ADC_TM devices. > + > +properties: > + compatible: > + const: qcom,spmi-adc5-gen3 > + > + reg: > + description: | > + - Each reg corresponds to an SDAM peripheral base address that is being used for ADC. > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + "#thermal-sensor-cells": > + const: 1 > + description: > + Number of cells required to uniquely identify the thermal sensors. Since > + we have multiple sensors this is set to 1. This property is required for > + ADC devices with channels used for TM (thermal monitoring) functionality. > + > + '#io-channel-cells': > + const: 1 > + > + interrupts: > + description: | > + End of conversion interrupt. Interrupts are defined for each SDAM being used. > + > + interrupt-names: > + minItems: 1 > + maxItems: 10 > + items: > + pattern: "^adc-sdam[0-9]+$" > + description: | > + Names should be defined as "adc-sdam<N>" where <N> represents the SDAM index. > + > +required: > + - compatible > + - reg > + - '#address-cells' > + - '#size-cells' > + - '#io-channel-cells' > + - interrupts > + - interrupt-names > + > +patternProperties: > + "^channel@[0-9a-f]+$": > + type: object > + additionalProperties: false > + description: | > + Represents the external channels which are connected to the ADC. > + > + properties: > + reg: > + maxItems: 1 > + description: | > + ADC channel number. > + See include/dt-bindings/iio/adc/qcom,spmi-vadc.h > + For PMIC5 Gen3 ADC, the channel numbers are specified separately > + per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc. > + > + label: > + $ref: /schemas/types.yaml#/definitions/string > + description: | > + ADC input of the platform as seen in the schematics. > + For thermistor inputs connected to generic AMUX or GPIO inputs > + these can vary across platform for the same pins. Hence select > + the platform schematics name for this channel. > + > + qcom,decimation: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + This parameter is used to decrease ADC sampling rate. > + Quicker measurements can be made by reducing decimation ratio. > + enum: [ 85, 340, 1360 ] > + default: 1360 > + > + qcom,pre-scaling: > + description: | > + Used for scaling the channel input signal before the signal is > + fed to VADC. The configuration for this node is to know the > + pre-determined ratio and use it for post scaling. It is a pair of > + integers, denoting the numerator and denominator of the fraction by which > + input signal is multiplied. For example, <1 3> indicates the signal is scaled > + down to 1/3 of its value before ADC measurement. > + If property is not found default value depending on chip will be used. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + items: > + - const: 1 > + - enum: [ 1, 3, 6, 16 ] > + > + qcom,ratiometric: > + description: | > + Channel calibration type. > + - If this property is specified VADC will use the VDD reference (1.875V) > + and GND for channel calibration. If property is not found, channel will be > + calibrated with 0V and 1.25V reference channels, also known as > + absolute calibration. > + type: boolean > + > + qcom,hw-settle-time: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Time between AMUX getting configured and the ADC starting > + conversion. The 'hw_settle_time' is an index used from valid values > + and programmed in hardware to achieve the hardware settling delay. > + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, > + 8000, 16000, 32000, 64000, 128000 ] > + default: 15 > + > + qcom,avg-samples: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Number of samples to be used for measurement. > + Averaging provides the option to obtain a single measurement > + from the ADC that is an average of multiple samples. The value > + selected is 2^(value). > + enum: [ 1, 2, 4, 8, 16 ] > + default: 1 > + > + qcom,adc-tm: > + description: | > + Indicates if ADC_TM monitoring is done on this channel. > + Defined for compatible property "qcom,spmi-adc5-gen3". > + This is the same functionality as in the existing QCOM ADC_TM > + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml. > + type: boolean > + > + required: > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h> > + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h> > + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h> > + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + pmic { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* VADC node */ > + pmk8550_vadc: vadc@9000 { > + compatible = "qcom,spmi-adc5-gen3"; > + reg = <0x9000>, <0x9100>; > + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, > + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "adc-sdam0", "adc-sdam1"; > + #address-cells = <1>; > + #size-cells = <0>; > + #io-channel-cells = <1>; > + #thermal-sensor-cells = <1>; > + > + /* PMK8550 Channel nodes */ > + channel@3 { > + reg = <PMK8550_ADC5_GEN3_DIE_TEMP>; > + label = "pmk8550_die_temp"; > + qcom,pre-scaling = <1 1>; > + }; > + > + channel@44 { > + reg = <PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>; > + label = "pmk8550_xo_therm"; > + qcom,pre-scaling = <1 1>; > + qcom,ratiometric; > + qcom,hw-settle-time = <200>; > + qcom,adc-tm; > + }; > + > + /* PM8550 Channel nodes */ > + channel@103 { > + reg = <PM8550_ADC5_GEN3_DIE_TEMP>; > + label = "pm8550_die_temp"; > + qcom,pre-scaling = <1 1>; > + }; > + > + /* PM8550B Channel nodes */ > + channel@78f { > + reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>; > + label = "pm8550b_vbat_sns_qbg"; > + qcom,pre-scaling = <1 3>; > + }; > + > + /* PM8550VS_C Channel nodes */ > + channel@203 { > + reg = <PM8550VS_ADC5_GEN3_DIE_TEMP(2)>; > + label = "pm8550vs_c_die_temp"; > + qcom,pre-scaling = <1 1>; > + }; > + }; > + }; > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h > new file mode 100644 > index 000000000000..0f25ef87ed5c > --- /dev/null > +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h > @@ -0,0 +1,50 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H > + > +#ifndef PM8550_SID > +#define PM8550_SID 1 > +#endif Please drop these defaults. We should drop them from the existing binding files too... > + > +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> >
On Sun, 31 Dec 2023 22:42:36 +0530 Jishnu Prakash <quic_jprakash@quicinc.com> wrote: > For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the > following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. > > It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs > going through PBS(Programmable Boot Sequence) firmware through a single > register interface. This interface is implemented on an SDAM (Shared > Direct Access Memory) peripheral on the master PMIC PMK8550 rather > than a dedicated ADC peripheral. > > Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC > channels and virtual channels (combination of ADC channel number and > PMIC SID number) per PMIC, to be used by clients of this device. > > Changes since v2: > - Moved ADC5 Gen3 documentation into a separate new file. > > Changes since v1: > - Updated properties separately for all compatibles to clarify usage > of new properties and updates in usage of old properties for ADC5 Gen3. > - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment > mentioning this convention. > - Used predefined channel IDs in individual PMIC channel definitions > instead of numeric IDs. > - Addressed other comments from reviewers. change log below the --- Comments inline. Jonathan > > Co-developed-by: Anjelique Melendez <quic_amelende@quicinc.com> > Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com> > Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> > --- > .../bindings/iio/adc/qcom,spmi-adc5-gen3.yaml | 212 ++++++++++++++++++ > .../iio/adc/qcom,spmi-adc5-gen3-pm8550.h | 50 +++++ > .../iio/adc/qcom,spmi-adc5-gen3-pm8550b.h | 89 ++++++++ > .../iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h | 22 ++ > .../iio/adc/qcom,spmi-adc5-gen3-pmk8550.h | 56 +++++ > .../iio/adc/qcom,spmi-adc7-pmr735b.h | 2 +- > .../iio/adc/qcom,spmi-adc7-smb139x.h | 2 +- > include/dt-bindings/iio/adc/qcom,spmi-vadc.h | 81 +++++++ > 8 files changed, 512 insertions(+), 2 deletions(-) > create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml > create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h > create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h > create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h > create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h > > diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml > new file mode 100644 > index 000000000000..ed5bb53e7628 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml > @@ -0,0 +1,212 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm's SPMI PMIC ADC5 Gen3 > + > +maintainers: > + - Jishnu Prakash <quic_jprakash@quicinc.com> > + > +description: | > + SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to > + clients to read voltage. It is a 16-bit sigma-delta ADC. > + It also performs the same thermal monitoring function as Line wrap is too short. > + the existing ADC_TM devices. > + > +properties: > + compatible: > + const: qcom,spmi-adc5-gen3 > + > + reg: > + description: | > + - Each reg corresponds to an SDAM peripheral base address that is being used for ADC. Formatted text / bullet point seems unnecessary as only one entyr. description: Each reg corresponds to an ... > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + "#thermal-sensor-cells": > + const: 1 > + description: > + Number of cells required to uniquely identify the thermal sensors. Since > + we have multiple sensors this is set to 1. This property is required for > + ADC devices with channels used for TM (thermal monitoring) functionality. > + > + '#io-channel-cells': > + const: 1 > + > + interrupts: > + description: | > + End of conversion interrupt. Interrupts are defined for each SDAM being used. As before - no need to preserve formatting for a simple one line statement. > + > + interrupt-names: > + minItems: 1 > + maxItems: 10 > + items: > + pattern: "^adc-sdam[0-9]+$" > + description: | > + Names should be defined as "adc-sdam<N>" where <N> represents the SDAM index. > + > +required: > + - compatible > + - reg > + - '#address-cells' > + - '#size-cells' > + - '#io-channel-cells' > + - interrupts > + - interrupt-names > + > +patternProperties: > + "^channel@[0-9a-f]+$": > + type: object > + additionalProperties: false > + description: | > + Represents the external channels which are connected to the ADC. > + > + properties: > + reg: > + maxItems: 1 > + description: | > + ADC channel number. > + See include/dt-bindings/iio/adc/qcom,spmi-vadc.h > + For PMIC5 Gen3 ADC, the channel numbers are specified separately > + per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc. > + > + label: > + $ref: /schemas/types.yaml#/definitions/string > + description: | > + ADC input of the platform as seen in the schematics. > + For thermistor inputs connected to generic AMUX or GPIO inputs > + these can vary across platform for the same pins. Hence select > + the platform schematics name for this channel. defined in adc.yaml, so should just have a reference to that here. > + > + qcom,decimation: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + This parameter is used to decrease ADC sampling rate. > + Quicker measurements can be made by reducing decimation ratio. Why is this in DT rather than as a userspace control? > + enum: [ 85, 340, 1360 ] > + default: 1360 > + > + qcom,pre-scaling: > + description: | > + Used for scaling the channel input signal before the signal is > + fed to VADC. The configuration for this node is to know the > + pre-determined ratio and use it for post scaling. It is a pair of > + integers, denoting the numerator and denominator of the fraction by which > + input signal is multiplied. For example, <1 3> indicates the signal is scaled > + down to 1/3 of its value before ADC measurement. > + If property is not found default value depending on chip will be used. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + items: > + - const: 1 > + - enum: [ 1, 3, 6, 16 ] > + > + qcom,ratiometric: > + description: | > + Channel calibration type. > + - If this property is specified VADC will use the VDD reference (1.875V) > + and GND for channel calibration. If property is not found, channel will be > + calibrated with 0V and 1.25V reference channels, also known as > + absolute calibration. > + type: boolean > + > + qcom,hw-settle-time: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Time between AMUX getting configured and the ADC starting > + conversion. The 'hw_settle_time' is an index used from valid values > + and programmed in hardware to achieve the hardware settling delay. > + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, > + 8000, 16000, 32000, 64000, 128000 ] > + default: 15 only currently defined for muxes but we have settle-time-us which has benefit of providing the units (which are missing here from the description as well) > + > + qcom,avg-samples: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Number of samples to be used for measurement. > + Averaging provides the option to obtain a single measurement > + from the ADC that is an average of multiple samples. The value > + selected is 2^(value). Why is this in dt? Why not just userspace control (in_voltageX_oversampling_ratio If it needs to be, we do have standard DT bindings for it in adc.yaml > + enum: [ 1, 2, 4, 8, 16 ] > + default: 1 > + > + qcom,adc-tm: > + description: | > + Indicates if ADC_TM monitoring is done on this channel. > + Defined for compatible property "qcom,spmi-adc5-gen3". > + This is the same functionality as in the existing QCOM ADC_TM > + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml. > + type: boolean > + > + required: > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h> > + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h> > + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h> > + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + pmic { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* VADC node */ > + pmk8550_vadc: vadc@9000 { > + compatible = "qcom,spmi-adc5-gen3"; > + reg = <0x9000>, <0x9100>; > + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, > + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "adc-sdam0", "adc-sdam1"; > + #address-cells = <1>; > + #size-cells = <0>; > + #io-channel-cells = <1>; > + #thermal-sensor-cells = <1>; > + > + /* PMK8550 Channel nodes */ > + channel@3 { > + reg = <PMK8550_ADC5_GEN3_DIE_TEMP>; > + label = "pmk8550_die_temp"; > + qcom,pre-scaling = <1 1>; > + }; > + > + channel@44 { > + reg = <PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>; > + label = "pmk8550_xo_therm"; > + qcom,pre-scaling = <1 1>; > + qcom,ratiometric; > + qcom,hw-settle-time = <200>; > + qcom,adc-tm; > + }; > + > + /* PM8550 Channel nodes */ > + channel@103 { > + reg = <PM8550_ADC5_GEN3_DIE_TEMP>; > + label = "pm8550_die_temp"; > + qcom,pre-scaling = <1 1>; > + }; > + > + /* PM8550B Channel nodes */ > + channel@78f { > + reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>; > + label = "pm8550b_vbat_sns_qbg"; > + qcom,pre-scaling = <1 3>; > + }; > + > + /* PM8550VS_C Channel nodes */ > + channel@203 { > + reg = <PM8550VS_ADC5_GEN3_DIE_TEMP(2)>; > + label = "pm8550vs_c_die_temp"; > + qcom,pre-scaling = <1 1>; > + }; > + }; > + }; > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h > new file mode 100644 > index 000000000000..0f25ef87ed5c > --- /dev/null > +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h > @@ -0,0 +1,50 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H > + > +#ifndef PM8550_SID > +#define PM8550_SID 1 > +#endif > + > +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> > + > +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */ > +#define PM8550_ADC5_GEN3_REF_GND (PM8550_SID << 8 | ADC5_GEN3_REF_GND) > +#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | ADC5_GEN3_1P25VREF) > +#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | ADC5_GEN3_VREF_VADC) > +#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | ADC5_GEN3_DIE_TEMP) > + > +#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | ADC5_GEN3_AMUX1_THM) > +#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | ADC5_GEN3_AMUX2_THM) > +#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_THM) > +#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_THM) > +#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | ADC5_GEN3_AMUX5_THM) > +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | ADC5_GEN3_AMUX6_THM) > +#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO) > +#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | ADC5_GEN3_AMUX2_GPIO) > +#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO) > +#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO) > + > +/* 100k pull-up */ > +#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU) > + > +/* 1/3 Divider */ > +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3) > +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO_DIV3) > + > +#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | ADC5_GEN3_VPH_PWR) > + > +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */ > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h > new file mode 100644 > index 000000000000..47116bbe45de > --- /dev/null > +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h > @@ -0,0 +1,89 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H > + > +#ifndef PM8550B_SID > +#define PM8550B_SID 7 > +#endif > + > +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> > + > +/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */ > +#define PM8550B_ADC5_GEN3_REF_GND (PM8550B_SID << 8 | ADC5_GEN3_REF_GND) > +#define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | ADC5_GEN3_1P25VREF) > +#define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | ADC5_GEN3_VREF_VADC) > +#define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | ADC5_GEN3_DIE_TEMP) > + > +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM) > +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM) > +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM) > +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM) > +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM) > +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM) > +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO) > +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO) > +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO) > +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO) > + > +#define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | ADC5_GEN3_CHG_TEMP) > +#define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | ADC5_GEN3_USB_SNS_V_16) > +#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | ADC5_GEN3_VIN_DIV16_MUX) > +#define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | ADC5_GEN3_VREF_BAT_THERM) > +#define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | ADC5_GEN3_IIN_FB) > +#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | ADC5_GEN3_TEMP_ALARM_LITE) > +#define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | ADC5_GEN3_IIN_SMB) > +#define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | ADC5_GEN3_ICHG_SMB) > +#define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | ADC5_GEN3_ICHG_FB) > + > +/* 30k pull-up */ > +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_30K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_30K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_30K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_30K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_30K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_30K_PU) > +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_30K_PU) > +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_30K_PU) > +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_30K_PU) > +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_30K_PU) > + > +/* 100k pull-up */ > +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) > +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) > +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU) > +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU) > +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU) > + > +/* 400k pull-up */ > +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_400K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_400K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_400K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_400K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_400K_PU) > +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_400K_PU) > +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_400K_PU) > +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_400K_PU) > +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_400K_PU) > +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_400K_PU) > + > +/* 1/3 Divider */ > +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_DIV3) > +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_DIV3) > +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3) > + > +#define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | ADC5_GEN3_VPH_PWR) > +#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | ADC5_GEN3_VBAT_SNS_QBG) > +#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | ADC5_GEN3_VBAT_SNS_CHGR) > +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | ADC5_GEN3_VBAT_2S_MID_QBG) > +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | ADC5_GEN3_VBAT_2S_MID_CHGR) > + > +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */ > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h > new file mode 100644 > index 000000000000..360f2245d582 > --- /dev/null > +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h > @@ -0,0 +1,22 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H > + > +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> > + > +/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */ > +#define PM8550VS_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) > +#define PM8550VS_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) > +#define PM8550VS_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC) > +#define PM8550VS_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) > + > +#define PM8550VE_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) > +#define PM8550VE_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) > +#define PM8550VE_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC) > +#define PM8550VE_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) > + > +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */ > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h > new file mode 100644 > index 000000000000..3fc829ebdf6d > --- /dev/null > +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h > @@ -0,0 +1,56 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H > + > +#ifndef PMK8550_SID > +#define PMK8550_SID 0 > +#endif > + > +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> > + > +/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */ > +#define PMK8550_ADC5_GEN3_REF_GND (PMK8550_SID << 8 | ADC5_GEN3_REF_GND) > +#define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | ADC5_GEN3_1P25VREF) > +#define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | ADC5_GEN3_VREF_VADC) > +#define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | ADC5_GEN3_DIE_TEMP) > + > +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM) > +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM) > +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM) > +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM) > +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM) > +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM) > +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO) > + > +/* 30k pull-up */ > +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_30K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_30K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_30K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_30K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_30K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_30K_PU) > +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_30K_PU) > + > +/* 100k pull-up */ > +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) > +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) > + > +/* 400k pull-up */ > +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_400K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_400K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_400K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_400K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_400K_PU) > +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_400K_PU) > +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_400K_PU) > + > +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */ > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h > index fdb8dd9ae541..812f33872e5e 100644 > --- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h > +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h > @@ -10,7 +10,7 @@ > #define PMR735B_SID 5 > #endif > > -#include <dt-bindings/iio/qcom,spmi-vadc.h> > +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> > > /* ADC channels for PMR735B_ADC for PMIC7 */ > #define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | ADC7_REF_GND) > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h > index c0680d1285cf..750a526af2c1 100644 > --- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h > +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h > @@ -6,7 +6,7 @@ > #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H > #define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H > > -#include <dt-bindings/iio/qcom,spmi-vadc.h> > +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> > > #define SMB139x_1_ADC7_SMB_TEMP (SMB139x_1_SID << 8 | ADC7_SMB_TEMP) > #define SMB139x_1_ADC7_ICHG_SMB (SMB139x_1_SID << 8 | ADC7_ICHG_SMB) > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h > index ef07ecd4d585..cfe653d945a4 100644 > --- a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h > +++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h > @@ -1,6 +1,8 @@ > /* SPDX-License-Identifier: GPL-2.0 */ > /* > * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. > + * > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > */ > > #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H > @@ -300,4 +302,83 @@ > #define ADC7_SBUx 0x94 > #define ADC7_VBAT_2S_MID 0x96 > > +/* ADC channels for PMIC5 Gen3 */ > + > +#define ADC5_GEN3_REF_GND 0x00 > +#define ADC5_GEN3_1P25VREF 0x01 > +#define ADC5_GEN3_VREF_VADC 0x02 > +#define ADC5_GEN3_DIE_TEMP 0x03 > + > +#define ADC5_GEN3_AMUX1_THM 0x04 > +#define ADC5_GEN3_AMUX2_THM 0x05 > +#define ADC5_GEN3_AMUX3_THM 0x06 > +#define ADC5_GEN3_AMUX4_THM 0x07 > +#define ADC5_GEN3_AMUX5_THM 0x08 > +#define ADC5_GEN3_AMUX6_THM 0x09 > +#define ADC5_GEN3_AMUX1_GPIO 0x0a > +#define ADC5_GEN3_AMUX2_GPIO 0x0b > +#define ADC5_GEN3_AMUX3_GPIO 0x0c > +#define ADC5_GEN3_AMUX4_GPIO 0x0d > + > +#define ADC5_GEN3_CHG_TEMP 0x10 > +#define ADC5_GEN3_USB_SNS_V_16 0x11 > +#define ADC5_GEN3_VIN_DIV16_MUX 0x12 > +#define ADC5_GEN3_VREF_BAT_THERM 0x15 > +#define ADC5_GEN3_IIN_FB 0x17 > +#define ADC5_GEN3_TEMP_ALARM_LITE 0x18 > +#define ADC5_GEN3_IIN_SMB 0x19 > +#define ADC5_GEN3_ICHG_SMB 0x1b > +#define ADC5_GEN3_ICHG_FB 0xa1 > + > +/* 30k pull-up1 */ > +#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24 > +#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25 > +#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26 > +#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27 > +#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28 > +#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29 > +#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a > +#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b > +#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c > +#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d > + > +/* 100k pull-up2 */ > +#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44 > +#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45 > +#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46 > +#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47 > +#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48 > +#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49 > +#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a > +#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b > +#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c > +#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d > + > +/* 400k pull-up3 */ > +#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64 > +#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65 > +#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66 > +#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67 > +#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68 > +#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69 > +#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a > +#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b > +#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c > +#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d > + > +/* 1/3 Divider */ > +#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a > +#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b > +#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c > +#define ADC5_GEN3_AMUX4_GPIO_DIV3 0x8d > + > +#define ADC5_GEN3_VPH_PWR 0x8e > +#define ADC5_GEN3_VBAT_SNS_QBG 0x8f > + > +#define ADC5_GEN3_VBAT_SNS_CHGR 0x94 > +#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96 > +#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d > + > +#define ADC5_GEN3_OFFSET_EXT2 0xf8 > + > #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
On 31/12/2023 18:12, Jishnu Prakash wrote: > For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the > following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. > > It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs > going through PBS(Programmable Boot Sequence) firmware through a single > register interface. This interface is implemented on an SDAM (Shared > Direct Access Memory) peripheral on the master PMIC PMK8550 rather > than a dedicated ADC peripheral. > > Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC > channels and virtual channels (combination of ADC channel number and > PMIC SID number) per PMIC, to be used by clients of this device. > > Changes since v2: > - Moved ADC5 Gen3 documentation into a separate new file. Changelog goes under ---. Why did you do this? What is the rationale? Sorry, this patchset goes nowhere. > > Changes since v1: > - Updated properties separately for all compatibles to clarify usage > of new properties and updates in usage of old properties for ADC5 Gen3. > - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment > mentioning this convention. > - Used predefined channel IDs in individual PMIC channel definitions > instead of numeric IDs. > - Addressed other comments from reviewers. > > Co-developed-by: Anjelique Melendez <quic_amelende@quicinc.com> > Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com> > Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> > --- > .../bindings/iio/adc/qcom,spmi-adc5-gen3.yaml | 212 ++++++++++++++++++ > .../iio/adc/qcom,spmi-adc5-gen3-pm8550.h | 50 +++++ > .../iio/adc/qcom,spmi-adc5-gen3-pm8550b.h | 89 ++++++++ > .../iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h | 22 ++ > .../iio/adc/qcom,spmi-adc5-gen3-pmk8550.h | 56 +++++ > .../iio/adc/qcom,spmi-adc7-pmr735b.h | 2 +- > .../iio/adc/qcom,spmi-adc7-smb139x.h | 2 +- > include/dt-bindings/iio/adc/qcom,spmi-vadc.h | 81 +++++++ > 8 files changed, 512 insertions(+), 2 deletions(-) > create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml > create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h > create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h > create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h > create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h > > diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml > new file mode 100644 > index 000000000000..ed5bb53e7628 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml > @@ -0,0 +1,212 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm's SPMI PMIC ADC5 Gen3 > + > +maintainers: > + - Jishnu Prakash <quic_jprakash@quicinc.com> > + > +description: | Do not need '|' unless you need to preserve formatting. > + SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to > + clients to read voltage. It is a 16-bit sigma-delta ADC. > + It also performs the same thermal monitoring function as > + the existing ADC_TM devices. > + > +properties: > + compatible: > + const: qcom,spmi-adc5-gen3 > + > + reg: > + description: | > + - Each reg corresponds to an SDAM peripheral base address that is being used for ADC. Missing constraints, weird formatting and not wrapped according to coding style (read Linux coding style). > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + "#thermal-sensor-cells": > + const: 1 > + description: > + Number of cells required to uniquely identify the thermal sensors. Since > + we have multiple sensors this is set to 1. This property is required for > + ADC devices with channels used for TM (thermal monitoring) functionality. > + > + '#io-channel-cells': > + const: 1 > + > + interrupts: > + description: | > + End of conversion interrupt. Interrupts are defined for each SDAM being used. Same problemns. You already got comments on this in v2. > + > + interrupt-names: > + minItems: 1 > + maxItems: 10 > + items: > + pattern: "^adc-sdam[0-9]+$" > + description: | > + Names should be defined as "adc-sdam<N>" where <N> represents the SDAM index. Don't repeat constraints in free form text. > + > +required: required: goes after all properties. > + - compatible > + - reg > + - '#address-cells' > + - '#size-cells' > + - '#io-channel-cells' > + - interrupts > + - interrupt-names > + > +patternProperties: > + "^channel@[0-9a-f]+$": > + type: object > + additionalProperties: false > + description: | Do not need '|' unless you need to preserve formatting. > + Represents the external channels which are connected to the ADC. > + > + properties: > + reg: > + maxItems: 1 > + description: | > + ADC channel number. > + See include/dt-bindings/iio/adc/qcom,spmi-vadc.h > + For PMIC5 Gen3 ADC, the channel numbers are specified separately > + per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc. > + > + label: > + $ref: /schemas/types.yaml#/definitions/string Why do you need it in the first place? Don't you miss some $ref? > + description: | Do not need '|' unless you need to preserve formatting. Applies everywhere. > + ADC input of the platform as seen in the schematics. > + For thermistor inputs connected to generic AMUX or GPIO inputs > + these can vary across platform for the same pins. Hence select > + the platform schematics name for this channel. > + > + qcom,decimation: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + This parameter is used to decrease ADC sampling rate. > + Quicker measurements can be made by reducing decimation ratio. > + enum: [ 85, 340, 1360 ] > + default: 1360 > + > + qcom,pre-scaling: > + description: | > + Used for scaling the channel input signal before the signal is > + fed to VADC. The configuration for this node is to know the > + pre-determined ratio and use it for post scaling. It is a pair of > + integers, denoting the numerator and denominator of the fraction by which > + input signal is multiplied. For example, <1 3> indicates the signal is scaled > + down to 1/3 of its value before ADC measurement. > + If property is not found default value depending on chip will be used. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + items: > + - const: 1 > + - enum: [ 1, 3, 6, 16 ] > + > + qcom,ratiometric: > + description: | > + Channel calibration type. > + - If this property is specified VADC will use the VDD reference (1.875V) > + and GND for channel calibration. If property is not found, channel will be > + calibrated with 0V and 1.25V reference channels, also known as > + absolute calibration. > + type: boolean > + > + qcom,hw-settle-time: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Time between AMUX getting configured and the ADC starting > + conversion. The 'hw_settle_time' is an index used from valid values > + and programmed in hardware to achieve the hardware settling delay. > + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, > + 8000, 16000, 32000, 64000, 128000 ] > + default: 15 > + > + qcom,avg-samples: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Number of samples to be used for measurement. > + Averaging provides the option to obtain a single measurement > + from the ADC that is an average of multiple samples. The value > + selected is 2^(value). > + enum: [ 1, 2, 4, 8, 16 ] > + default: 1 > + > + qcom,adc-tm: > + description: | > + Indicates if ADC_TM monitoring is done on this channel. > + Defined for compatible property "qcom,spmi-adc5-gen3". > + This is the same functionality as in the existing QCOM ADC_TM > + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml. > + type: boolean > + Why do you duplicate entire vadc file? Why it cannot be part of that file? Oh wait, it was in v2. You now duplicated a lot of property definitions without clear reason. If this is intention, then you need to put them in common schema. > + required: > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h> > + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h> > + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h> > + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + pmic { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* VADC node */ > + pmk8550_vadc: vadc@9000 { Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation Really, duplicating entire file and adding mistakes? Just open the original file which you changed in v2 and look how it is done there. > + compatible = "qcom,spmi-adc5-gen3"; > + reg = <0x9000>, <0x9100>; > + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, > + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; wrong alignment. > + interrupt-names = "adc-sdam0", "adc-sdam1"; > + #address-cells = <1>; > + #size-cells = <0>; > + #io-channel-cells = <1>; > + #thermal-sensor-cells = <1>; > + > + /* PMK8550 Channel nodes */ > + channel@3 { > + reg = <PMK8550_ADC5_GEN3_DIE_TEMP>; > + label = "pmk8550_die_temp"; > + qcom,pre-scaling = <1 1>; > + }; > + > + channel@44 { > + reg = <PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>; > + label = "pmk8550_xo_therm"; > + qcom,pre-scaling = <1 1>; > + qcom,ratiometric; > + qcom,hw-settle-time = <200>; > + qcom,adc-tm; > + }; > + > + /* PM8550 Channel nodes */ > + channel@103 { > + reg = <PM8550_ADC5_GEN3_DIE_TEMP>; > + label = "pm8550_die_temp"; > + qcom,pre-scaling = <1 1>; > + }; > + > + /* PM8550B Channel nodes */ > + channel@78f { > + reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>; > + label = "pm8550b_vbat_sns_qbg"; > + qcom,pre-scaling = <1 3>; > + }; > + > + /* PM8550VS_C Channel nodes */ > + channel@203 { > + reg = <PM8550VS_ADC5_GEN3_DIE_TEMP(2)>; > + label = "pm8550vs_c_die_temp"; > + qcom,pre-scaling = <1 1>; > + }; > + }; > + }; > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h > new file mode 100644 > index 000000000000..0f25ef87ed5c > --- /dev/null > +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h > @@ -0,0 +1,50 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H > + > +#ifndef PM8550_SID > +#define PM8550_SID 1 > +#endif Drop > + > +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> > + > +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */ > +#define PM8550_ADC5_GEN3_REF_GND (PM8550_SID << 8 | ADC5_GEN3_REF_GND) > +#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | ADC5_GEN3_1P25VREF) > +#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | ADC5_GEN3_VREF_VADC) > +#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | ADC5_GEN3_DIE_TEMP) > + > +#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | ADC5_GEN3_AMUX1_THM) > +#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | ADC5_GEN3_AMUX2_THM) > +#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_THM) > +#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_THM) > +#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | ADC5_GEN3_AMUX5_THM) > +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | ADC5_GEN3_AMUX6_THM) > +#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO) > +#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | ADC5_GEN3_AMUX2_GPIO) > +#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO) > +#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO) > + > +/* 100k pull-up */ > +#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU) > +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU) > + > +/* 1/3 Divider */ > +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3) > +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO_DIV3) > + > +#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | ADC5_GEN3_VPH_PWR) > + > +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */ > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h > new file mode 100644 > index 000000000000..47116bbe45de > --- /dev/null > +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h > @@ -0,0 +1,89 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H > + > +#ifndef PM8550B_SID > +#define PM8550B_SID 7 Drop > +#endif > + ... > +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */ > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h > new file mode 100644 > index 000000000000..3fc829ebdf6d > --- /dev/null > +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h > @@ -0,0 +1,56 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H > + > +#ifndef PMK8550_SID > +#define PMK8550_SID 0 > +#endif Drop > > /* ADC channels for PMR735B_ADC for PMIC7 */ > #define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | ADC7_REF_GND) > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h > index c0680d1285cf..750a526af2c1 100644 > --- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h > +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h > @@ -6,7 +6,7 @@ > #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H > #define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H > > -#include <dt-bindings/iio/qcom,spmi-vadc.h> > +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> ? How is it related? > > #define SMB139x_1_ADC7_SMB_TEMP (SMB139x_1_SID << 8 | ADC7_SMB_TEMP) > #define SMB139x_1_ADC7_ICHG_SMB (SMB139x_1_SID << 8 | ADC7_ICHG_SMB) > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h > index ef07ecd4d585..cfe653d945a4 100644 > --- a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h > +++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h > @@ -1,6 +1,8 @@ > /* SPDX-License-Identifier: GPL-2.0 */ > /* > * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. > + * Drop stray blank line Best regards, Krzysztof
Hi Jonathan, On 1/1/2024 11:32 PM, Jonathan Cameron wrote: > On Sun, 31 Dec 2023 22:42:36 +0530 > Jishnu Prakash <quic_jprakash@quicinc.com> wrote: > >> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the >> + >> + label: >> + $ref: /schemas/types.yaml#/definitions/string >> + description: | >> + ADC input of the platform as seen in the schematics. >> + For thermistor inputs connected to generic AMUX or GPIO inputs >> + these can vary across platform for the same pins. Hence select >> + the platform schematics name for this channel. > defined in adc.yaml, so should just have a reference to that here. > >> + >> + qcom,decimation: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: | >> + This parameter is used to decrease ADC sampling rate. >> + Quicker measurements can be made by reducing decimation ratio. > Why is this in DT rather than as a userspace control? We don't intend this property to be something that can be controlled from userspace - if a client wants to read an ADC channel from userspace, we only intend to provide them the processed value, calculated with a fixed set of ADC properties mentioned in the corresponding channel node in DT. >> + enum: [ 85, 340, 1360 ] >> + default: 1360 >> + >> + >> + qcom,hw-settle-time: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: | >> + Time between AMUX getting configured and the ADC starting >> + conversion. The 'hw_settle_time' is an index used from valid values >> + and programmed in hardware to achieve the hardware settling delay. >> + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, >> + 8000, 16000, 32000, 64000, 128000 ] >> + default: 15 > only currently defined for muxes but we have settle-time-us which has benefit of > providing the units (which are missing here from the description as well) > >> + >> + qcom,avg-samples: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: | >> + Number of samples to be used for measurement. >> + Averaging provides the option to obtain a single measurement >> + from the ADC that is an average of multiple samples. The value >> + selected is 2^(value). > Why is this in dt? Why not just userspace control (in_voltageX_oversampling_ratio > > If it needs to be, we do have standard DT bindings for it in adc.yaml avg-samples is also something we don't want the client to modify from userspace. As for using adc.yaml, I think I could use settling-time-us and oversampling-ratio from it for the above two properties. However, Krzysztof has mentioned in another comment that I should put properties common to ADC5 Gen3 and older QCOM VADC devices in a common schema. If I now try replacing the existing qcom,hw-settle-time and qcom,avg-samples properties with settling-time-us and oversampling-ratio for older devices too, I would have to make several DT changes for existing devices...are you fine with this? Or should I just replace these two properties for ADC5 Gen3? I'll address your other comments in the next patchset. Thanks, Jishnu
Hi Jishnu, On Fri, 16 Feb 2024 at 12:39, Jishnu Prakash <quic_jprakash@quicinc.com> wrote: Please disable sending HTML emails in your email client. It is generally frowned upon, it complicates replying, it breaks quotations, etc. > > Hi Krzysztof, > > On 1/4/2024 1:48 PM, Krzysztof Kozlowski wrote: > > On 31/12/2023 18:12, Jishnu Prakash wrote: > > For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the > following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. > > It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs > going through PBS(Programmable Boot Sequence) firmware through a single > register interface. This interface is implemented on an SDAM (Shared > Direct Access Memory) peripheral on the master PMIC PMK8550 rather > than a dedicated ADC peripheral. > > Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC > channels and virtual channels (combination of ADC channel number and > PMIC SID number) per PMIC, to be used by clients of this device. > > Changes since v2: > - Moved ADC5 Gen3 documentation into a separate new file. > > Changelog goes under ---. > > Why did you do this? What is the rationale? Sorry, this patchset goes > nowhere. > > > I'll elaborate this more in the next patchset. There are two main reasons for adding this documentation in a new file: > > 1.This device is not exactly like the existing QCOM VADC drivers as it now combines VADC functionality (reading ADC channel on client request) with ADC_TM functionality (thermal threshold monitoring). > > 2.Adding this device's bindings in the existing qcom,spmi-vadc.yaml file is not possible as it would require updating some of the existing top-level constraints. (for the older devices in that file, "reg" and "interrupts" can have at most one item, while this device can have more than one item under these properties.) > > > Changes since v1: > - Updated properties separately for all compatibles to clarify usage > of new properties and updates in usage of old properties for ADC5 Gen3. > - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment > mentioning this convention. > - Used predefined channel IDs in individual PMIC channel definitions > instead of numeric IDs. > - Addressed other comments from reviewers. > > > + per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc. > + > + label: > + $ref: /schemas/types.yaml#/definitions/string > > Why do you need it in the first place? Don't you miss some $ref? > > > This is just meant to show the ADC channel name in DT for our reference. I'll check if I can use adc.yaml, which includes this property already, as a reference in this case. > > > + description: | > > Do not need '|' unless you need to preserve formatting. Applies everywhere. > > > > + ADC input of the platform as seen in the schematics. > + For thermistor inputs connected to generic AMUX or GPIO inputs > + these can vary across platform for the same pins. Hence select > + the platform schematics name for this channel. > + > > + qcom,adc-tm: > + description: | > + Indicates if ADC_TM monitoring is done on this channel. > + Defined for compatible property "qcom,spmi-adc5-gen3". You are describing qcom,spmi-adc5-gen3, are you not? So this phrase adds nothing. > + This is the same functionality as in the existing QCOM ADC_TM > + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml. > + type: boolean > + > > Why do you duplicate entire vadc file? Why it cannot be part of that > file? Oh wait, it was in v2. > > You now duplicated a lot of property definitions without clear reason. > If this is intention, then you need to put them in common schema. > > > Many of the properties used for earlier QCOM VADC devices will be used for this device too.....do you mean I can add a new schema file (named something like qcom,vadc.yaml) and move common properties into it (like qcom,hw-settle-time, qcom,decimation, etc) from this file and qcom,spmi-vadc.yaml? > > Can I do it in the same patch or should it be a separate patch coming before this one ? I'd say, separate patch. Move first, extend later. > > > > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h > > index c0680d1285cf..750a526af2c1 100644 > --- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h > +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h > @@ -6,7 +6,7 @@ > #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H > #define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H > > -#include <dt-bindings/iio/qcom,spmi-vadc.h> > +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> > > ? How is it related? > > > This should have gone into patch 1, I'll fix it in the next patch series. > > I'll address all your other comments in the next patchset. > > Thanks, > > Jishnu > > > > #define SMB139x_1_ADC7_SMB_TEMP (SMB139x_1_SID << 8 | ADC7_SMB_TEMP) > #define SMB139x_1_ADC7_ICHG_SMB (SMB139x_1_SID << 8 | ADC7_ICHG_SMB) > diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h > index ef07ecd4d585..cfe653d945a4 100644 > --- a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h > +++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h > @@ -1,6 +1,8 @@ > /* SPDX-License-Identifier: GPL-2.0 */ > /* > * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. > + * > > Drop stray blank line > > Best regards, > Krzysztof >
Hi Dmitry, On 2/16/2024 4:18 PM, Dmitry Baryshkov wrote: > Hi Jishnu, > > > On Fri, 16 Feb 2024 at 12:39, Jishnu Prakash <quic_jprakash@quicinc.com> wrote: > > Please disable sending HTML emails in your email client. It is > generally frowned upon, it complicates replying, it breaks quotations, > etc. Sorry, I'm not sure how that happened, but I have fixed it now. > >> >> Hi Krzysztof, >> >> On 1/4/2024 1:48 PM, Krzysztof Kozlowski wrote: >> >> On 31/12/2023 18:12, Jishnu Prakash wrote: >> >> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the >> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. >> >> + >> >> + qcom,adc-tm: >> + description: | >> + Indicates if ADC_TM monitoring is done on this channel. >> + Defined for compatible property "qcom,spmi-adc5-gen3". > > You are describing qcom,spmi-adc5-gen3, are you not? So this phrase > adds nothing. Yes, I'll remove this. > >> + This is the same functionality as in the existing QCOM ADC_TM >> + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml. >> + type: boolean >> + >> >> Why do you duplicate entire vadc file? Why it cannot be part of that >> file? Oh wait, it was in v2. >> >> You now duplicated a lot of property definitions without clear reason. >> If this is intention, then you need to put them in common schema. >> >> >> Many of the properties used for earlier QCOM VADC devices will be used for this device too.....do you mean I can add a new schema file (named something like qcom,vadc.yaml) and move common properties into it (like qcom,hw-settle-time, qcom,decimation, etc) from this file and qcom,spmi-vadc.yaml? >> >> Can I do it in the same patch or should it be a separate patch coming before this one ? > > I'd say, separate patch. Move first, extend later. OK, I'll make it this way if no one else has any objections. Thanks, Jishnu > >> >> >>
On Fri, 16 Feb 2024 16:09:38 +0530 Jishnu Prakash <quic_jprakash@quicinc.com> wrote: > Hi Jonathan, > > On 1/1/2024 11:32 PM, Jonathan Cameron wrote: > > On Sun, 31 Dec 2023 22:42:36 +0530 > > Jishnu Prakash <quic_jprakash@quicinc.com> wrote: > > > >> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the > > >> + > >> + label: > >> + $ref: /schemas/types.yaml#/definitions/string > >> + description: | > >> + ADC input of the platform as seen in the schematics. > >> + For thermistor inputs connected to generic AMUX or GPIO inputs > >> + these can vary across platform for the same pins. Hence select > >> + the platform schematics name for this channel. > > defined in adc.yaml, so should just have a reference to that here. > > > >> + > >> + qcom,decimation: > >> + $ref: /schemas/types.yaml#/definitions/uint32 > >> + description: | > >> + This parameter is used to decrease ADC sampling rate. > >> + Quicker measurements can be made by reducing decimation ratio. > > Why is this in DT rather than as a userspace control? > > > We don't intend this property to be something that can be controlled > from userspace - if a client wants to read an ADC channel from > userspace, we only intend to provide them the processed value, > calculated with a fixed set of ADC properties mentioned in the > corresponding channel node in DT. Why? This is a way to control precision of an ADC channel read out. That's policy rather than dependent on the hardware. To be in DT we (mostly) need it to be related to the hardware configuration (i.e. what it is wired to etc). > > > >> + enum: [ 85, 340, 1360 ] > >> + default: 1360 > >> + > > >> + > >> + qcom,hw-settle-time: > >> + $ref: /schemas/types.yaml#/definitions/uint32 > >> + description: | > >> + Time between AMUX getting configured and the ADC starting > >> + conversion. The 'hw_settle_time' is an index used from valid values > >> + and programmed in hardware to achieve the hardware settling delay. > >> + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, > >> + 8000, 16000, 32000, 64000, 128000 ] > >> + default: 15 > > only currently defined for muxes but we have settle-time-us which has benefit of > > providing the units (which are missing here from the description as well) > > > >> + > >> + qcom,avg-samples: > >> + $ref: /schemas/types.yaml#/definitions/uint32 > >> + description: | > >> + Number of samples to be used for measurement. > >> + Averaging provides the option to obtain a single measurement > >> + from the ADC that is an average of multiple samples. The value > >> + selected is 2^(value). > > Why is this in dt? Why not just userspace control (in_voltageX_oversampling_ratio > > > > If it needs to be, we do have standard DT bindings for it in adc.yaml > > > avg-samples is also something we don't want the client to modify from > userspace. As for using adc.yaml, I think I could use settling-time-us > and oversampling-ratio from it for the above two properties. Same as for above. This is policy. If you want to control it that belongs in a udev script or similar, not the DT bindings. We tend to resist defining such policy in DT because it isn't a characteristic of the hardware and depending on the usecase userspace may have good reason to tweak the settings (or consumer drivers if you have those as sometimes these numbers are about getting a particular precision needed for what we are measuring to be useful for another driver). There is some legacy for this though as you point out. So that may be a strong enough argument for why we should make an exception this time. If so make that clear in the patch description. > > However, Krzysztof has mentioned in another comment that I should put > properties common to ADC5 Gen3 and older QCOM VADC devices in a common > schema. If I now try replacing the existing qcom,hw-settle-time and > qcom,avg-samples properties with settling-time-us and oversampling-ratio > for older devices too, I would have to make several DT changes for > existing devices...are you fine with this? Or should I just replace > these two properties for ADC5 Gen3? If you change DT binding for older devices, you will need to maintain backwards compatibility. It's fine to deprecate them in the binding docs etc, but not the driver (as there may be old DT on devices that can't be easily updated). > > > I'll address your other comments in the next patchset. > > > Thanks, > > Jishnu >
On 16/02/2024 11:39, Jishnu Prakash wrote: > Hi Krzysztof, > > On 1/4/2024 1:48 PM, Krzysztof Kozlowski wrote: >> On 31/12/2023 18:12, Jishnu Prakash wrote: >>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the >>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. >>> >>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs >>> going through PBS(Programmable Boot Sequence) firmware through a single >>> register interface. This interface is implemented on an SDAM (Shared >>> Direct Access Memory) peripheral on the master PMIC PMK8550 rather >>> than a dedicated ADC peripheral. >>> >>> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC >>> channels and virtual channels (combination of ADC channel number and >>> PMIC SID number) per PMIC, to be used by clients of this device. >>> >>> Changes since v2: >>> - Moved ADC5 Gen3 documentation into a separate new file. >> Changelog goes under ---. >> >> Why did you do this? What is the rationale? Sorry, this patchset goes >> nowhere. > > > I'll elaborate this more in the next patchset. There are two main > reasons for adding this documentation in a new file: This was more than a month ago? You reply to my comment with 1.5 months delay? Sorry, I am not in the context and I am not going back to it. I have many other emails where my questions are addressed faster than 1.5 months. The patch is not even in my mailbox, long gone. Why you are making it so difficult for reviewers? You will get answers like I am not in context, sorry. Next time don't respond after 1.5 months. > > 1.This device is not exactly like the existing QCOM VADC drivers as it > now combines VADC functionality (reading ADC channel on client request) > with ADC_TM functionality (thermal threshold monitoring). Does no explain touching bindings. Your drivers don't matter for bindings. > > 2.Adding this device's bindings in the existing qcom,spmi-vadc.yaml file No rationale was provided in commit msg. > is not possible as it would require updating some of the existing > top-level constraints. (for the older devices in that file, "reg" and > "interrupts" can have at most one item, while this device can have more > than one item under these properties.) How is this a problem? Best regards, Krzysztof
On 16/02/2024 12:44, Jishnu Prakash wrote: > Hi Krzysztof, > > (Resending this mail for tracking on mailing lists, as it got rejected > from lists the first time due to HTML) I already responded to some other email of yours and I am not going to respond twice. Best regards, Krzysztof
Hi Krzysztof, On 2/17/2024 7:43 PM, Krzysztof Kozlowski wrote: > On 16/02/2024 11:39, Jishnu Prakash wrote: >> Hi Krzysztof, >> >> On 1/4/2024 1:48 PM, Krzysztof Kozlowski wrote: >>> On 31/12/2023 18:12, Jishnu Prakash wrote: >>>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the >>>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. >>>> >>>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs >>>> going through PBS(Programmable Boot Sequence) firmware through a single >>>> register interface. This interface is implemented on an SDAM (Shared >>>> Direct Access Memory) peripheral on the master PMIC PMK8550 rather >>>> than a dedicated ADC peripheral. >>>> >>>> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC >>>> channels and virtual channels (combination of ADC channel number and >>>> PMIC SID number) per PMIC, to be used by clients of this device. >>>> >>>> Changes since v2: >>>> - Moved ADC5 Gen3 documentation into a separate new file. >>> Changelog goes under ---. >>> >>> Why did you do this? What is the rationale? Sorry, this patchset goes >>> nowhere. >> >> >> I'll elaborate this more in the next patchset. There are two main >> reasons for adding this documentation in a new file: > > This was more than a month ago? You reply to my comment with 1.5 months > delay? > > Sorry, I am not in the context and I am not going back to it. I have > many other emails where my questions are addressed faster than 1.5 months. > > The patch is not even in my mailbox, long gone. > Why you are making it so difficult for reviewers? > > You will get answers like I am not in context, sorry. Next time don't > respond after 1.5 months. > You're right - I'll do my best to get back to review comments in a reasonable time frame. > >> >> 1.This device is not exactly like the existing QCOM VADC drivers as it >> now combines VADC functionality (reading ADC channel on client request) >> with ADC_TM functionality (thermal threshold monitoring). > > Does no explain touching bindings. Your drivers don't matter for bindings. > >> >> 2.Adding this device's bindings in the existing qcom,spmi-vadc.yaml file > > No rationale was provided in commit msg. > >> is not possible as it would require updating some of the existing >> top-level constraints. (for the older devices in that file, "reg" and >> "interrupts" can have at most one item, while this device can have more >> than one item under these properties.) > > How is this a problem? In qcom,spmi-vadc.yaml, we have the following top-level constraints for the "reg" and "interrupts" properties: reg: maxItems: 1 interrupts: maxItems: 1 For the ADC5 Gen3 device being added now, these constraints cannot be followed always, as there may be more than one peripheral under one device instance, each with a corresponding interrupt. For example, the above properties could be like this for a ADC5 Gen3 device: reg = <0x9000>, <0x9100>; interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; I could not overwrite the top-level constraints for the new device "qcom,spmi-adc5-gen3" alone in qcom,spmi-vadc.yaml, so I tried to remove the constraints from the top level and add them back conditionally for all the device types separately, but you told me not to remove them (full message: https://lore.kernel.org/linux-iio/832053f4-bd5d-4e58-81bb-1a8188e7f364@linaro.org/) Since these constraints cannot be modified for a specific new device or removed, I think the only way to accommodate this new device is to add it in its own new file. Is this a sufficient justification for adding this documentation in a new file or do you have any other suggestions? Thanks, Jishnu > > > Best regards, > Krzysztof >
On 21/02/2024 06:36, Jishnu Prakash wrote: > Hi Krzysztof, > > On 2/17/2024 7:43 PM, Krzysztof Kozlowski wrote: >> On 16/02/2024 11:39, Jishnu Prakash wrote: >>> Hi Krzysztof, >>> >>> On 1/4/2024 1:48 PM, Krzysztof Kozlowski wrote: >>>> On 31/12/2023 18:12, Jishnu Prakash wrote: >>>>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the >>>>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. >>>>> >>>>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs >>>>> going through PBS(Programmable Boot Sequence) firmware through a single >>>>> register interface. This interface is implemented on an SDAM (Shared >>>>> Direct Access Memory) peripheral on the master PMIC PMK8550 rather >>>>> than a dedicated ADC peripheral. >>>>> >>>>> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC >>>>> channels and virtual channels (combination of ADC channel number and >>>>> PMIC SID number) per PMIC, to be used by clients of this device. >>>>> >>>>> Changes since v2: >>>>> - Moved ADC5 Gen3 documentation into a separate new file. >>>> Changelog goes under ---. >>>> >>>> Why did you do this? What is the rationale? Sorry, this patchset goes >>>> nowhere. >>> >>> >>> I'll elaborate this more in the next patchset. There are two main >>> reasons for adding this documentation in a new file: >> >> This was more than a month ago? You reply to my comment with 1.5 months >> delay? >> >> Sorry, I am not in the context and I am not going back to it. I have >> many other emails where my questions are addressed faster than 1.5 months. >> >> The patch is not even in my mailbox, long gone. >> Why you are making it so difficult for reviewers? >> >> You will get answers like I am not in context, sorry. Next time don't >> respond after 1.5 months. >> > > You're right - I'll do my best to get back to review comments in a > reasonable time frame. > >> >>> >>> 1.This device is not exactly like the existing QCOM VADC drivers as it >>> now combines VADC functionality (reading ADC channel on client request) >>> with ADC_TM functionality (thermal threshold monitoring). >> >> Does no explain touching bindings. Your drivers don't matter for bindings. >> >>> >>> 2.Adding this device's bindings in the existing qcom,spmi-vadc.yaml file >> >> No rationale was provided in commit msg. >> >>> is not possible as it would require updating some of the existing >>> top-level constraints. (for the older devices in that file, "reg" and >>> "interrupts" can have at most one item, while this device can have more >>> than one item under these properties.) >> > >> How is this a problem? > > In qcom,spmi-vadc.yaml, we have the following top-level constraints for > the "reg" and "interrupts" properties: > > reg: > maxItems: 1 > > interrupts: > maxItems: 1 > > For the ADC5 Gen3 device being added now, these constraints cannot be > followed always, as there may be more than one peripheral under one > device instance, each with a corresponding interrupt. For example, the > above properties could be like this for a ADC5 Gen3 device: > > reg = <0x9000>, <0x9100>; > interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, > <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; > > > I could not overwrite the top-level constraints for the new device > "qcom,spmi-adc5-gen3" alone in qcom,spmi-vadc.yaml, so I tried to remove > the constraints from the top level and add them back conditionally for > all the device types separately, but you told me not to remove them > (full message: > https://lore.kernel.org/linux-iio/832053f4-bd5d-4e58-81bb-1a8188e7f364@linaro.org/) Because top-level widest constraints must stay, but it is not a problem. Most of the multi-device bindings work like this. Dozen of Qualcomm. Why you cannot do this the same way we do for all Qualcomm devices? > > Since these constraints cannot be modified for a specific new device or ??? > removed, I think the only way to accommodate this new device is to add > it in its own new file. > > Is this a sufficient justification for adding this documentation in a > new file or do you have any other suggestions? I already gave you the suggestions and you ignored them. Do like we are doing for all other drivers. Don't re-invent stuff. Either this fits to existing schema or come with common schema (and then provide rationale why it does not fit to existing one). Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml new file mode 100644 index 000000000000..ed5bb53e7628 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml @@ -0,0 +1,212 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC ADC5 Gen3 + +maintainers: + - Jishnu Prakash <quic_jprakash@quicinc.com> + +description: | + SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to + clients to read voltage. It is a 16-bit sigma-delta ADC. + It also performs the same thermal monitoring function as + the existing ADC_TM devices. + +properties: + compatible: + const: qcom,spmi-adc5-gen3 + + reg: + description: | + - Each reg corresponds to an SDAM peripheral base address that is being used for ADC. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + "#thermal-sensor-cells": + const: 1 + description: + Number of cells required to uniquely identify the thermal sensors. Since + we have multiple sensors this is set to 1. This property is required for + ADC devices with channels used for TM (thermal monitoring) functionality. + + '#io-channel-cells': + const: 1 + + interrupts: + description: | + End of conversion interrupt. Interrupts are defined for each SDAM being used. + + interrupt-names: + minItems: 1 + maxItems: 10 + items: + pattern: "^adc-sdam[0-9]+$" + description: | + Names should be defined as "adc-sdam<N>" where <N> represents the SDAM index. + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - '#io-channel-cells' + - interrupts + - interrupt-names + +patternProperties: + "^channel@[0-9a-f]+$": + type: object + additionalProperties: false + description: | + Represents the external channels which are connected to the ADC. + + properties: + reg: + maxItems: 1 + description: | + ADC channel number. + See include/dt-bindings/iio/adc/qcom,spmi-vadc.h + For PMIC5 Gen3 ADC, the channel numbers are specified separately + per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc. + + label: + $ref: /schemas/types.yaml#/definitions/string + description: | + ADC input of the platform as seen in the schematics. + For thermistor inputs connected to generic AMUX or GPIO inputs + these can vary across platform for the same pins. Hence select + the platform schematics name for this channel. + + qcom,decimation: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + This parameter is used to decrease ADC sampling rate. + Quicker measurements can be made by reducing decimation ratio. + enum: [ 85, 340, 1360 ] + default: 1360 + + qcom,pre-scaling: + description: | + Used for scaling the channel input signal before the signal is + fed to VADC. The configuration for this node is to know the + pre-determined ratio and use it for post scaling. It is a pair of + integers, denoting the numerator and denominator of the fraction by which + input signal is multiplied. For example, <1 3> indicates the signal is scaled + down to 1/3 of its value before ADC measurement. + If property is not found default value depending on chip will be used. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - const: 1 + - enum: [ 1, 3, 6, 16 ] + + qcom,ratiometric: + description: | + Channel calibration type. + - If this property is specified VADC will use the VDD reference (1.875V) + and GND for channel calibration. If property is not found, channel will be + calibrated with 0V and 1.25V reference channels, also known as + absolute calibration. + type: boolean + + qcom,hw-settle-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Time between AMUX getting configured and the ADC starting + conversion. The 'hw_settle_time' is an index used from valid values + and programmed in hardware to achieve the hardware settling delay. + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, + 8000, 16000, 32000, 64000, 128000 ] + default: 15 + + qcom,avg-samples: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Number of samples to be used for measurement. + Averaging provides the option to obtain a single measurement + from the ADC that is an average of multiple samples. The value + selected is 2^(value). + enum: [ 1, 2, 4, 8, 16 ] + default: 1 + + qcom,adc-tm: + description: | + Indicates if ADC_TM monitoring is done on this channel. + Defined for compatible property "qcom,spmi-adc5-gen3". + This is the same functionality as in the existing QCOM ADC_TM + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml. + type: boolean + + required: + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h> + #include <dt-bindings/interrupt-controller/irq.h> + + pmic { + #address-cells = <1>; + #size-cells = <0>; + + /* VADC node */ + pmk8550_vadc: vadc@9000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x9000>, <0x9100>; + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "adc-sdam0", "adc-sdam1"; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + #thermal-sensor-cells = <1>; + + /* PMK8550 Channel nodes */ + channel@3 { + reg = <PMK8550_ADC5_GEN3_DIE_TEMP>; + label = "pmk8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@44 { + reg = <PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>; + label = "pmk8550_xo_therm"; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,adc-tm; + }; + + /* PM8550 Channel nodes */ + channel@103 { + reg = <PM8550_ADC5_GEN3_DIE_TEMP>; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@78f { + reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>; + label = "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg = <PM8550VS_ADC5_GEN3_DIE_TEMP(2)>; + label = "pm8550vs_c_die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + }; diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h new file mode 100644 index 000000000000..0f25ef87ed5c --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H + +#ifndef PM8550_SID +#define PM8550_SID 1 +#endif + +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> + +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */ +#define PM8550_ADC5_GEN3_REF_GND (PM8550_SID << 8 | ADC5_GEN3_REF_GND) +#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | ADC5_GEN3_1P25VREF) +#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | ADC5_GEN3_VREF_VADC) +#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | ADC5_GEN3_DIE_TEMP) + +#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | ADC5_GEN3_AMUX1_THM) +#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | ADC5_GEN3_AMUX2_THM) +#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_THM) +#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_THM) +#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | ADC5_GEN3_AMUX5_THM) +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | ADC5_GEN3_AMUX6_THM) +#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO) +#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | ADC5_GEN3_AMUX2_GPIO) +#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO) + +/* 100k pull-up */ +#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) +#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU) +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU) + +/* 1/3 Divider */ +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO_DIV3) + +#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | ADC5_GEN3_VPH_PWR) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h new file mode 100644 index 000000000000..47116bbe45de --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H + +#ifndef PM8550B_SID +#define PM8550B_SID 7 +#endif + +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> + +/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */ +#define PM8550B_ADC5_GEN3_REF_GND (PM8550B_SID << 8 | ADC5_GEN3_REF_GND) +#define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | ADC5_GEN3_1P25VREF) +#define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | ADC5_GEN3_VREF_VADC) +#define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | ADC5_GEN3_DIE_TEMP) + +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO) + +#define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | ADC5_GEN3_CHG_TEMP) +#define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | ADC5_GEN3_USB_SNS_V_16) +#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | ADC5_GEN3_VIN_DIV16_MUX) +#define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | ADC5_GEN3_VREF_BAT_THERM) +#define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | ADC5_GEN3_IIN_FB) +#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | ADC5_GEN3_TEMP_ALARM_LITE) +#define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | ADC5_GEN3_IIN_SMB) +#define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | ADC5_GEN3_ICHG_SMB) +#define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | ADC5_GEN3_ICHG_FB) + +/* 30k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_30K_PU) + +/* 100k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU) + +/* 400k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_400K_PU) + +/* 1/3 Divider */ +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_DIV3) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_DIV3) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3) + +#define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | ADC5_GEN3_VPH_PWR) +#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | ADC5_GEN3_VBAT_SNS_QBG) +#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | ADC5_GEN3_VBAT_SNS_CHGR) +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | ADC5_GEN3_VBAT_2S_MID_QBG) +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | ADC5_GEN3_VBAT_2S_MID_CHGR) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h new file mode 100644 index 000000000000..360f2245d582 --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H + +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> + +/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */ +#define PM8550VS_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) +#define PM8550VS_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) +#define PM8550VS_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC) +#define PM8550VS_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) + +#define PM8550VE_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) +#define PM8550VE_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) +#define PM8550VE_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC) +#define PM8550VE_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h new file mode 100644 index 000000000000..3fc829ebdf6d --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H + +#ifndef PMK8550_SID +#define PMK8550_SID 0 +#endif + +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> + +/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */ +#define PMK8550_ADC5_GEN3_REF_GND (PMK8550_SID << 8 | ADC5_GEN3_REF_GND) +#define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | ADC5_GEN3_1P25VREF) +#define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | ADC5_GEN3_VREF_VADC) +#define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | ADC5_GEN3_DIE_TEMP) + +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO) + +/* 30k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_30K_PU) + +/* 100k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) + +/* 400k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_400K_PU) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h index fdb8dd9ae541..812f33872e5e 100644 --- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h @@ -10,7 +10,7 @@ #define PMR735B_SID 5 #endif -#include <dt-bindings/iio/qcom,spmi-vadc.h> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> /* ADC channels for PMR735B_ADC for PMIC7 */ #define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | ADC7_REF_GND) diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h index c0680d1285cf..750a526af2c1 100644 --- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h @@ -6,7 +6,7 @@ #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H #define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H -#include <dt-bindings/iio/qcom,spmi-vadc.h> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> #define SMB139x_1_ADC7_SMB_TEMP (SMB139x_1_SID << 8 | ADC7_SMB_TEMP) #define SMB139x_1_ADC7_ICHG_SMB (SMB139x_1_SID << 8 | ADC7_ICHG_SMB) diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h index ef07ecd4d585..cfe653d945a4 100644 --- a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h +++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. + * + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H @@ -300,4 +302,83 @@ #define ADC7_SBUx 0x94 #define ADC7_VBAT_2S_MID 0x96 +/* ADC channels for PMIC5 Gen3 */ + +#define ADC5_GEN3_REF_GND 0x00 +#define ADC5_GEN3_1P25VREF 0x01 +#define ADC5_GEN3_VREF_VADC 0x02 +#define ADC5_GEN3_DIE_TEMP 0x03 + +#define ADC5_GEN3_AMUX1_THM 0x04 +#define ADC5_GEN3_AMUX2_THM 0x05 +#define ADC5_GEN3_AMUX3_THM 0x06 +#define ADC5_GEN3_AMUX4_THM 0x07 +#define ADC5_GEN3_AMUX5_THM 0x08 +#define ADC5_GEN3_AMUX6_THM 0x09 +#define ADC5_GEN3_AMUX1_GPIO 0x0a +#define ADC5_GEN3_AMUX2_GPIO 0x0b +#define ADC5_GEN3_AMUX3_GPIO 0x0c +#define ADC5_GEN3_AMUX4_GPIO 0x0d + +#define ADC5_GEN3_CHG_TEMP 0x10 +#define ADC5_GEN3_USB_SNS_V_16 0x11 +#define ADC5_GEN3_VIN_DIV16_MUX 0x12 +#define ADC5_GEN3_VREF_BAT_THERM 0x15 +#define ADC5_GEN3_IIN_FB 0x17 +#define ADC5_GEN3_TEMP_ALARM_LITE 0x18 +#define ADC5_GEN3_IIN_SMB 0x19 +#define ADC5_GEN3_ICHG_SMB 0x1b +#define ADC5_GEN3_ICHG_FB 0xa1 + +/* 30k pull-up1 */ +#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24 +#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25 +#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26 +#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27 +#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28 +#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29 +#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a +#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b +#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c +#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d + +/* 100k pull-up2 */ +#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44 +#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45 +#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46 +#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47 +#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48 +#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49 +#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a +#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b +#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c +#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d + +/* 400k pull-up3 */ +#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64 +#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65 +#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66 +#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67 +#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68 +#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69 +#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a +#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b +#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c +#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d + +/* 1/3 Divider */ +#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a +#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b +#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c +#define ADC5_GEN3_AMUX4_GPIO_DIV3 0x8d + +#define ADC5_GEN3_VPH_PWR 0x8e +#define ADC5_GEN3_VBAT_SNS_QBG 0x8f + +#define ADC5_GEN3_VBAT_SNS_CHGR 0x94 +#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96 +#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d + +#define ADC5_GEN3_OFFSET_EXT2 0xf8 + #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */