| Message ID | 20231228125805.661725-1-tudor.ambarus@linaro.org |
|---|---|
| Headers | show |
| Series | GS101 Oriole: CMU_PERIC0 support and USI updates | expand |
On 12/28/23 14:04, André Draszik wrote: > Hi Tudor, Hi! > > On Thu, 2023-12-28 at 12:58 +0000, Tudor Ambarus wrote: >> [...] >> >> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi >> index 0e5b1b490b0b..c6ae33016992 100644 >> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi >> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi >> @@ -354,6 +354,35 @@ pinctrl_peric0: pinctrl@10840000 { >> interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; >> }; >> >> + usi8: usi@109700c0 { >> + compatible = "google,gs101-usi", >> + "samsung,exynos850-usi"; >> + reg = <0x109700c0 0x20>; >> + ranges; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, >> + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; >> + clock-names = "pclk", "ipclk"; > > Given the clock-names, shouldn't the clock indices be the other way around? Also see below. You're right, they should have been the other way around! Didn't make any difference at testing because the usi driver uses clk_bulk_prepare_enable(), what matters is the order of clocks in the i2c node, and those are fine. > >> + samsung,sysreg = <&sysreg_peric0 0x101c>; >> + status = "disabled"; >> + >> + hsi2c_8: i2c@10970000 { >> + compatible = "google,gs101-hsi2c", >> + "samsung,exynosautov9-hsi2c"; >> + reg = <0x10970000 0xc0>; >> + interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&hsi2c8_bus>; >> + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, >> + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; >> + clock-names = "hsi2c", "hsi2c_pclk"; > > Here, pclk == CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK (which is correct, I believe), whereas > above pclk == CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 > Indeed, I'll reverse the order for the USI clocks and do some more testing. Thanks! ta
On 12/29/23 08:04, Tudor Ambarus wrote: > > > On 12/28/23 14:04, André Draszik wrote: >> Hi Tudor, > > Hi! > >> >> On Thu, 2023-12-28 at 12:58 +0000, Tudor Ambarus wrote: >>> [...] >>> >>> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi >>> index 0e5b1b490b0b..c6ae33016992 100644 >>> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi >>> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi >>> @@ -354,6 +354,35 @@ pinctrl_peric0: pinctrl@10840000 { >>> interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; >>> }; >>> >>> + usi8: usi@109700c0 { >>> + compatible = "google,gs101-usi", >>> + "samsung,exynos850-usi"; >>> + reg = <0x109700c0 0x20>; >>> + ranges; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, >>> + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; >>> + clock-names = "pclk", "ipclk"; >> >> Given the clock-names, shouldn't the clock indices be the other way around? Also see below. > > You're right, they should have been the other way around! Didn't make > any difference at testing because the usi driver uses > clk_bulk_prepare_enable(), what matters is the order of clocks in the > i2c node, and those are fine. > >> >>> + samsung,sysreg = <&sysreg_peric0 0x101c>; >>> + status = "disabled"; >>> + >>> + hsi2c_8: i2c@10970000 { >>> + compatible = "google,gs101-hsi2c", >>> + "samsung,exynosautov9-hsi2c"; >>> + reg = <0x10970000 0xc0>; >>> + interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&hsi2c8_bus>; >>> + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, >>> + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; >>> + clock-names = "hsi2c", "hsi2c_pclk"; >> >> Here, pclk == CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK (which is correct, I believe), whereas >> above pclk == CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 >> > > Indeed, I'll reverse the order for the USI clocks and do some more > testing. Thanks! FYI, I reversed the order of the USI clocks, tested again with the eeprom at 100 KHz and 10KHz, everything went fine. I'll wait for some other feedback and probably submit a v3 next week. Cheers, ta
On Thu, Dec 28, 2023 at 12:57:57PM +0000, Tudor Ambarus wrote: > GS101's Connectivity Peripheral blocks (peric0/1 blocks) which > include the I3C and USI (I2C, SPI, UART) only allow 32-bit > register accesses. If using 8-bit register accesses, a SError > Interrupt is raised causing the system unusable. > > Instead of specifying the reg-io-width = 4 everywhere, for each node, > the requirement should be deduced from the compatible. > > Prepare the samsung tty driver to allow IO types different than > UPIO_MEM. ``struct uart_port::iotype`` is an unsigned char where all > its 8 bits are exposed to uapi. We can't make NULL checks on it to > verify if it's set, thus always set it from the driver's data. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > --- > v2: new patch > > drivers/tty/serial/samsung_tty.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c > index 66bd6c090ace..97ce4b2424af 100644 > --- a/drivers/tty/serial/samsung_tty.c > +++ b/drivers/tty/serial/samsung_tty.c > @@ -72,6 +72,7 @@ struct s3c24xx_uart_info { > const char *name; > enum s3c24xx_port_type type; > unsigned int port_type; > + unsigned char iotype; > unsigned int fifosize; > unsigned long rx_fifomask; > unsigned long rx_fifoshift; Is there a reason you are trying to add unused memory spaces to this structure for no valid reason? I don't think you could have picked a more incorrect place in there to add this :) Please fix. thanks, greg k-h
On 1/4/24 15:32, Greg KH wrote: > On Thu, Dec 28, 2023 at 12:57:57PM +0000, Tudor Ambarus wrote: >> GS101's Connectivity Peripheral blocks (peric0/1 blocks) which >> include the I3C and USI (I2C, SPI, UART) only allow 32-bit >> register accesses. If using 8-bit register accesses, a SError >> Interrupt is raised causing the system unusable. >> >> Instead of specifying the reg-io-width = 4 everywhere, for each node, >> the requirement should be deduced from the compatible. >> >> Prepare the samsung tty driver to allow IO types different than >> UPIO_MEM. ``struct uart_port::iotype`` is an unsigned char where all >> its 8 bits are exposed to uapi. We can't make NULL checks on it to >> verify if it's set, thus always set it from the driver's data. >> >> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> >> --- >> v2: new patch >> >> drivers/tty/serial/samsung_tty.c | 9 ++++++++- >> 1 file changed, 8 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c >> index 66bd6c090ace..97ce4b2424af 100644 >> --- a/drivers/tty/serial/samsung_tty.c >> +++ b/drivers/tty/serial/samsung_tty.c >> @@ -72,6 +72,7 @@ struct s3c24xx_uart_info { >> const char *name; >> enum s3c24xx_port_type type; >> unsigned int port_type; >> + unsigned char iotype; >> unsigned int fifosize; >> unsigned long rx_fifomask; >> unsigned long rx_fifoshift; > > Is there a reason you are trying to add unused memory spaces to this > structure for no valid reason? I don't think you could have picked a > more incorrect place in there to add this :) > > Please fix. > Will put it after "const char *name". Thanks, ta
On Thu, Jan 04, 2024 at 03:41:28PM +0000, Tudor Ambarus wrote: > > > On 1/4/24 15:32, Greg KH wrote: > > On Thu, Dec 28, 2023 at 12:57:57PM +0000, Tudor Ambarus wrote: > >> GS101's Connectivity Peripheral blocks (peric0/1 blocks) which > >> include the I3C and USI (I2C, SPI, UART) only allow 32-bit > >> register accesses. If using 8-bit register accesses, a SError > >> Interrupt is raised causing the system unusable. > >> > >> Instead of specifying the reg-io-width = 4 everywhere, for each node, > >> the requirement should be deduced from the compatible. > >> > >> Prepare the samsung tty driver to allow IO types different than > >> UPIO_MEM. ``struct uart_port::iotype`` is an unsigned char where all > >> its 8 bits are exposed to uapi. We can't make NULL checks on it to > >> verify if it's set, thus always set it from the driver's data. > >> > >> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > >> --- > >> v2: new patch > >> > >> drivers/tty/serial/samsung_tty.c | 9 ++++++++- > >> 1 file changed, 8 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c > >> index 66bd6c090ace..97ce4b2424af 100644 > >> --- a/drivers/tty/serial/samsung_tty.c > >> +++ b/drivers/tty/serial/samsung_tty.c > >> @@ -72,6 +72,7 @@ struct s3c24xx_uart_info { > >> const char *name; > >> enum s3c24xx_port_type type; > >> unsigned int port_type; > >> + unsigned char iotype; > >> unsigned int fifosize; > >> unsigned long rx_fifomask; > >> unsigned long rx_fifoshift; > > > > Is there a reason you are trying to add unused memory spaces to this > > structure for no valid reason? I don't think you could have picked a > > more incorrect place in there to add this :) > > > > Please fix. > > > > Will put it after "const char *name". If you do, spend some time with the tool, pahole, and see if that's really the best place for it or not. Might be, might not be, but you should verify it please. thanks, greg k-h
On 1/4/24 15:56, Greg KH wrote: > On Thu, Jan 04, 2024 at 03:41:28PM +0000, Tudor Ambarus wrote: >> >> >> On 1/4/24 15:32, Greg KH wrote: >>> On Thu, Dec 28, 2023 at 12:57:57PM +0000, Tudor Ambarus wrote: >>>> GS101's Connectivity Peripheral blocks (peric0/1 blocks) which >>>> include the I3C and USI (I2C, SPI, UART) only allow 32-bit >>>> register accesses. If using 8-bit register accesses, a SError >>>> Interrupt is raised causing the system unusable. >>>> >>>> Instead of specifying the reg-io-width = 4 everywhere, for each node, >>>> the requirement should be deduced from the compatible. >>>> >>>> Prepare the samsung tty driver to allow IO types different than >>>> UPIO_MEM. ``struct uart_port::iotype`` is an unsigned char where all >>>> its 8 bits are exposed to uapi. We can't make NULL checks on it to >>>> verify if it's set, thus always set it from the driver's data. >>>> >>>> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> >>>> --- >>>> v2: new patch >>>> >>>> drivers/tty/serial/samsung_tty.c | 9 ++++++++- >>>> 1 file changed, 8 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c >>>> index 66bd6c090ace..97ce4b2424af 100644 >>>> --- a/drivers/tty/serial/samsung_tty.c >>>> +++ b/drivers/tty/serial/samsung_tty.c >>>> @@ -72,6 +72,7 @@ struct s3c24xx_uart_info { >>>> const char *name; >>>> enum s3c24xx_port_type type; >>>> unsigned int port_type; >>>> + unsigned char iotype; >>>> unsigned int fifosize; >>>> unsigned long rx_fifomask; >>>> unsigned long rx_fifoshift; >>> >>> Is there a reason you are trying to add unused memory spaces to this >>> structure for no valid reason? I don't think you could have picked a >>> more incorrect place in there to add this :) >>> >>> Please fix. >>> >> >> Will put it after "const char *name". > > If you do, spend some time with the tool, pahole, and see if that's > really the best place for it or not. Might be, might not be, but you > should verify it please. > Thanks! I played with pahole a bit. For arm32 this struct is not as bad defined as for arm64, all members fit in the same cacheline. There are some holes though and 2 cachelines for arm64 where this struct needs some love. The best and minimum invasive change for my iotype member would be to put it before the "has_divslot" member, as the has_divslot bitfield will be combined with the previous field. But I think the entire struct has to be reworked and the driver butchered a bit so that we get to a better memory footprint and a single cacheline. I volunteer to do this in a separate patch set so that we don't block this series. I think the final struct can look as following: struct s3c24xx_uart_info { const char * name; /* 0 8 */ enum s3c24xx_port_type type; /* 8 4 */ unsigned int port_type; /* 12 4 */ unsigned int fifosize; /* 16 4 */ u32 rx_fifomask; /* 20 4 */ u32 rx_fifoshift; /* 24 4 */ u32 rx_fifofull; /* 28 4 */ u32 tx_fifomask; /* 32 4 */ u32 tx_fifoshift; /* 36 4 */ u32 tx_fifofull; /* 40 4 */ u32 clksel_mask; /* 44 4 */ u32 clksel_shift; /* 48 4 */ u32 ucon_mask; /* 52 4 */ u8 def_clk_sel; /* 56 1 */ u8 num_clks; /* 57 1 */ u8 iotype; /* 58 1 */ u8 has_divslot:1; /* 59: 0 1 */ /* size: 64, cachelines: 1, members: 17 */ /* padding: 4 */ /* bit_padding: 7 bits */ }; This looks a lot better than what we have now: /* size: 120, cachelines: 2, members: 17 */ /* sum members: 105, holes: 2, sum holes: 8 */ /* sum bitfield members: 1 bits (0 bytes) */ /* padding: 4 */ /* bit_padding: 23 bits */ /* last cacheline: 56 bytes */ I'll put iotype before has_divslot and then follow up with a patch set to clean the driver. Cheers, ta
Hi Tudor, On Thu, 28 Dec 2023 at 12:58, Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > Add google,gs101-hsi2c dedicated compatible for representing > I2C of Google GS101 SoC. > > Acked-by: Wolfram Sang <wsa@kernel.org> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Hi Tudor, On Thu, 28 Dec 2023 at 12:58, Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > GS101's Connectivity Peripheral blocks (peric0/1 blocks) which > include the I3C and USI (I2C, SPI, UART) only allow 32-bit > register accesses. > > Instead of specifying the reg-io-width = 4 everywhere, for each node, > the requirement should be deduced from the compatible. > > Infer UPIO_MEM32 iotype from the "google,gs101-uart" compatible. > Update the uart info name to be GS101 specific in order to > differentiate from the other exynos platforms. All the other settings > are not changed. > > exynos_fifoszdt_serial_drv_data was replaced by gs101_serial_drv_data > because the iotype restriction is gs101 specific and there was no other > user of exynos_fifoszdt_serial_drv_data. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Hi Tudor, On Thu, 28 Dec 2023 at 12:58, Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > CMU_PERIC0 is the clock management unit used for the peric0 block which > is used for USI and I3C. Add support for all cmu_peric0 clocks but > CLK_GOUT_PERIC0_IP (not enough info in the datasheet). > > Few clocks are marked as critical because when either of them is > disabled, the system hangs even if their clock parents are enabled. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Great to see another cmu bank being added, /sys/kernel/debug/clk/clk_summary looks good and I compile/boot tested this series Reviewed-by: Peter Griffin <peter.griffin@linaro.org> I tested this > --- > v2: > - update commit message > - identify and mark critical clocks > > drivers/clk/samsung/clk-gs101.c | 583 ++++++++++++++++++++++++++++++++ > 1 file changed, 583 insertions(+) > > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c > index 0964bb11657f..68a27b78b00b 100644 > --- a/drivers/clk/samsung/clk-gs101.c > +++ b/drivers/clk/samsung/clk-gs101.c > @@ -20,6 +20,7 @@ > #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1) > #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) > #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) > +#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) > > /* ---- CMU_TOP ------------------------------------------------------------- */ > > @@ -2478,6 +2479,585 @@ static const struct samsung_cmu_info misc_cmu_info __initconst = { > .clk_name = "dout_cmu_misc_bus", > }; > > +/* ---- CMU_PERIC0 ---------------------------------------------------------- */ > + > +/* Register Offset definitions for CMU_PERIC0 (0x10800000) */ > +#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600 > +#define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604 > +#define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610 > +#define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614 > +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620 > +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624 > +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640 > +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644 > +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650 > +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654 > +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660 > +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664 > +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670 > +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674 > +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680 > +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684 > +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690 > +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694 > +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0 > +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4 > +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0 > +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4 > +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0 > +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4 > +#define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800 > +#define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810 > +#define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800 > +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804 > +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c > +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810 > +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814 > +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820 > +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824 > +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828 > +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c > +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830 > +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834 > +#define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000 > +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004 > +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2018 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x201c > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2020 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2024 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2028 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x202c > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2030 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2034 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x2038 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x203c > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2040 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2044 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2048 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x204c > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2050 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2054 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2058 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x205c > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2060 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2064 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2068 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x206c > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2070 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2074 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x2078 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x207c > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2080 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2084 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2088 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x208c > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2090 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2094 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2098 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x209c > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x20a4 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x20a8 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x20b0 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK 0x20b8 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK 0x20bc > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20c4 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK 0x20c8 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK 0x20cc > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK 0x20d0 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK 0x20d4 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK 0x20d8 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK 0x20dc > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK 0x20e0 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK 0x20e4 > +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e8 > +#define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000 > +#define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004 > +#define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008 > +#define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c > +#define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010 > +#define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014 > +#define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018 > +#define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c > +#define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020 > +#define QCH_CON_D_TZPC_PERIC0_QCH 0x3024 > +#define QCH_CON_GPC_PERIC0_QCH 0x3028 > +#define QCH_CON_GPIO_PERIC0_QCH 0x302c > +#define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030 > +#define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034 > +#define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038 > +#define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c > +#define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040 > +#define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044 > +#define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048 > +#define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c > +#define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050 > +#define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054 > +#define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058 > +#define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c > +#define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060 > +#define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064 > +#define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068 > +#define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c > +#define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070 > +#define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074 > +#define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078 > +#define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c > +#define QCH_CON_SYSREG_PERIC0_QCH 0x3080 > +#define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00 > + > +static const unsigned long peric0_clk_regs[] __initconst = { > + PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, > + PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER, > + PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, > + PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, > + PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, > + PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, > + PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, > + PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, > + PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, > + PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, > + PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, > + PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, > + PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, > + PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER, > + PERIC0_CMU_PERIC0_CONTROLLER_OPTION, > + CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0, > + CLK_CON_DIV_DIV_CLK_PERIC0_I3C, > + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, > + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, > + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, > + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, > + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, > + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, > + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, > + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, > + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, > + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, > + CLK_CON_BUF_CLKBUF_PERIC0_IP, > + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, > + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, > + DMYQCH_CON_PERIC0_TOP0_QCH_S1, > + DMYQCH_CON_PERIC0_TOP0_QCH_S2, > + DMYQCH_CON_PERIC0_TOP0_QCH_S3, > + DMYQCH_CON_PERIC0_TOP0_QCH_S4, > + DMYQCH_CON_PERIC0_TOP0_QCH_S5, > + DMYQCH_CON_PERIC0_TOP0_QCH_S6, > + DMYQCH_CON_PERIC0_TOP0_QCH_S7, > + DMYQCH_CON_PERIC0_TOP0_QCH_S8, > + PCH_CON_LHM_AXI_P_PERIC0_PCH, > + QCH_CON_D_TZPC_PERIC0_QCH, > + QCH_CON_GPC_PERIC0_QCH, > + QCH_CON_GPIO_PERIC0_QCH, > + QCH_CON_LHM_AXI_P_PERIC0_QCH, > + QCH_CON_PERIC0_CMU_PERIC0_QCH, > + QCH_CON_PERIC0_TOP0_QCH_I3C1, > + QCH_CON_PERIC0_TOP0_QCH_I3C2, > + QCH_CON_PERIC0_TOP0_QCH_I3C3, > + QCH_CON_PERIC0_TOP0_QCH_I3C4, > + QCH_CON_PERIC0_TOP0_QCH_I3C5, > + QCH_CON_PERIC0_TOP0_QCH_I3C6, > + QCH_CON_PERIC0_TOP0_QCH_I3C7, > + QCH_CON_PERIC0_TOP0_QCH_I3C8, > + QCH_CON_PERIC0_TOP0_QCH_USI1_USI, > + QCH_CON_PERIC0_TOP0_QCH_USI2_USI, > + QCH_CON_PERIC0_TOP0_QCH_USI3_USI, > + QCH_CON_PERIC0_TOP0_QCH_USI4_USI, > + QCH_CON_PERIC0_TOP0_QCH_USI5_USI, > + QCH_CON_PERIC0_TOP0_QCH_USI6_USI, > + QCH_CON_PERIC0_TOP0_QCH_USI7_USI, > + QCH_CON_PERIC0_TOP0_QCH_USI8_USI, > + QCH_CON_PERIC0_TOP1_QCH_USI0_UART, > + QCH_CON_PERIC0_TOP1_QCH_USI14_UART, > + QCH_CON_SYSREG_PERIC0_QCH, > + QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0, > +}; > + > +/* List of parent clocks for Muxes in CMU_PERIC0 */ > +PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" }; > +PNAME(mout_peric0_i3c_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; > +PNAME(mout_peric0_usi0_uart_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; > +PNAME(mout_peric0_usi_usi_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; > + > +static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { > + MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user", > + mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1), > + MUX(CLK_MOUT_PERIC0_I3C_USER, "mout_peric0_i3c_user", > + mout_peric0_i3c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 4, 1), > + MUX(CLK_MOUT_PERIC0_USI0_UART_USER, > + "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1), > + MUX(CLK_MOUT_PERIC0_USI14_USI_USER, > + "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1), > + MUX(CLK_MOUT_PERIC0_USI1_USI_USER, > + "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1), > + MUX(CLK_MOUT_PERIC0_USI2_USI_USER, > + "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1), > + MUX(CLK_MOUT_PERIC0_USI3_USI_USER, > + "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1), > + MUX(CLK_MOUT_PERIC0_USI4_USI_USER, > + "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1), > + MUX(CLK_MOUT_PERIC0_USI5_USI_USER, > + "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1), > + MUX(CLK_MOUT_PERIC0_USI6_USI_USER, > + "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1), > + MUX(CLK_MOUT_PERIC0_USI7_USI_USER, > + "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1), > + MUX(CLK_MOUT_PERIC0_USI8_USI_USER, > + "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p, > + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1), > +}; > + > +static const struct samsung_div_clock peric0_div_clks[] __initconst = { > + DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", "mout_peric0_i3c_user", > + CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 3), > + DIV(CLK_DOUT_PERIC0_USI0_UART, > + "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user", > + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 3), > + DIV(CLK_DOUT_PERIC0_USI14_USI, > + "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user", > + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 3), > + DIV(CLK_DOUT_PERIC0_USI1_USI, > + "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user", > + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 3), > + DIV(CLK_DOUT_PERIC0_USI2_USI, > + "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user", > + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 3), > + DIV(CLK_DOUT_PERIC0_USI3_USI, > + "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user", > + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 3), > + DIV(CLK_DOUT_PERIC0_USI4_USI, > + "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user", > + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 3), > + DIV(CLK_DOUT_PERIC0_USI5_USI, > + "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user", > + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 3), > + DIV(CLK_DOUT_PERIC0_USI6_USI, > + "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user", > + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 3), > + DIV(CLK_DOUT_PERIC0_USI7_USI, > + "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user", > + CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 3), > + DIV(CLK_DOUT_PERIC0_USI8_USI, > + "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user", > + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 3), > +}; > + > +static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { > + /* Disabling this clock makes the system hang. Mark the clock as critical. */ > + GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK, > + "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user", > + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, > + 21, CLK_IS_CRITICAL, 0), > + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK, > + "gout_peric0_clk_peric0_oscclk_clk", "oscclk", > + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK, > + "gout_peric0_d_tzpc_peric0_pclk", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK, > + "gout_peric0_gpc_peric0_pclk", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, > + "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, > + 21, 0, 0), > + /* Disabling this clock makes the system hang. Mark the clock as critical. */ > + GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK, > + "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, > + 21, CLK_IS_CRITICAL, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0, > + "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1, > + "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10, > + "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11, > + "gout_peric0_peric0_top0_ipclk_11", "dout_peric0_i3c", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12, > + "gout_peric0_peric0_top0_ipclk_12", "dout_peric0_i3c", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13, > + "gout_peric0_peric0_top0_ipclk_13", "dout_peric0_i3c", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14, > + "gout_peric0_peric0_top0_ipclk_14", "dout_peric0_i3c", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15, > + "gout_peric0_peric0_top0_ipclk_15", "dout_peric0_i3c", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2, > + "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3, > + "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4, > + "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5, > + "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6, > + "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7, > + "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8, > + "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9, > + "gout_peric0_peric0_top0_ipclk_9", "dout_peric0_i3c", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0, > + "gout_peric0_peric0_top0_pclk_0", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1, > + "gout_peric0_peric0_top0_pclk_1", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10, > + "gout_peric0_peric0_top0_pclk_10", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11, > + "gout_peric0_peric0_top0_pclk_11", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12, > + "gout_peric0_peric0_top0_pclk_12", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13, > + "gout_peric0_peric0_top0_pclk_13", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14, > + "gout_peric0_peric0_top0_pclk_14", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15, > + "gout_peric0_peric0_top0_pclk_15", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2, > + "gout_peric0_peric0_top0_pclk_2", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3, > + "gout_peric0_peric0_top0_pclk_3", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4, > + "gout_peric0_peric0_top0_pclk_4", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5, > + "gout_peric0_peric0_top0_pclk_5", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6, > + "gout_peric0_peric0_top0_pclk_6", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7, > + "gout_peric0_peric0_top0_pclk_7", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8, > + "gout_peric0_peric0_top0_pclk_8", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9, > + "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, > + 21, 0, 0), > + /* Disabling this clock makes the system hang. Mark the clock as critical. */ > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, > + "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, > + 21, CLK_IS_CRITICAL, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, > + "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, > + 21, 0, 0), > + /* Disabling this clock makes the system hang. Mark the clock as critical. */ > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, > + "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, > + 21, CLK_IS_CRITICAL, 0), > + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, > + "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK, > + "gout_peric0_clk_peric0_busp_clk", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK, > + "gout_peric0_clk_peric0_i3c_clk", "dout_peric0_i3c", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK, > + "gout_peric0_clk_peric0_usi0_uart_clk", "dout_peric0_usi0_uart", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK, > + "gout_peric0_clk_peric0_usi14_usi_clk", "dout_peric0_usi14_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK, > + "gout_peric0_clk_peric0_usi1_usi_clk", "dout_peric0_usi1_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK, > + "gout_peric0_clk_peric0_usi2_usi_clk", "dout_peric0_usi2_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK, > + "gout_peric0_clk_peric0_usi3_usi_clk", "dout_peric0_usi3_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK, > + "gout_peric0_clk_peric0_usi4_usi_clk", "dout_peric0_usi4_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK, > + "gout_peric0_clk_peric0_usi5_usi_clk", "dout_peric0_usi5_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK, > + "gout_peric0_clk_peric0_usi6_usi_clk", "dout_peric0_usi6_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK, > + "gout_peric0_clk_peric0_usi7_usi_clk", "dout_peric0_usi7_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK, > + "gout_peric0_clk_peric0_usi8_usi_clk", "dout_peric0_usi8_usi", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, > + 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK, > + "gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, > + 21, 0, 0), > +}; > + > +static const struct samsung_cmu_info peric0_cmu_info __initconst = { > + .mux_clks = peric0_mux_clks, > + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), > + .div_clks = peric0_div_clks, > + .nr_div_clks = ARRAY_SIZE(peric0_div_clks), > + .gate_clks = peric0_gate_clks, > + .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), > + .nr_clk_ids = CLKS_NR_PERIC0, > + .clk_regs = peric0_clk_regs, > + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), > + .clk_name = "dout_cmu_peric0_bus", > +}; > + > /* ---- platform_driver ----------------------------------------------------- */ > > static int __init gs101_cmu_probe(struct platform_device *pdev) > @@ -2498,6 +3078,9 @@ static const struct of_device_id gs101_cmu_of_match[] = { > }, { > .compatible = "google,gs101-cmu-misc", > .data = &misc_cmu_info, > + }, { > + .compatible = "google,gs101-cmu-peric0", > + .data = &peric0_cmu_info, > }, { > }, > }; > -- > 2.43.0.472.g3155946c3a-goog >
Hi Tudor, On Thu, 28 Dec 2023 at 12:58, Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > Enable the cmu-peric0 clock controller. It feeds USI and I3c. > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Add support for PERIC0 clocks. Use them for USI in serial and I2C configurations. Tested the serial at different baudrates (115200, 1M, 3M) and the I2C with an at24 eeprom, all went fine. Apart of the DT and defconfig changes, the patch set spans through the tty and clk subsystems. The expectation is that Krzysztof will apply the whole series through the Samsung SoC tree. If the tty and clk subsystem maintainers can give an acked-by or reviewed-by on the relevant patches that would be most appreciated! Thanks! ta changes in v2: - gs101 serial - infer the reg-io-width from the compatible as the entire PERIC block allows just 32-bit register accesses. - identify the critical clocks from PERIC0 and mark them accordingly (if disabled these clocks hang the system even if their parents are still enabled). - update dtsi and use USI's gate clocks instead of the dividers clocks - move hsi2c_8 cells and pinctrls into dtsi - address Sam's cosmetic changes in the device tree files - drop defconfig patches (savedefconfig output & at24 eeprom enablement) - collect Acked-by and Reviewed-by tags - changes log in each patch as well, in the comments section under ```---``` Tudor Ambarus (12): dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit dt-bindings: i2c: exynos5: add google,gs101-hsi2c compatible dt-bindings: serial: samsung: do not allow reg-io-width for gs101 tty: serial: samsung: prepare for different IO types tty: serial: samsung: set UPIO_MEM32 iotype for gs101 tty: serial: samsung: add gs101 earlycon support clk: samsung: gs101: add support for cmu_peric0 arm64: dts: exynos: gs101: remove reg-io-width from serial arm64: dts: exynos: gs101: enable cmu-peric0 clock controller arm64: dts: exynos: gs101: update USI UART to use peric0 clocks arm64: dts: exynos: gs101: define USI8 with I2C configuration arm64: dts: exynos: gs101: enable eeprom on gs101-oriole .../bindings/clock/google,gs101-clock.yaml | 25 +- .../devicetree/bindings/i2c/i2c-exynos5.yaml | 1 + .../bindings/serial/samsung_uart.yaml | 2 + .../boot/dts/exynos/google/gs101-oriole.dts | 14 + arch/arm64/boot/dts/exynos/google/gs101.dtsi | 56 +- drivers/clk/samsung/clk-gs101.c | 583 ++++++++++++++++++ drivers/tty/serial/samsung_tty.c | 58 +- include/dt-bindings/clock/google,gs101.h | 81 +++ 8 files changed, 796 insertions(+), 24 deletions(-)