Message ID | 20240212165043.26961-5-johan+linaro@kernel.org |
---|---|
State | Superseded |
Headers | show |
Series | arm64: dts: qcom: sc8280xp: enable GICv3 ITS for PCIe | expand |
On Thu, Feb 15, 2024 at 09:47:01PM +0100, Konrad Dybcio wrote: > On 12.02.2024 17:50, Johan Hovold wrote: > > Limit the WiFi PCIe link speed to Gen2 speed (500 GB/s), which is the > > MB/s Indeed, thanks for spotting that. > > speed that Windows uses. > > > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> > > --- > > Hm.. I'dve assumed it ships with a WLAN card that supports moving > more bandwidth.. Is it always at gen2? I don't know how the Windows driver works, but the UEFI firmware has brought the link up at Gen2 and that's also what Windows reported when I checked. But I was not actually using the wifi when I did so. But yes, it seems we may be limiting the theoretical maximum data rate for the wifi this way. As this appears to fix wifi startup issue reported by one user, and allows us to enable ITS and AER reporting, perhaps that's acceptable until the Linux driver can manage to scale the link speed (or we figure out a more elaborate way of restarting the link at boot). The PCIe link errors could also indicate that the wifi can not be run any faster than this on these machines even if my guess is something is wrong with ASPM implementation. Hopefully Qualcomm will be able to shed some light on that. Johan
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index f34c572253f5..8c1fccf8847a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -563,6 +563,8 @@ &pcie3a_phy { }; &pcie4 { + max-link-speed = <2>; + perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
Limit the WiFi PCIe link speed to Gen2 speed (500 GB/s), which is the speed that Windows uses. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 2 ++ 1 file changed, 2 insertions(+)