| Message ID | 20240203165307.7806-10-aford173@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | soc: imx8mp: Add support for HDMI | expand |
Hi all, Am Samstag, 3. Februar 2024, 17:52:49 CET schrieb Adam Ford: > From: Lucas Stach <l.stach@pengutronix.de> > > The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP > core with a little bit of SoC integration around it. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Signed-off-by: Adam Ford <aford173@gmail.com> > > --- > V3: Change name and location to better idenfity as a bridge and > HDMI 2.0a transmitter > > Fix typos and feedback from Rob and added ports. > --- > .../display/bridge/fsl,imx8mp-hdmi-tx.yaml | 102 ++++++++++++++++++ > 1 file changed, 102 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml > > diff --git > a/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml > b/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml > new file mode 100644 > index 000000000000..3791c9f4ebab > --- /dev/null > +++ > b/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml > @@ -0,0 +1,102 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8MP DWC HDMI TX Encoder > + > +maintainers: > + - Lucas Stach <l.stach@pengutronix.de> > + > +description: > + The i.MX8MP HDMI transmitter is a Synopsys DesignWare > + HDMI 2.0a TX controller IP. > + > +allOf: > + - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# > + > +properties: > + compatible: > + enum: > + - fsl,imx8mp-hdmi-tx > + > + reg-io-width: > + const: 1 > + > + clocks: > + maxItems: 4 > + > + clock-names: > + items: > + - const: iahb > + - const: isfr > + - const: cec > + - const: pix > + > + power-domains: > + maxItems: 1 > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: Parallel RGB input port > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: HDMI output port > + > + required: > + - port@0 > + - port@1 Is this really correct that port@1 is required? AFAICS this host already supports HPD and DDC by itself, so there is no need for a dedicated HDMI connector. With the current state of the drivers this output port is completely ignored anyway. Yet it works for a lot of people. Best regards, Alexander > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - power-domains > + - ports > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/imx8mp-clock.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/power/imx8mp-power.h> > + > + hdmi@32fd8000 { > + compatible = "fsl,imx8mp-hdmi-tx"; > + reg = <0x32fd8000 0x7eff>; > + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MP_CLK_HDMI_APB>, > + <&clk IMX8MP_CLK_HDMI_REF_266M>, > + <&clk IMX8MP_CLK_32K>, > + <&hdmi_tx_phy>; > + clock-names = "iahb", "isfr", "cec", "pix"; > + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; > + reg-io-width = <1>; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + > + hdmi_tx_from_pvi: endpoint { > + remote-endpoint = <&pvi_to_hdmi_tx>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + hdmi_tx_out: endpoint { > + remote-endpoint = <&hdmi0_con>; > + }; > + }; > + }; > + };
On Fri, Feb 16, 2024 at 10:05:26AM +0100, Alexander Stein wrote: > Hi all, > > Am Samstag, 3. Februar 2024, 17:52:49 CET schrieb Adam Ford: > > From: Lucas Stach <l.stach@pengutronix.de> > > > > The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP > > core with a little bit of SoC integration around it. > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > Signed-off-by: Adam Ford <aford173@gmail.com> > > > > --- > > V3: Change name and location to better idenfity as a bridge and > > HDMI 2.0a transmitter > > > > Fix typos and feedback from Rob and added ports. > > --- > > .../display/bridge/fsl,imx8mp-hdmi-tx.yaml | 102 ++++++++++++++++++ > > 1 file changed, 102 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml > > b/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml > > new file mode 100644 > > index 000000000000..3791c9f4ebab > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml > > @@ -0,0 +1,102 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Freescale i.MX8MP DWC HDMI TX Encoder > > + > > +maintainers: > > + - Lucas Stach <l.stach@pengutronix.de> > > + > > +description: > > + The i.MX8MP HDMI transmitter is a Synopsys DesignWare > > + HDMI 2.0a TX controller IP. > > + > > +allOf: > > + - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# > > + > > +properties: > > + compatible: > > + enum: > > + - fsl,imx8mp-hdmi-tx > > + > > + reg-io-width: > > + const: 1 > > + > > + clocks: > > + maxItems: 4 > > + > > + clock-names: > > + items: > > + - const: iahb > > + - const: isfr > > + - const: cec > > + - const: pix > > + > > + power-domains: > > + maxItems: 1 > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: Parallel RGB input port > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: HDMI output port > > + > > + required: > > + - port@0 > > + - port@1 > > Is this really correct that port@1 is required? AFAICS this host already > supports HPD and DDC by itself, so there is no need for a dedicated HDMI > connector. The chip has an HDMI output, so there's an output port. > With the current state of the drivers this output port is completely ignored > anyway. Yet it works for a lot of people. DT bindings describe the hardware. From a DT point of view, tt's fine for drivers to ignore the port (that may or may not be true from a DRM point of view, but that's a separate discussion). > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > + - interrupts > > + - power-domains > > + - ports > > + > > +unevaluatedProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/imx8mp-clock.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/power/imx8mp-power.h> > > + > > + hdmi@32fd8000 { > > + compatible = "fsl,imx8mp-hdmi-tx"; > > + reg = <0x32fd8000 0x7eff>; > > + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&clk IMX8MP_CLK_HDMI_APB>, > > + <&clk IMX8MP_CLK_HDMI_REF_266M>, > > + <&clk IMX8MP_CLK_32K>, > > + <&hdmi_tx_phy>; > > + clock-names = "iahb", "isfr", "cec", "pix"; > > + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; > > + reg-io-width = <1>; > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + port@0 { > > + reg = <0>; > > + > > + hdmi_tx_from_pvi: endpoint { > > + remote-endpoint = <&pvi_to_hdmi_tx>; > > + }; > > + }; > > + > > + port@1 { > > + reg = <1>; > > + hdmi_tx_out: endpoint { > > + remote-endpoint = <&hdmi0_con>; > > + }; > > + }; > > + }; > > + };
On Fri, Feb 16, 2024 at 3:05 AM Alexander Stein <alexander.stein@ew.tq-group.com> wrote: > > Hi all, > > Am Samstag, 3. Februar 2024, 17:52:49 CET schrieb Adam Ford: > > From: Lucas Stach <l.stach@pengutronix.de> > > > > The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP > > core with a little bit of SoC integration around it. > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > Signed-off-by: Adam Ford <aford173@gmail.com> > > > > --- > > V3: Change name and location to better idenfity as a bridge and > > HDMI 2.0a transmitter > > > > Fix typos and feedback from Rob and added ports. > > --- > > .../display/bridge/fsl,imx8mp-hdmi-tx.yaml | 102 ++++++++++++++++++ > > 1 file changed, 102 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml > > b/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml > > new file mode 100644 > > index 000000000000..3791c9f4ebab > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml > > @@ -0,0 +1,102 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Freescale i.MX8MP DWC HDMI TX Encoder > > + > > +maintainers: > > + - Lucas Stach <l.stach@pengutronix.de> > > + > > +description: > > + The i.MX8MP HDMI transmitter is a Synopsys DesignWare > > + HDMI 2.0a TX controller IP. > > + > > +allOf: > > + - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# > > + > > +properties: > > + compatible: > > + enum: > > + - fsl,imx8mp-hdmi-tx > > + > > + reg-io-width: > > + const: 1 > > + > > + clocks: > > + maxItems: 4 > > + > > + clock-names: > > + items: > > + - const: iahb > > + - const: isfr > > + - const: cec > > + - const: pix > > + > > + power-domains: > > + maxItems: 1 > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: Parallel RGB input port > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: HDMI output port > > + > > + required: > > + - port@0 > > + - port@1 > > Is this really correct that port@1 is required? AFAICS this host already > supports HPD and DDC by itself, so there is no need for a dedicated HDMI > connector. > With the current state of the drivers this output port is completely ignored > anyway. Yet it works for a lot of people. One of the feedback responses Lucas got was that it was missing the reference to the HDMI connector, so I added it as a response to that feedback. I have tried device trees with and without it, and it doesn't impact anything, but It seems like there may be a requirement for it. adam > > Best regards, > Alexander > > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > + - interrupts > > + - power-domains > > + - ports > > + > > +unevaluatedProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/imx8mp-clock.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/power/imx8mp-power.h> > > + > > + hdmi@32fd8000 { > > + compatible = "fsl,imx8mp-hdmi-tx"; > > + reg = <0x32fd8000 0x7eff>; > > + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&clk IMX8MP_CLK_HDMI_APB>, > > + <&clk IMX8MP_CLK_HDMI_REF_266M>, > > + <&clk IMX8MP_CLK_32K>, > > + <&hdmi_tx_phy>; > > + clock-names = "iahb", "isfr", "cec", "pix"; > > + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; > > + reg-io-width = <1>; > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + port@0 { > > + reg = <0>; > > + > > + hdmi_tx_from_pvi: endpoint { > > + remote-endpoint = <&pvi_to_hdmi_tx>; > > + }; > > + }; > > + > > + port@1 { > > + reg = <1>; > > + hdmi_tx_out: endpoint { > > + remote-endpoint = <&hdmi0_con>; > > + }; > > + }; > > + }; > > + }; > > > -- > TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany > Amtsgericht München, HRB 105018 > Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider > http://www.tq-group.com/ > >
Am Freitag, 16. Februar 2024, 12:31:12 CET schrieb Adam Ford: > On Fri, Feb 16, 2024 at 3:05 AM Alexander Stein > > <alexander.stein@ew.tq-group.com> wrote: > > Hi all, > > > > Am Samstag, 3. Februar 2024, 17:52:49 CET schrieb Adam Ford: > > > From: Lucas Stach <l.stach@pengutronix.de> > > > > > > The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP > > > core with a little bit of SoC integration around it. > > > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > > Signed-off-by: Adam Ford <aford173@gmail.com> > > > > > > --- > > > V3: Change name and location to better idenfity as a bridge and > > > > > > HDMI 2.0a transmitter > > > > > > Fix typos and feedback from Rob and added ports. > > > > > > --- > > > > > > .../display/bridge/fsl,imx8mp-hdmi-tx.yaml | 102 ++++++++++++++++++ > > > 1 file changed, 102 insertions(+) > > > create mode 100644 > > > > > > Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml > > > > > > diff --git > > > a/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.ya > > > ml > > > b/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.ya > > > ml > > > new file mode 100644 > > > index 000000000000..3791c9f4ebab > > > --- /dev/null > > > +++ > > > b/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.ya > > > ml > > > @@ -0,0 +1,102 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: > > > http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Freescale i.MX8MP DWC HDMI TX Encoder > > > + > > > +maintainers: > > > + - Lucas Stach <l.stach@pengutronix.de> > > > + > > > +description: > > > + The i.MX8MP HDMI transmitter is a Synopsys DesignWare > > > + HDMI 2.0a TX controller IP. > > > + > > > +allOf: > > > + - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# > > > + > > > +properties: > > > + compatible: > > > + enum: > > > + - fsl,imx8mp-hdmi-tx > > > + > > > + reg-io-width: > > > + const: 1 > > > + > > > + clocks: > > > + maxItems: 4 > > > + > > > + clock-names: > > > + items: > > > + - const: iahb > > > + - const: isfr > > > + - const: cec > > > + - const: pix > > > + > > > + power-domains: > > > + maxItems: 1 > > > + > > > + ports: > > > + $ref: /schemas/graph.yaml#/properties/ports > > > + > > > + properties: > > > + port@0: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: Parallel RGB input port > > > + > > > + port@1: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: HDMI output port > > > + > > > + required: > > > + - port@0 > > > + - port@1 > > > > Is this really correct that port@1 is required? AFAICS this host already > > supports HPD and DDC by itself, so there is no need for a dedicated HDMI > > connector. > > With the current state of the drivers this output port is completely > > ignored anyway. Yet it works for a lot of people. > > One of the feedback responses Lucas got was that it was missing the > reference to the HDMI connector, so I added it as a response to that > feedback. I have tried device trees with and without it, and it > doesn't impact anything, but It seems like there may be a requirement > for it. Yes, I noticed as well. A specified connector is completely ignored. One reason is that dw_hdmi_plat_data.output_port is unsed in drivers/gpu/drm/ bridge/imx/imx8mp-hdmi-tx.c. Another one is that without DRM_BRIDGE_ATTACH_NO_CONNECTOR support in drivers/gpu/drm/mxsfb/lcdif_drv.c nothing changes. Best regards, Alexander > adam > > > Best regards, > > Alexander > > > > > + > > > +required: > > > + - compatible > > > + - reg > > > + - clocks > > > + - clock-names > > > + - interrupts > > > + - power-domains > > > + - ports > > > + > > > +unevaluatedProperties: false > > > + > > > +examples: > > > + - | > > > + #include <dt-bindings/clock/imx8mp-clock.h> > > > + #include <dt-bindings/interrupt-controller/irq.h> > > > + #include <dt-bindings/power/imx8mp-power.h> > > > + > > > + hdmi@32fd8000 { > > > + compatible = "fsl,imx8mp-hdmi-tx"; > > > + reg = <0x32fd8000 0x7eff>; > > > + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&clk IMX8MP_CLK_HDMI_APB>, > > > + <&clk IMX8MP_CLK_HDMI_REF_266M>, > > > + <&clk IMX8MP_CLK_32K>, > > > + <&hdmi_tx_phy>; > > > + clock-names = "iahb", "isfr", "cec", "pix"; > > > + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; > > > + reg-io-width = <1>; > > > + ports { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + port@0 { > > > + reg = <0>; > > > + > > > + hdmi_tx_from_pvi: endpoint { > > > + remote-endpoint = <&pvi_to_hdmi_tx>; > > > + }; > > > + }; > > > + > > > + port@1 { > > > + reg = <1>; > > > + hdmi_tx_out: endpoint { > > > + remote-endpoint = <&hdmi0_con>; > > > + }; > > > + }; > > > + }; > > > + }; > > > > -- > > TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany > > Amtsgericht München, HRB 105018 > > Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider > > http://www.tq-group.com/
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml new file mode 100644 index 000000000000..3791c9f4ebab --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP DWC HDMI TX Encoder + +maintainers: + - Lucas Stach <l.stach@pengutronix.de> + +description: + The i.MX8MP HDMI transmitter is a Synopsys DesignWare + HDMI 2.0a TX controller IP. + +allOf: + - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# + +properties: + compatible: + enum: + - fsl,imx8mp-hdmi-tx + + reg-io-width: + const: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: iahb + - const: isfr + - const: cec + - const: pix + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Parallel RGB input port + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI output port + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - power-domains + - ports + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mp-clock.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/imx8mp-power.h> + + hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi-tx"; + reg = <0x32fd8000 0x7eff>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_32K>, + <&hdmi_tx_phy>; + clock-names = "iahb", "isfr", "cec", "pix"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; + reg-io-width = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + hdmi_tx_from_pvi: endpoint { + remote-endpoint = <&pvi_to_hdmi_tx>; + }; + }; + + port@1 { + reg = <1>; + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + }; + };