| Message ID | 20240221103202.3628142-1-quic_kriskura@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | phy: qcom-snps: Fixed order of enabling regulators | expand |
On 2/21/2024 4:26 PM, Dmitry Baryshkov wrote: > On Wed, 21 Feb 2024 at 12:32, Krishna Kurapati > <quic_kriskura@quicinc.com> wrote: [...] >> --- >> >> Downstream kernels on QC targets use this sequence to power up >> the phy and this has been tested extensively on multiple targets. >> This change has been tested with upstream kernel on QCM6490-IDP >> without EUD to ensure there is no loss or breakage of functionality. >> >> drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c >> index eb0b0f61d98e..e86d221b7397 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c >> +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c >> @@ -79,7 +79,7 @@ >> #define LS_FS_OUTPUT_IMPEDANCE_MASK GENMASK(3, 0) >> >> static const char * const qcom_snps_hsphy_vreg_names[] = { >> - "vdda-pll", "vdda33", "vdda18", >> + "vdda-pll", "vdda18", "vdda33", > > NAK. > The driver uses regulator_bulk_enable, which enables all three > regulators simultaneously via async calls, thus your change doesn't > have any effect. > Hi Dmitry, Thanks for this information. I thought it was synchronous but you are right, I see in code they are async: async_schedule_domain(regulator_bulk_enable_async, &consumers[i], &async_domain); I think separating them out and calling regulator_enable on each one might work out. > Also note, that these regulators are frequently shared between > different consumers. As such, even if you have tight control of > regulator ordering in the driver, other drivers might enable > corresponding regulators on their own, breaking the ordering. > You are right. Let me check how the phy regulators are allocated in different femto phy targets. Thanks for the review. Regards, Krishna,
diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c index eb0b0f61d98e..e86d221b7397 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -79,7 +79,7 @@ #define LS_FS_OUTPUT_IMPEDANCE_MASK GENMASK(3, 0) static const char * const qcom_snps_hsphy_vreg_names[] = { - "vdda-pll", "vdda33", "vdda18", + "vdda-pll", "vdda18", "vdda33", }; #define SNPS_HS_NUM_VREGS ARRAY_SIZE(qcom_snps_hsphy_vreg_names)
The SNPS Femto phy has 3 supplies, vdda-pll (0.88V), vdd18 (1.8V), vdd33 (3.3V). The driver enables these in order of 0.88 -> 3.3 -> 1.88. But on phy instances which have EUD attached, it is seen that not enabling the regulators in the order of (0.88 -> 1.8V -> 3.3V) is causing the EUD to reset the phy (issue seen rarely) thereby disturbing enumeration. This change doesn't disturb operation of phy's where EUD is not present. According to the some of the applicable power-supply ramp scenarios present in data book: (DVDD is 0.88V, VDDH is 1.8V) a) VDDH<#> and VDD33<#> held to 0 V (cannot be left floating) with DVDD ramped to a valid level b) VDD33<#> held to 0 V (cannot be left floating) with DVDD and VDDH<#> ramped to their respective, valid levels Modify the driver to power up the phy regulators in order of: 0.88 -> 1.8 -> 3.3 respectively. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> --- Downstream kernels on QC targets use this sequence to power up the phy and this has been tested extensively on multiple targets. This change has been tested with upstream kernel on QCM6490-IDP without EUD to ensure there is no loss or breakage of functionality. drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)