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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm7150-dispcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller for SM7150
+
+maintainers:
+ - Danila Tikhonov <danila@jiaxyga.com>
+ - David Wronek <david@mainlining.org>
+ - Jens Reidel <adrian@travitia.xyz>
+
+description: |
+ Qualcomm display clock control module provides the clocks, resets and power
+ domains on SM7150.
+
+ See also:: include/dt-bindings/clock/qcom,sm7150-dispcc.h
+
+properties:
+ compatible:
+ const: qcom,sm7150-dispcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board Always On XO source
+ - description: GPLL0 source from GCC
+ - description: Sleep clock source
+ - description: Byte clock from MDSS DSI PHY0
+ - description: Pixel clock from MDSS DSI PHY0
+ - description: Byte clock from MDSS DSI PHY1
+ - description: Pixel clock from MDSS DSI PHY1
+ - description: Link clock from DP PHY
+ - description: VCO DIV clock from DP PHY
+
+ power-domains:
+ maxItems: 1
+ description:
+ CX power domain.
+
+required:
+ - compatible
+ - clocks
+ - power-domains
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm7150-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ clock-controller@af00000 {
+ compatible = "qcom,sm7150-dispcc";
+ reg = <0x0af00000 0x200000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ <&sleep_clk>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>,
+ <&dp_phy 0>,
+ <&dp_phy 1>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
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+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
+ * Copyright (c) 2024, David Wronek <david@mainlining.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM7150_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM7150_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_PLL0 0
+#define DISP_CC_MDSS_AHB_CLK 1
+#define DISP_CC_MDSS_AHB_CLK_SRC 2
+#define DISP_CC_MDSS_BYTE0_CLK 3
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
+#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
+#define DISP_CC_MDSS_BYTE1_CLK 7
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 8
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 9
+#define DISP_CC_MDSS_BYTE1_INTF_CLK 10
+#define DISP_CC_MDSS_DP_AUX_CLK 11
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC 12
+#define DISP_CC_MDSS_DP_CRYPTO_CLK 13
+#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 14
+#define DISP_CC_MDSS_DP_LINK_CLK 15
+#define DISP_CC_MDSS_DP_LINK_CLK_SRC 16
+#define DISP_CC_MDSS_DP_LINK_INTF_CLK 17
+#define DISP_CC_MDSS_DP_PIXEL1_CLK 18
+#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 19
+#define DISP_CC_MDSS_DP_PIXEL_CLK 20
+#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 21
+#define DISP_CC_MDSS_ESC0_CLK 22
+#define DISP_CC_MDSS_ESC0_CLK_SRC 23
+#define DISP_CC_MDSS_ESC1_CLK 24
+#define DISP_CC_MDSS_ESC1_CLK_SRC 25
+#define DISP_CC_MDSS_MDP_CLK 26
+#define DISP_CC_MDSS_MDP_CLK_SRC 27
+#define DISP_CC_MDSS_MDP_LUT_CLK 28
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 29
+#define DISP_CC_MDSS_PCLK0_CLK 30
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 31
+#define DISP_CC_MDSS_PCLK1_CLK 32
+#define DISP_CC_MDSS_PCLK1_CLK_SRC 33
+#define DISP_CC_MDSS_ROT_CLK 34
+#define DISP_CC_MDSS_ROT_CLK_SRC 35
+#define DISP_CC_MDSS_RSCC_AHB_CLK 36
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK 37
+#define DISP_CC_MDSS_VSYNC_CLK 38
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 39
+#define DISP_CC_XO_CLK_SRC 40
+#define DISP_CC_SLEEP_CLK 41
+#define DISP_CC_SLEEP_CLK_SRC 42
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC 0
+
+#endif