Message ID | 20240511115400.7587-8-richard.henderson@linaro.org |
---|---|
State | New |
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([195.76.196.165]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502bbbbf20sm6764797f8f.93.2024.05.11.04.54.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 May 2024 04:54:09 -0700 (PDT) From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 07/17] ppc64: Compare all bits of CCR Date: Sat, 11 May 2024 13:53:50 +0200 Message-Id: <20240511115400.7587-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240511115400.7587-1-richard.henderson@linaro.org> References: <20240511115400.7587-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org |
Series |
RISU misc updates
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expand
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On 11/5/24 13:53, Richard Henderson wrote: > There are 32 bits in this register, and they are all valid > comparision destinations. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > risu_reginfo_ppc64.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 67ea3ce..109b87b 100644 --- a/risu_reginfo_ppc64.c +++ b/risu_reginfo_ppc64.c @@ -78,7 +78,7 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a) return 0; } - if ((m->gregs[CCR] & 0x10) != (a->gregs[CCR] & 0x10)) { + if (m->gregs[CCR] != a->gregs[CCR]) { return 0; }
There are 32 bits in this register, and they are all valid comparision destinations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- risu_reginfo_ppc64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)