| Message ID | 20240116150411.23876-5-quic_bibekkum@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs | expand |
On 1/16/24 16:04, Bibek Kumar Patro wrote: > Add ACTLR data table for SM8550 along with support for > same including SM8550 specific implementation operations. > > Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com> > --- [...] > +static const struct actlr_variant sm8550_actlr[] = { > + { .io_start = 0x15000000, .actlrcfg = sm8550_apps_actlr_cfg, > + .num_actlrcfg = ARRAY_SIZE(sm8550_apps_actlr_cfg) }, > + { .io_start = 0x03da0000, .actlrcfg = sm8550_gfx_actlr_cfg, > + .num_actlrcfg = ARRAY_SIZE(sm8550_gfx_actlr_cfg) }, > +}; Just a nit again, but if struct definitions need to be wrapped, this looks better: { .io_start = 0..., .aclrcfg = ..., .num_actlrcfg = ARR.., }, { .io_start = 0.., .aclrcfg = ..., .num_actlrcfg = ARR.., }; Konrad
On 1/18/2024 11:28 PM, Konrad Dybcio wrote: > > > On 1/16/24 16:04, Bibek Kumar Patro wrote: >> Add ACTLR data table for SM8550 along with support for >> same including SM8550 specific implementation operations. >> >> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com> >> --- > > [...] > >> +static const struct actlr_variant sm8550_actlr[] = { >> + { .io_start = 0x15000000, .actlrcfg = sm8550_apps_actlr_cfg, >> + .num_actlrcfg = ARRAY_SIZE(sm8550_apps_actlr_cfg) }, >> + { .io_start = 0x03da0000, .actlrcfg = sm8550_gfx_actlr_cfg, >> + .num_actlrcfg = ARRAY_SIZE(sm8550_gfx_actlr_cfg) }, >> +}; > Just a nit again, but if struct definitions need to be wrapped, this looks > better: > > { > .io_start = 0..., > .aclrcfg = ..., > .num_actlrcfg = ARR.., > }, { > .io_start = 0.., > .aclrcfg = ..., > .num_actlrcfg = ARR.., > }; > Noted, will wrap this to keep each member in a new line as shown. This looks much cleaner. Thanks for this suggestion. Regards, Bibek > Konrad
On Tue, Jan 16, 2024 at 7:06 AM Bibek Kumar Patro <quic_bibekkum@quicinc.com> wrote: > > Add ACTLR data table for SM8550 along with support for > same including SM8550 specific implementation operations. > > Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com> > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 85 ++++++++++++++++++++++ > 1 file changed, 85 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index e6fad02aae92..26acfbdafd0f 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -23,6 +23,12 @@ > > #define CPRE (1 << 1) > #define CMTLB (1 << 0) > +#define PREFETCH_SHIFT 8 > +#define PREFETCH_DEFAULT 0 > +#define PREFETCH_SHALLOW (1 << PREFETCH_SHIFT) > +#define PREFETCH_MODERATE (2 << PREFETCH_SHIFT) > +#define PREFETCH_DEEP (3 << PREFETCH_SHIFT) > +#define PREFETCH_SWITCH_GFX (5 << 3) so, PREFETCH_SWITCH_GFX seems to actually be two things, b5 is actually PRR_ENABLE and b3 is ?? Probably you should drop the PRR_ENABLE, and perhaps give b3 a better name BR, -R > > struct actlr_config { > u16 sid; > @@ -30,6 +36,75 @@ struct actlr_config { > u32 actlr; > }; > > +static const struct actlr_config sm8550_apps_actlr_cfg[] = { > + { 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, > + { 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, > + { 0x0800, 0x0020, PREFETCH_DEFAULT | CMTLB }, > + { 0x1800, 0x00c0, PREFETCH_DEFAULT | CMTLB }, > + { 0x1820, 0x0000, PREFETCH_DEFAULT | CMTLB }, > + { 0x1860, 0x0000, PREFETCH_DEFAULT | CMTLB }, > + { 0x0c01, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x0c02, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x0c03, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x0c04, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x0c05, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x0c06, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x0c07, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x0c08, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x0c09, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x0c0c, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x0c0d, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x0c0e, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x0c0f, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x1961, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x1962, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x1963, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x1964, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x1965, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x1966, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x1967, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x1968, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x1969, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x196c, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x196d, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x196e, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x196f, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x19c1, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x19c2, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x19c3, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x19c4, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x19c5, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x19c6, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x19c7, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x19c8, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x19c9, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x19cc, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x19cd, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x19ce, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x19cf, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, > + { 0x1c00, 0x0002, PREFETCH_SHALLOW | CPRE | CMTLB }, > + { 0x1c01, 0x0000, PREFETCH_DEFAULT | CMTLB }, > + { 0x1920, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, > + { 0x1923, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, > + { 0x1924, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, > + { 0x1940, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, > + { 0x1941, 0x0004, PREFETCH_SHALLOW | CPRE | CMTLB }, > + { 0x1943, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, > + { 0x1944, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, > + { 0x1947, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, > +}; > + > +static const struct actlr_config sm8550_gfx_actlr_cfg[] = { > + { 0x0000, 0x03ff, PREFETCH_SWITCH_GFX | PREFETCH_DEEP | CPRE | CMTLB }, > +}; > + > +static const struct actlr_variant sm8550_actlr[] = { > + { .io_start = 0x15000000, .actlrcfg = sm8550_apps_actlr_cfg, > + .num_actlrcfg = ARRAY_SIZE(sm8550_apps_actlr_cfg) }, > + { .io_start = 0x03da0000, .actlrcfg = sm8550_gfx_actlr_cfg, > + .num_actlrcfg = ARRAY_SIZE(sm8550_gfx_actlr_cfg) }, > +}; > + > static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) > { > return container_of(smmu, struct qcom_smmu, smmu); > @@ -601,6 +676,15 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = { > /* Also no debug configuration. */ > }; > > + > +static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = { > + .impl = &qcom_smmu_500_impl, > + .adreno_impl = &qcom_adreno_smmu_500_impl, > + .cfg = &qcom_smmu_impl0_cfg, > + .actlrvar = sm8550_actlr, > + .num_smmu = ARRAY_SIZE(sm8550_actlr), > +}; > + > static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = { > .impl = &qcom_smmu_500_impl, > .adreno_impl = &qcom_adreno_smmu_500_impl, > @@ -635,6 +719,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { > { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data }, > { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data }, > { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data }, > + { .compatible = "qcom,sm8550-smmu-500", .data = &sm8550_smmu_500_impl0_data }, > { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data }, > { } > }; > -- > 2.17.1 > >
On 6/4/2024 10:43 PM, Rob Clark wrote: > On Tue, Jan 16, 2024 at 7:06 AM Bibek Kumar Patro > <quic_bibekkum@quicinc.com> wrote: >> >> Add ACTLR data table for SM8550 along with support for >> same including SM8550 specific implementation operations. >> >> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com> >> --- >> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 85 ++++++++++++++++++++++ >> 1 file changed, 85 insertions(+) >> >> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> index e6fad02aae92..26acfbdafd0f 100644 >> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> @@ -23,6 +23,12 @@ >> >> #define CPRE (1 << 1) >> #define CMTLB (1 << 0) >> +#define PREFETCH_SHIFT 8 >> +#define PREFETCH_DEFAULT 0 >> +#define PREFETCH_SHALLOW (1 << PREFETCH_SHIFT) >> +#define PREFETCH_MODERATE (2 << PREFETCH_SHIFT) >> +#define PREFETCH_DEEP (3 << PREFETCH_SHIFT) >> +#define PREFETCH_SWITCH_GFX (5 << 3) > > so, PREFETCH_SWITCH_GFX seems to actually be two things, b5 is > actually PRR_ENABLE and b3 is ?? > only b5 is not prr related bit as I checked now, will drop b3 and use this field for PRR bit only. Thanks & regards, Bibek > Probably you should drop the PRR_ENABLE, and perhaps give b3 a better name > > BR, > -R > Thanks & regards, Bibek >> >> struct actlr_config { >> u16 sid; >> @@ -30,6 +36,75 @@ struct actlr_config { >> u32 actlr; >> }; >> >> +static const struct actlr_config sm8550_apps_actlr_cfg[] = { >> + { 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, >> + { 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, >> + { 0x0800, 0x0020, PREFETCH_DEFAULT | CMTLB }, >> + { 0x1800, 0x00c0, PREFETCH_DEFAULT | CMTLB }, >> + { 0x1820, 0x0000, PREFETCH_DEFAULT | CMTLB }, >> + { 0x1860, 0x0000, PREFETCH_DEFAULT | CMTLB }, >> + { 0x0c01, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x0c02, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x0c03, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x0c04, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x0c05, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x0c06, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x0c07, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x0c08, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x0c09, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x0c0c, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x0c0d, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x0c0e, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x0c0f, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x1961, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x1962, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x1963, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x1964, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x1965, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x1966, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x1967, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x1968, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x1969, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x196c, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x196d, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x196e, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x196f, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x19c1, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x19c2, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x19c3, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x19c4, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x19c5, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x19c6, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x19c7, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x19c8, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x19c9, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x19cc, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x19cd, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x19ce, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x19cf, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, >> + { 0x1c00, 0x0002, PREFETCH_SHALLOW | CPRE | CMTLB }, >> + { 0x1c01, 0x0000, PREFETCH_DEFAULT | CMTLB }, >> + { 0x1920, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, >> + { 0x1923, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, >> + { 0x1924, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, >> + { 0x1940, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, >> + { 0x1941, 0x0004, PREFETCH_SHALLOW | CPRE | CMTLB }, >> + { 0x1943, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, >> + { 0x1944, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, >> + { 0x1947, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, >> +}; >> + >> +static const struct actlr_config sm8550_gfx_actlr_cfg[] = { >> + { 0x0000, 0x03ff, PREFETCH_SWITCH_GFX | PREFETCH_DEEP | CPRE | CMTLB }, >> +}; >> + >> +static const struct actlr_variant sm8550_actlr[] = { >> + { .io_start = 0x15000000, .actlrcfg = sm8550_apps_actlr_cfg, >> + .num_actlrcfg = ARRAY_SIZE(sm8550_apps_actlr_cfg) }, >> + { .io_start = 0x03da0000, .actlrcfg = sm8550_gfx_actlr_cfg, >> + .num_actlrcfg = ARRAY_SIZE(sm8550_gfx_actlr_cfg) }, >> +}; >> + >> static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) >> { >> return container_of(smmu, struct qcom_smmu, smmu); >> @@ -601,6 +676,15 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = { >> /* Also no debug configuration. */ >> }; >> >> + >> +static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = { >> + .impl = &qcom_smmu_500_impl, >> + .adreno_impl = &qcom_adreno_smmu_500_impl, >> + .cfg = &qcom_smmu_impl0_cfg, >> + .actlrvar = sm8550_actlr, >> + .num_smmu = ARRAY_SIZE(sm8550_actlr), >> +}; >> + >> static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = { >> .impl = &qcom_smmu_500_impl, >> .adreno_impl = &qcom_adreno_smmu_500_impl, >> @@ -635,6 +719,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { >> { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data }, >> { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data }, >> { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data }, >> + { .compatible = "qcom,sm8550-smmu-500", .data = &sm8550_smmu_500_impl0_data }, >> { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data }, >> { } >> }; >> -- >> 2.17.1 >> >>
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index e6fad02aae92..26acfbdafd0f 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -23,6 +23,12 @@ #define CPRE (1 << 1) #define CMTLB (1 << 0) +#define PREFETCH_SHIFT 8 +#define PREFETCH_DEFAULT 0 +#define PREFETCH_SHALLOW (1 << PREFETCH_SHIFT) +#define PREFETCH_MODERATE (2 << PREFETCH_SHIFT) +#define PREFETCH_DEEP (3 << PREFETCH_SHIFT) +#define PREFETCH_SWITCH_GFX (5 << 3) struct actlr_config { u16 sid; @@ -30,6 +36,75 @@ struct actlr_config { u32 actlr; }; +static const struct actlr_config sm8550_apps_actlr_cfg[] = { + { 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x0800, 0x0020, PREFETCH_DEFAULT | CMTLB }, + { 0x1800, 0x00c0, PREFETCH_DEFAULT | CMTLB }, + { 0x1820, 0x0000, PREFETCH_DEFAULT | CMTLB }, + { 0x1860, 0x0000, PREFETCH_DEFAULT | CMTLB }, + { 0x0c01, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c02, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c03, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c04, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c05, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c06, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c07, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c08, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c09, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c0c, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c0d, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c0e, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c0f, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1961, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1962, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1963, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1964, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1965, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1966, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1967, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1968, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1969, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x196c, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x196d, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x196e, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x196f, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c1, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c2, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c3, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c4, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c5, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c6, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c7, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c8, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c9, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19cc, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19cd, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19ce, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19cf, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1c00, 0x0002, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1c01, 0x0000, PREFETCH_DEFAULT | CMTLB }, + { 0x1920, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1923, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1924, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1940, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1941, 0x0004, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1943, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1944, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1947, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, +}; + +static const struct actlr_config sm8550_gfx_actlr_cfg[] = { + { 0x0000, 0x03ff, PREFETCH_SWITCH_GFX | PREFETCH_DEEP | CPRE | CMTLB }, +}; + +static const struct actlr_variant sm8550_actlr[] = { + { .io_start = 0x15000000, .actlrcfg = sm8550_apps_actlr_cfg, + .num_actlrcfg = ARRAY_SIZE(sm8550_apps_actlr_cfg) }, + { .io_start = 0x03da0000, .actlrcfg = sm8550_gfx_actlr_cfg, + .num_actlrcfg = ARRAY_SIZE(sm8550_gfx_actlr_cfg) }, +}; + static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) { return container_of(smmu, struct qcom_smmu, smmu); @@ -601,6 +676,15 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = { /* Also no debug configuration. */ }; + +static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = { + .impl = &qcom_smmu_500_impl, + .adreno_impl = &qcom_adreno_smmu_500_impl, + .cfg = &qcom_smmu_impl0_cfg, + .actlrvar = sm8550_actlr, + .num_smmu = ARRAY_SIZE(sm8550_actlr), +}; + static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = { .impl = &qcom_smmu_500_impl, .adreno_impl = &qcom_adreno_smmu_500_impl, @@ -635,6 +719,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data }, + { .compatible = "qcom,sm8550-smmu-500", .data = &sm8550_smmu_500_impl0_data }, { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data }, { } };
Add ACTLR data table for SM8550 along with support for same including SM8550 specific implementation operations. Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com> --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 85 ++++++++++++++++++++++ 1 file changed, 85 insertions(+) -- 2.17.1