| Message ID | 20240620081427.2860066-6-quic_varada@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v1,1/7] dt-bindings: power: rpmpd: Add IPQ9574 power domains | expand |
On Thu, Jun 20, 2024 at 06:11:32PM +0300, Dmitry Baryshkov wrote: > On Thu, Jun 20, 2024 at 01:44:25PM GMT, Varadarajan Narayanan wrote: > > Add the CPR clock definition needed for enabling access to > > CPR register space. > > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > > --- > > drivers/clk/qcom/gcc-ipq9574.c | 38 ++++++++++++++++++++++++++++++++++ > > 1 file changed, 38 insertions(+) > > > > diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c > > index e1dc74d04ed1..7c8eb94f654b 100644 > > --- a/drivers/clk/qcom/gcc-ipq9574.c > > +++ b/drivers/clk/qcom/gcc-ipq9574.c > > @@ -3994,6 +3994,43 @@ static struct clk_branch gcc_xo_div4_clk = { > > }, > > }; > > > > +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { > > + F(24000000, P_XO, 1, 0, 0), > > + { } > > +}; > > + > > +static struct clk_rcg2 rbcpr_clk_src = { > > + .cmd_rcgr = 0x48044, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = gcc_xo_map, > > + .freq_tbl = ftbl_gp1_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "rbcpr_clk_src", > > + .parent_data = gcc_xo_gpll0_gpll4, > > + .num_parents = ARRAY_SIZE(gcc_xo_map), > > + .ops = &clk_rcg2_ops, > > + }, > > +}; > > + > > +static struct clk_branch gcc_rbcpr_clk = { > > + .halt_reg = 0x48008, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x48008, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gcc_rbcpr_clk", > > + .parent_hws = (const struct clk_hw *[]) { > > + &rbcpr_clk_src.clkr.hw, > > Where is the &rbcpr_clk_src registered? Oops. Missed it. Will post a corrected patch. Thanks Varada > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > static struct clk_hw *gcc_ipq9574_hws[] = { > > &gpll0_out_main_div2.hw, > > &gcc_xo_div4_clk_src.hw, > > @@ -4219,6 +4256,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { > > [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, > > [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, > > [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, > > + [GCC_RBCPR_CLK] = &gcc_rbcpr_clk.clkr, > > }; > > > > static const struct qcom_reset_map gcc_ipq9574_resets[] = { > > -- > > 2.34.1
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index e1dc74d04ed1..7c8eb94f654b 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -3994,6 +3994,43 @@ static struct clk_branch gcc_xo_div4_clk = { }, }; +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { + F(24000000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 rbcpr_clk_src = { + .cmd_rcgr = 0x48044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_xo_map, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rbcpr_clk_src", + .parent_data = gcc_xo_gpll0_gpll4, + .num_parents = ARRAY_SIZE(gcc_xo_map), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_rbcpr_clk = { + .halt_reg = 0x48008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x48008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rbcpr_clk", + .parent_hws = (const struct clk_hw *[]) { + &rbcpr_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_hw *gcc_ipq9574_hws[] = { &gpll0_out_main_div2.hw, &gcc_xo_div4_clk_src.hw, @@ -4219,6 +4256,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, + [GCC_RBCPR_CLK] = &gcc_rbcpr_clk.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = {
Add the CPR clock definition needed for enabling access to CPR register space. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> --- drivers/clk/qcom/gcc-ipq9574.c | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+)