diff mbox series

[13/13] target/arm: Delete dead code from disas_simd_indexed

Message ID 20240625050810.1475643-14-richard.henderson@linaro.org
State Superseded
Headers show
Series target/arm: AdvSIMD conversion, part 2 | expand

Commit Message

Richard Henderson June 25, 2024, 5:08 a.m. UTC 
The last insns in this block, MLA and MLS, were converted
with f80701cb44d, and this code should have been removed then.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/tcg/translate-a64.c | 93 ----------------------------------
 1 file changed, 93 deletions(-)

Comments

Peter Maydell June 25, 2024, 12:41 p.m. UTC | #1 
On Tue, 25 Jun 2024 at 06:09, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The last insns in this block, MLA and MLS, were converted
> with f80701cb44d, and this code should have been removed then.

"MLA, MLS, SQDMULH, SQRDMULH, were converted with f80701cb44d
and f80701cb44d33", I think, since there's still code for
all four of those insns that we're deleting here ?


> -            switch (16 * u + opcode) {
> -            case 0x10: /* MLA */
> -            case 0x14: /* MLS */
> -            {
> -                static NeonGenTwoOpFn * const fns[2][2] = {
> -                    { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
> -                    { tcg_gen_add_i32, tcg_gen_sub_i32 },
> -                };
> -                NeonGenTwoOpFn *genfn;
> -                bool is_sub = opcode == 0x4;
> -
> -                if (size == 1) {
> -                    gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx);
> -                } else {
> -                    tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx);
> -                }
> -                if (opcode == 0x8) {
> -                    break;
> -                }
> -                read_vec_element_i32(s, tcg_op, rd, pass, MO_32);
> -                genfn = fns[size - 1][is_sub];
> -                genfn(tcg_res, tcg_op, tcg_res);
> -                break;
> -            }
> -            case 0x0c: /* SQDMULH */
> -                if (size == 1) {
> -                    gen_helper_neon_qdmulh_s16(tcg_res, tcg_env,
> -                                               tcg_op, tcg_idx);
> -                } else {
> -                    gen_helper_neon_qdmulh_s32(tcg_res, tcg_env,
> -                                               tcg_op, tcg_idx);
> -                }
> -                break;
> -            case 0x0d: /* SQRDMULH */
> -                if (size == 1) {
> -                    gen_helper_neon_qrdmulh_s16(tcg_res, tcg_env,
> -                                                tcg_op, tcg_idx);
> -                } else {
> -                    gen_helper_neon_qrdmulh_s32(tcg_res, tcg_env,
> -                                                tcg_op, tcg_idx);
> -                }
> -                break;

Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM
Richard Henderson June 25, 2024, 2:18 p.m. UTC | #2 
On 6/25/24 05:41, Peter Maydell wrote:
> On Tue, 25 Jun 2024 at 06:09, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> The last insns in this block, MLA and MLS, were converted
>> with f80701cb44d, and this code should have been removed then.
> 
> "MLA, MLS, SQDMULH, SQRDMULH, were converted with f80701cb44d
> and f80701cb44d33", I think, since there's still code for
> all four of those insns that we're deleting here ?

Yes.


r~
Peter Maydell June 25, 2024, 2:21 p.m. UTC | #3 
On Tue, 25 Jun 2024 at 15:18, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 6/25/24 05:41, Peter Maydell wrote:
> > On Tue, 25 Jun 2024 at 06:09, Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> The last insns in this block, MLA and MLS, were converted
> >> with f80701cb44d, and this code should have been removed then.
> >
> > "MLA, MLS, SQDMULH, SQRDMULH, were converted with f80701cb44d
> > and f80701cb44d33", I think, since there's still code for
> > all four of those insns that we're deleting here ?
>
> Yes.

...except "with 8db93dcd3def0ca and f80701cb44d".

-- PMM
diff mbox series

Patch

diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 0a54a9ef8f..11955c0c36 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -11979,7 +11979,6 @@  static void disas_simd_indexed(DisasContext *s, uint32_t insn)
     int h = extract32(insn, 11, 1);
     int rn = extract32(insn, 5, 5);
     int rd = extract32(insn, 0, 5);
-    bool is_long = false;
     int index;
 
     switch (16 * u + opcode) {
@@ -11993,12 +11992,10 @@  static void disas_simd_indexed(DisasContext *s, uint32_t insn)
             unallocated_encoding(s);
             return;
         }
-        is_long = true;
         break;
     case 0x03: /* SQDMLAL, SQDMLAL2 */
     case 0x07: /* SQDMLSL, SQDMLSL2 */
     case 0x0b: /* SQDMULL, SQDMULL2 */
-        is_long = true;
         break;
     default:
     case 0x00: /* FMLAL */
@@ -12050,96 +12047,6 @@  static void disas_simd_indexed(DisasContext *s, uint32_t insn)
 
     if (size == 3) {
         g_assert_not_reached();
-    } else if (!is_long) {
-        /* 32 bit floating point, or 16 or 32 bit integer.
-         * For the 16 bit scalar case we use the usual Neon helpers and
-         * rely on the fact that 0 op 0 == 0 with no side effects.
-         */
-        TCGv_i32 tcg_idx = tcg_temp_new_i32();
-        int pass, maxpasses;
-
-        if (is_scalar) {
-            maxpasses = 1;
-        } else {
-            maxpasses = is_q ? 4 : 2;
-        }
-
-        read_vec_element_i32(s, tcg_idx, rm, index, size);
-
-        if (size == 1 && !is_scalar) {
-            /* The simplest way to handle the 16x16 indexed ops is to duplicate
-             * the index into both halves of the 32 bit tcg_idx and then use
-             * the usual Neon helpers.
-             */
-            tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
-        }
-
-        for (pass = 0; pass < maxpasses; pass++) {
-            TCGv_i32 tcg_op = tcg_temp_new_i32();
-            TCGv_i32 tcg_res = tcg_temp_new_i32();
-
-            read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32);
-
-            switch (16 * u + opcode) {
-            case 0x10: /* MLA */
-            case 0x14: /* MLS */
-            {
-                static NeonGenTwoOpFn * const fns[2][2] = {
-                    { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
-                    { tcg_gen_add_i32, tcg_gen_sub_i32 },
-                };
-                NeonGenTwoOpFn *genfn;
-                bool is_sub = opcode == 0x4;
-
-                if (size == 1) {
-                    gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx);
-                } else {
-                    tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx);
-                }
-                if (opcode == 0x8) {
-                    break;
-                }
-                read_vec_element_i32(s, tcg_op, rd, pass, MO_32);
-                genfn = fns[size - 1][is_sub];
-                genfn(tcg_res, tcg_op, tcg_res);
-                break;
-            }
-            case 0x0c: /* SQDMULH */
-                if (size == 1) {
-                    gen_helper_neon_qdmulh_s16(tcg_res, tcg_env,
-                                               tcg_op, tcg_idx);
-                } else {
-                    gen_helper_neon_qdmulh_s32(tcg_res, tcg_env,
-                                               tcg_op, tcg_idx);
-                }
-                break;
-            case 0x0d: /* SQRDMULH */
-                if (size == 1) {
-                    gen_helper_neon_qrdmulh_s16(tcg_res, tcg_env,
-                                                tcg_op, tcg_idx);
-                } else {
-                    gen_helper_neon_qrdmulh_s32(tcg_res, tcg_env,
-                                                tcg_op, tcg_idx);
-                }
-                break;
-            default:
-            case 0x01: /* FMLA */
-            case 0x05: /* FMLS */
-            case 0x09: /* FMUL */
-            case 0x19: /* FMULX */
-            case 0x1d: /* SQRDMLAH */
-            case 0x1f: /* SQRDMLSH */
-                g_assert_not_reached();
-            }
-
-            if (is_scalar) {
-                write_fp_sreg(s, rd, tcg_res);
-            } else {
-                write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
-            }
-        }
-
-        clear_vec_high(s, is_q, rd);
     } else {
         /* long ops: 16x16->32 or 32x32->64 */
         TCGv_i64 tcg_res[2];