| Message ID | 20240828203721.2751904-1-quic_nkela@quicinc.com |
|---|---|
| Headers | show |
| Series | arm64: qcom: Introduce SA8255p Ride platform | expand |
On Wed, Aug 28, 2024 at 01:37:00PM -0700, Nikunj Kela wrote: > Add the SoC ID entry for SA8255P. > > Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com> > --- > include/dt-bindings/arm/qcom,ids.h | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Wed, Aug 28, 2024 at 01:37:02PM -0700, Nikunj Kela wrote: > Document the SA8255p SoC and its reference board: sa8255p-ride. > > Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com> > --- > Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Wed, Aug 28, 2024 at 01:37:06PM -0700, Nikunj Kela wrote: > Document SA8255p compatible for the True Random Number Generator. > > Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com> > --- > Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Wed, Aug 28, 2024 at 01:37:09PM -0700, Nikunj Kela wrote: > Add compatible for pincontrol representing support on SA8255p. > > SA8255p uses the same TLMM block as SA8775p however the ownership > of pins are split between Firmware VM and Linux VM on SA8255p. For > example, pins used by UART are owned and configured by Firmware VM > while pins used by ethernet are owned and configured by Linux VM. > Therefore, adding a sa8255p specific compatible to mark the difference. > > Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com> > --- Explanation does not match driver (discussion in the driver). Best regards, Krzysztof
On Wed, Aug 28, 2024 at 01:37:19PM -0700, Nikunj Kela wrote: > This change extends scmi node name so as to allow multiple virtual > SCMI instances. > > Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com> > --- > Documentation/devicetree/bindings/firmware/arm,scmi.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml > index 211f5254adf2..a168be6dd30c 100644 > --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml > +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml > @@ -24,7 +24,7 @@ description: | > > properties: > $nodename: > - const: scmi > + pattern: '^scmi\.*' ^scmi(-[0-9]+)?$ Best regards, Krzysztof
On 28/08/2024 22:36, Nikunj Kela wrote: > This series enables the support for SA8255p Qualcomm SoC and Ride > platform. This platform uses SCMI power, reset, performance, sensor > protocols for resources(e.g. clocks, regulator, interconnect, phy etc.) > management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc > transport driver. > Who is supposed to merge it? The Cc-list is quite enormous and I got now 20 bounces: " Too many recipients to the message" at least drop some non-maintainer related, I counted 5-7 Qualcomm ones which should not be needed. Best regards, Krzysztof
On 8/29/2024 12:57 AM, Krzysztof Kozlowski wrote: > On 28/08/2024 22:36, Nikunj Kela wrote: >> This series enables the support for SA8255p Qualcomm SoC and Ride >> platform. This platform uses SCMI power, reset, performance, sensor >> protocols for resources(e.g. clocks, regulator, interconnect, phy etc.) >> management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc >> transport driver. >> > Who is supposed to merge it? The Cc-list is quite enormous and I got now > 20 bounces: > > " Too many recipients to the message" > > at least drop some non-maintainer related, I counted 5-7 Qualcomm ones > which should not be needed. > > Best regards, > Krzysztof Hi Krzysztof, I ran maintainers script to get all the emails. I kept maintainers, reviewers and "in file" ones in addition to some Qualcomm leads. I will drop "in file" and Qualcomm leads in next version. Thanks, -Nikunj
On 8/29/2024 12:36 AM, Krzysztof Kozlowski wrote: > On Wed, Aug 28, 2024 at 01:37:13PM -0700, Nikunj Kela wrote: >> Add compatible for smmu representing support on SA8255p. >> >> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com> >> --- >> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++ >> 1 file changed, 3 insertions(+) >> > Your subjects contain quite redundant/excessive information. In the same > time they lack information about device. > > 1. s/document the support on/add/ > 2. s/SA8255p/SA8255p SMMU-or-whatever-device-it-is/ > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > Best regards, > Krzysztof Okay. I thought arm-smmu tag already indicate which device this patch is for but would put SMMU explicitly in the subject. Thanks, -Nikunj
On Wed, Aug 28, 2024 at 01:37:20PM -0700, Nikunj Kela wrote: > Add interrupt specifier for extended SPI interrupts. What's an "extended SPI"? Is this a GIC spec thing? If so, what version? > > Qualcomm SA8255p platform uses extended SPI for SCMI 'a2p' doorbells. > > Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com> > --- > include/dt-bindings/interrupt-controller/arm-gic.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h > index 35b6f69b7db6..9c06248446b7 100644 > --- a/include/dt-bindings/interrupt-controller/arm-gic.h > +++ b/include/dt-bindings/interrupt-controller/arm-gic.h > @@ -12,6 +12,7 @@ > > #define GIC_SPI 0 > #define GIC_PPI 1 > +#define GIC_ESPI 2 > > /* > * Interrupt specifier cell 2. > -- > 2.34.1 >
On 8/29/2024 11:52 AM, Rob Herring wrote: > On Wed, Aug 28, 2024 at 01:37:20PM -0700, Nikunj Kela wrote: >> Add interrupt specifier for extended SPI interrupts. > What's an "extended SPI"? Is this a GIC spec thing? If so, what version? Extended SPI is an extended range of SPI interrupts supported by GIC. Excerpt below from Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml "The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI interrupts, 2 for interrupts in the Extended SPI range, 3 for the Extended PPI range. Other values are reserved for future use." "The 2nd cell contains the interrupt number for the interrupt type. SPI interrupts are in the range [0-987]. PPI interrupts are in the range [0-15]. Extented SPI interrupts are in the range [0-1023]. Extended PPI interrupts are in the range [0-127]." >> Qualcomm SA8255p platform uses extended SPI for SCMI 'a2p' doorbells. >> >> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com> >> --- >> include/dt-bindings/interrupt-controller/arm-gic.h | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h >> index 35b6f69b7db6..9c06248446b7 100644 >> --- a/include/dt-bindings/interrupt-controller/arm-gic.h >> +++ b/include/dt-bindings/interrupt-controller/arm-gic.h >> @@ -12,6 +12,7 @@ >> >> #define GIC_SPI 0 >> #define GIC_PPI 1 >> +#define GIC_ESPI 2 >> >> /* >> * Interrupt specifier cell 2. >> -- >> 2.34.1 >>
On 29/08/2024 17:39, Nikunj Kela wrote: > > On 8/29/2024 12:36 AM, Krzysztof Kozlowski wrote: >> On Wed, Aug 28, 2024 at 01:37:13PM -0700, Nikunj Kela wrote: >>> Add compatible for smmu representing support on SA8255p. >>> >>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com> >>> --- >>> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++ >>> 1 file changed, 3 insertions(+) >>> >> Your subjects contain quite redundant/excessive information. In the same >> time they lack information about device. >> >> 1. s/document the support on/add/ >> 2. s/SA8255p/SA8255p SMMU-or-whatever-device-it-is/ >> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> >> Best regards, >> Krzysztof > > Okay. I thought arm-smmu tag already indicate which device this patch is > for but would put SMMU explicitly in the subject. arm,smmu indicates the binding file which might be or might not exactly be the same as actual device. Sometimes they have difference names. I am not saying that it would be beneficial here, but some other patches could benefit probably. Best regards, Krzysztof
On Thu, Aug 29, 2024 at 2:02 PM Nikunj Kela <quic_nkela@quicinc.com> wrote: > > > On 8/29/2024 11:52 AM, Rob Herring wrote: > > On Wed, Aug 28, 2024 at 01:37:20PM -0700, Nikunj Kela wrote: > >> Add interrupt specifier for extended SPI interrupts. > > What's an "extended SPI"? Is this a GIC spec thing? If so, what version? > > Extended SPI is an extended range of SPI interrupts supported by GIC. > > Excerpt below from > Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml > > "The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI > interrupts, 2 for interrupts in the Extended SPI range, 3 for the > Extended PPI range. Other values are reserved for future use." > > "The 2nd cell contains the interrupt number for the interrupt type. SPI > interrupts are in the range [0-987]. PPI interrupts are in the range > [0-15]. Extented SPI interrupts are in the range [0-1023]. Extended PPI > interrupts are in the range [0-127]." Looks like you should add EPPI define too while you're here. Rob
On 8/30/2024 7:44 AM, Rob Herring wrote: > On Thu, Aug 29, 2024 at 2:02 PM Nikunj Kela <quic_nkela@quicinc.com> wrote: >> >> On 8/29/2024 11:52 AM, Rob Herring wrote: >>> On Wed, Aug 28, 2024 at 01:37:20PM -0700, Nikunj Kela wrote: >>>> Add interrupt specifier for extended SPI interrupts. >>> What's an "extended SPI"? Is this a GIC spec thing? If so, what version? >> Extended SPI is an extended range of SPI interrupts supported by GIC. >> >> Excerpt below from >> Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml >> >> "The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI >> interrupts, 2 for interrupts in the Extended SPI range, 3 for the >> Extended PPI range. Other values are reserved for future use." >> >> "The 2nd cell contains the interrupt number for the interrupt type. SPI >> interrupts are in the range [0-987]. PPI interrupts are in the range >> [0-15]. Extented SPI interrupts are in the range [0-1023]. Extended PPI >> interrupts are in the range [0-127]." > Looks like you should add EPPI define too while you're here. > > Rob Sure Rob. I can add that. Generally, there is an ask for a usecase before we push anything that is used in DT. I won't have any usecase to show for EPPI.
This series enables the support for SA8255p Qualcomm SoC and Ride
platform. This platform uses SCMI power, reset, performance, sensor
protocols for resources(e.g. clocks, regulator, interconnect, phy etc.)
management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc
transport driver.
Multiple virtual SCMI instances are being used to achieve the parallelism.
SCMI platform stack runs in SMP enabled VM hence allows platform to service
multiple resource requests in parallel. Each device is assigned its own
dedicated SCMI channel and Tx/Rx doorbells.
Resource operations are grouped together to achieve better abstraction
and to reduce the number of requests being sent to SCMI platform(server)
thus improving boot time KPIs. This design approach was presented during
LinaroConnect 2024 conference[1].
Architecture:
------------
+--------------------+
| Shared Memory |
| |
| +----------------+ | +----------------------------------+
+----------------------------+ +-+-> ufs-shmem <-+---+ | Linux VM |
| Firmware VM | | | +----------------+ | | | +----------+ +----------+ |
| | | | | | | | UFS | | PCIe | |
| +---------+ f +----------+ | | | | | | | Driver | | Driver | |
| |Drivers <---+ SCMI | | e | | | | | | +--+----^--+ +----------+ |
| | (clks, | g | Server +-+---------------------+ | | | | | | |
| | vreg, +---> | | h | | | b|k | a| l| |
| | gpio, | +--^-----+-+ | | | | | | | |
| | phy, | | | | | | | | | +---v----+----+ +----------+ |
| | etc.) | | | | | | +------------+--+ UFS SCMI | | PCIe SCMI| |
| +---------+ | | | | | | | INSTANCE | | INSTANCE | |
| | | | | +---------------+ | | +-^-----+-----+ +----------+ |
| | | | | | pcie-shmem | | | | | |
+------------------+-----+---+ | +---------------+ | +----+-----+-----------------------+
| | | | | |
| | +--------------------+ | |
d|IRQ i|HVC j|IRQ c|HVC
| | | |
| | | |
+-----------------------+-----v----------------------------------------------------------------------+-----v------------------------------+
| |
| |
| |
| HYPERVISOR |
| |
| |
+-----------------------------------------------------------------------------------------------------------------------------------------+
+--------+ +--------+ +----------+ +-----------+
| CLOCK | | PHY | | UFS | | PCIe |
+--------+ +--------+ +----------+ +-----------+
This series is based on next-20240903.
[1]: https://resources.linaro.org/en/resource/wfnfEwBhRjLV1PEAJoDDte
---
Changes in v2:
- Patch 1/21 - 11/21
- Added Reviewed-by tag
- Patch 12/21
- Already applied in the maintainers tree
- Patch 13/21
- Modified subject line
- Fixed schema to include fallback
- Patch 14/21
- Added constraints
- Patch 15/21
- Modified schema to remove useless text
- Patch 16/21
- Modified schema formatting
- Amended schema definition as advised
- Patch 17/21
- Moved allOf block after required
- Fixed formatting
- Modified schema to remove useless text
- Patch 18/21
- Fixed clock property changes
- Patch 19/21
- Fixed scmi nodename pattern
- Patch 20/21
- Modified subject line and description
- Added EPPI macro
- Patch 21/21
- Removed scmichannels label and alias
- Modified scmi node name to conform to schema
- Moved status property to be the last one in scmi instances
- Changed to lower case for cpu labels
- Added fallback compatible for tlmm node
Nikunj Kela (21):
dt-bindings: arm: qcom: add the SoC ID for SA8255P
soc: qcom: socinfo: add support for SA8255P
dt-bindings: arm: qcom: add SA8255p Ride board
dt-bindings: firmware: qcom,scm: document support for SA8255p
dt-bindings: mailbox: qcom-ipcc: document the support for SA8255p
dt-bindings: watchdog: qcom-wdt: document support on SA8255p
dt-bindings: crypto: qcom,prng: document support for SA8255p
dt-bindings: interrupt-controller: qcom-pdc: document support for
SA8255p
dt-bindings: soc: qcom: aoss-qmp: document support for SA8255p
dt-bindings: arm-smmu: document the support on SA8255p
dt-bindings: mfd: qcom,tcsr: document support for SA8255p
dt-bindings: thermal: tsens: document support on SA8255p
dt-bindings: pinctrl: Add SA8255p TLMM
dt-bindings: cpufreq: qcom-hw: document support for SA8255p
dt-bindings: i2c: document support for SA8255p
dt-bindings: spi: document support for SA8255p
dt-bindings: serial: document support for SA8255p
dt-bindings: qcom: geni-se: document support for SA8255P
dt-bindings: firmware: arm,scmi: allow multiple virtual instances
dt-bindings: arm: GIC: add ESPI and EPPI specifiers
arm64: dts: qcom: Add reduced functional DT for SA8255p Ride platform
.../devicetree/bindings/arm/qcom.yaml | 6 +
.../bindings/cpufreq/cpufreq-qcom-hw.yaml | 16 +
.../devicetree/bindings/crypto/qcom,prng.yaml | 1 +
.../bindings/firmware/arm,scmi.yaml | 2 +-
.../bindings/firmware/qcom,scm.yaml | 2 +
.../bindings/i2c/qcom,i2c-geni-qcom.yaml | 33 +-
.../interrupt-controller/qcom,pdc.yaml | 1 +
.../devicetree/bindings/iommu/arm,smmu.yaml | 3 +
.../bindings/mailbox/qcom-ipcc.yaml | 1 +
.../devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +
.../bindings/pinctrl/qcom,sa8775p-tlmm.yaml | 8 +-
.../serial/qcom,serial-geni-qcom.yaml | 53 +-
.../bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 +
.../bindings/soc/qcom/qcom,geni-se.yaml | 45 +-
.../bindings/spi/qcom,spi-geni-qcom.yaml | 60 +-
.../bindings/thermal/qcom-tsens.yaml | 1 +
.../bindings/watchdog/qcom-wdt.yaml | 1 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi | 80 +
arch/arm64/boot/dts/qcom/sa8255p-ride.dts | 148 +
arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi | 2312 ++++++++++++++++
arch/arm64/boot/dts/qcom/sa8255p.dtsi | 2405 +++++++++++++++++
drivers/soc/qcom/socinfo.c | 1 +
include/dt-bindings/arm/qcom,ids.h | 1 +
.../interrupt-controller/arm-gic.h | 2 +
25 files changed, 5169 insertions(+), 16 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts
create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi
base-commit: 6804f0edbe7747774e6ae60f20cec4ee3ad7c187
On 9/4/2024 10:05 AM, Andrew Lunn wrote: >> The driver changes will soon be posted. They are being reviewed >> internally. > And what do you do when internal reviewers tell you that everything is > wrong and you need to change the binding? You just wasted a lot of > peoples time. Let me clarify here, the patches have already been through multiple rounds of review and since this is new architecture that we are using, we want to make sure this gets reviewed internally as much as possible. While, we will be posting them soon, they are available on public git repo for anyone to take a feel of the amount of changes. Let's not be judgemental here. > Please don't post patches until you know they are correct, complete, > build W=1, and pass all the standard static analysers. > > I suggest you try to find an experience Mainline developer who can > mentor you. No one is born with experience. You learn as you go. Please note that this series has gone through internal review before I posted it in upstream. > Andrew
Hi All, I have decided to split this series into multiple smaller ones as follows: - Patches 1/21 - 11/21, 13/21 - 14/21, 19/21: will split them to each subsystem specific patch sets. - Patches 15/21 - 18/21: will come in separate series along with QUPs driver changes. - Patches 20/21 - 21/21: will come in separate series after above two sets are accepted. Thanks, -Nikunj On 9/3/2024 3:02 PM, Nikunj Kela wrote: > This series enables the support for SA8255p Qualcomm SoC and Ride > platform. This platform uses SCMI power, reset, performance, sensor > protocols for resources(e.g. clocks, regulator, interconnect, phy etc.) > management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc > transport driver. > > Multiple virtual SCMI instances are being used to achieve the parallelism. > SCMI platform stack runs in SMP enabled VM hence allows platform to service > multiple resource requests in parallel. Each device is assigned its own > dedicated SCMI channel and Tx/Rx doorbells. > > Resource operations are grouped together to achieve better abstraction > and to reduce the number of requests being sent to SCMI platform(server) > thus improving boot time KPIs. This design approach was presented during > LinaroConnect 2024 conference[1]. > > Architecture: > ------------ > +--------------------+ > | Shared Memory | > | | > | +----------------+ | +----------------------------------+ > +----------------------------+ +-+-> ufs-shmem <-+---+ | Linux VM | > | Firmware VM | | | +----------------+ | | | +----------+ +----------+ | > | | | | | | | | UFS | | PCIe | | > | +---------+ f +----------+ | | | | | | | Driver | | Driver | | > | |Drivers <---+ SCMI | | e | | | | | | +--+----^--+ +----------+ | > | | (clks, | g | Server +-+---------------------+ | | | | | | | > | | vreg, +---> | | h | | | b|k | a| l| | > | | gpio, | +--^-----+-+ | | | | | | | | > | | phy, | | | | | | | | | +---v----+----+ +----------+ | > | | etc.) | | | | | | +------------+--+ UFS SCMI | | PCIe SCMI| | > | +---------+ | | | | | | | INSTANCE | | INSTANCE | | > | | | | | +---------------+ | | +-^-----+-----+ +----------+ | > | | | | | | pcie-shmem | | | | | | > +------------------+-----+---+ | +---------------+ | +----+-----+-----------------------+ > | | | | | | > | | +--------------------+ | | > d|IRQ i|HVC j|IRQ c|HVC > | | | | > | | | | > +-----------------------+-----v----------------------------------------------------------------------+-----v------------------------------+ > | | > | | > | | > | HYPERVISOR | > | | > | | > +-----------------------------------------------------------------------------------------------------------------------------------------+ > > +--------+ +--------+ +----------+ +-----------+ > | CLOCK | | PHY | | UFS | | PCIe | > +--------+ +--------+ +----------+ +-----------+ > > > This series is based on next-20240903. > > [1]: https://resources.linaro.org/en/resource/wfnfEwBhRjLV1PEAJoDDte > > --- > Changes in v2: > - Patch 1/21 - 11/21 > - Added Reviewed-by tag > > - Patch 12/21 > - Already applied in the maintainers tree > > - Patch 13/21 > - Modified subject line > - Fixed schema to include fallback > > - Patch 14/21 > - Added constraints > > - Patch 15/21 > - Modified schema to remove useless text > > - Patch 16/21 > - Modified schema formatting > - Amended schema definition as advised > > - Patch 17/21 > - Moved allOf block after required > - Fixed formatting > - Modified schema to remove useless text > > - Patch 18/21 > - Fixed clock property changes > > - Patch 19/21 > - Fixed scmi nodename pattern > > - Patch 20/21 > - Modified subject line and description > - Added EPPI macro > > - Patch 21/21 > - Removed scmichannels label and alias > - Modified scmi node name to conform to schema > - Moved status property to be the last one in scmi instances > - Changed to lower case for cpu labels > - Added fallback compatible for tlmm node > > Nikunj Kela (21): > dt-bindings: arm: qcom: add the SoC ID for SA8255P > soc: qcom: socinfo: add support for SA8255P > dt-bindings: arm: qcom: add SA8255p Ride board > dt-bindings: firmware: qcom,scm: document support for SA8255p > dt-bindings: mailbox: qcom-ipcc: document the support for SA8255p > dt-bindings: watchdog: qcom-wdt: document support on SA8255p > dt-bindings: crypto: qcom,prng: document support for SA8255p > dt-bindings: interrupt-controller: qcom-pdc: document support for > SA8255p > dt-bindings: soc: qcom: aoss-qmp: document support for SA8255p > dt-bindings: arm-smmu: document the support on SA8255p > dt-bindings: mfd: qcom,tcsr: document support for SA8255p > dt-bindings: thermal: tsens: document support on SA8255p > dt-bindings: pinctrl: Add SA8255p TLMM > dt-bindings: cpufreq: qcom-hw: document support for SA8255p > dt-bindings: i2c: document support for SA8255p > dt-bindings: spi: document support for SA8255p > dt-bindings: serial: document support for SA8255p > dt-bindings: qcom: geni-se: document support for SA8255P > dt-bindings: firmware: arm,scmi: allow multiple virtual instances > dt-bindings: arm: GIC: add ESPI and EPPI specifiers > arm64: dts: qcom: Add reduced functional DT for SA8255p Ride platform > > .../devicetree/bindings/arm/qcom.yaml | 6 + > .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 16 + > .../devicetree/bindings/crypto/qcom,prng.yaml | 1 + > .../bindings/firmware/arm,scmi.yaml | 2 +- > .../bindings/firmware/qcom,scm.yaml | 2 + > .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 33 +- > .../interrupt-controller/qcom,pdc.yaml | 1 + > .../devicetree/bindings/iommu/arm,smmu.yaml | 3 + > .../bindings/mailbox/qcom-ipcc.yaml | 1 + > .../devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + > .../bindings/pinctrl/qcom,sa8775p-tlmm.yaml | 8 +- > .../serial/qcom,serial-geni-qcom.yaml | 53 +- > .../bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 + > .../bindings/soc/qcom/qcom,geni-se.yaml | 45 +- > .../bindings/spi/qcom,spi-geni-qcom.yaml | 60 +- > .../bindings/thermal/qcom-tsens.yaml | 1 + > .../bindings/watchdog/qcom-wdt.yaml | 1 + > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi | 80 + > arch/arm64/boot/dts/qcom/sa8255p-ride.dts | 148 + > arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi | 2312 ++++++++++++++++ > arch/arm64/boot/dts/qcom/sa8255p.dtsi | 2405 +++++++++++++++++ > drivers/soc/qcom/socinfo.c | 1 + > include/dt-bindings/arm/qcom,ids.h | 1 + > .../interrupt-controller/arm-gic.h | 2 + > 25 files changed, 5169 insertions(+), 16 deletions(-) > create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi > create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts > create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi > create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi > > > base-commit: 6804f0edbe7747774e6ae60f20cec4ee3ad7c187
On 04/09/2024 23:54, Andrew Lunn wrote: >> No one is born with experience. You learn as you go. Please note that >> this series has gone through internal review before I posted it in >> upstream. > > Then i'm surprise you were not told to submit lots of smaller > patchsets, one per subsystem, which are complete. We did... multiple times. We gave examples how entire new Qualcomm SoC should be upstreamed, how this process should be organized. We gave trainings. Some listen, some not. Sometimes people do not even come to a training (for free). But there will be always an excuse for patchset doing something entirely different than community expects... The patchset here is a result of some misconceptions and not understanding what is the dependency (claiming there is while there is no) and what are the maintainer trees. > > I get nobody is born with experience, but for a company the size of > Qualcomm, they can easily hire a few experienced mainline developers > who can mentor you, rather than having overloaded Maintainers teach > you the basics, and getting frustrated in the process. Best regards, Krzysztof
On Wed, Sep 04, 2024 at 05:48:35AM GMT, Nikunj Kela wrote: > > On 9/3/2024 11:34 PM, Krzysztof Kozlowski wrote: > > On Tue, Sep 03, 2024 at 03:02:35PM -0700, Nikunj Kela wrote: > >> Add compatible representing spi support on SA8255p. > >> > >> Clocks and interconnects are being configured in firmware VM > >> on SA8255p platform, therefore making them optional. > >> > > Please use standard email subjects, so with the PATCH keyword in the > > title. helps here to create proper versioned patches. > Where did I miss PATCH keyword in the subject here? It says "[PATCH v2 > 16/21] dt-bindings: spi: document support for SA8255p" > > Another useful tool is b4. Skipping the PATCH keyword makes filtering of > > emails more difficult thus making the review process less convenient. > > > > > >> CC: Praveen Talari <quic_ptalari@quicinc.com> > >> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com> > >> --- > >> .../bindings/spi/qcom,spi-geni-qcom.yaml | 60 +++++++++++++++++-- > >> 1 file changed, 56 insertions(+), 4 deletions(-) > >> > >> properties: > >> compatible: > >> - const: qcom,geni-spi > >> + enum: > >> + - qcom,geni-spi > >> + - qcom,sa8255p-geni-spi > > You have entire commit msg to explain why this device's programming > > model is not compatible with existing generic compatible which must > > cover all variants (because it is crazy generic). > > > > Best regards, > > Krzysztof > > I will put more details in the description of the patch, though, I had > put the description in the cover letter for this entire series. Cover letters do not land in the git repo, so the next person coming to perform modifications can not understand what was so special about this platform. Please always provide all reasoning for a change in the commit message.
On 9/5/2024 1:04 AM, Krzysztof Kozlowski wrote: > On 04/09/2024 23:06, Nikunj Kela wrote: >> On 9/4/2024 9:58 AM, Andrew Lunn wrote: >>>> Sorry, didn't realize SPI uses different subject format than other >>>> subsystems. Will fix in v3. Thanks >>> Each subsystem is free to use its own form. e.g for netdev you will >>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos: >> of course they are! No one is disputing that. >>> This is another reason why you should be splitting these patches per >>> subsystem, and submitting both the DT bindings and the code changes as >>> a two patch patchset. You can then learn how each subsystem names its >>> patches. >> Qualcomm QUPs chips have serial engines that can be configured as >> UART/I2C/SPI so QUPs changes require to be pushed in one series for all >> 3 subsystems as they all are dependent. > No, they are not dependent. They have never been. Look how all other > upstreaming process worked in the past. Top level QUP node(patch#18) includes i2c,spi,uart nodes. soc/qcom/qcom,geni-se.yaml validate those subnodes against respective yaml. The example that is added in YAML file for QUP node will not find sa8255p compatibles if all 4 yaml(qup, i2c, spi, serial nodes) are not included in the same series. > > Best regards, > Krzysztof >
On 05/09/2024 16:15, Nikunj Kela wrote: > > On 9/5/2024 7:09 AM, Krzysztof Kozlowski wrote: >> On 05/09/2024 16:03, Nikunj Kela wrote: >>> On 9/5/2024 1:04 AM, Krzysztof Kozlowski wrote: >>>> On 04/09/2024 23:06, Nikunj Kela wrote: >>>>> On 9/4/2024 9:58 AM, Andrew Lunn wrote: >>>>>>> Sorry, didn't realize SPI uses different subject format than other >>>>>>> subsystems. Will fix in v3. Thanks >>>>>> Each subsystem is free to use its own form. e.g for netdev you will >>>>>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos: >>>>> of course they are! No one is disputing that. >>>>>> This is another reason why you should be splitting these patches per >>>>>> subsystem, and submitting both the DT bindings and the code changes as >>>>>> a two patch patchset. You can then learn how each subsystem names its >>>>>> patches. >>>>> Qualcomm QUPs chips have serial engines that can be configured as >>>>> UART/I2C/SPI so QUPs changes require to be pushed in one series for all >>>>> 3 subsystems as they all are dependent. >>>> No, they are not dependent. They have never been. Look how all other >>>> upstreaming process worked in the past. >>> Top level QUP node(patch#18) includes i2c,spi,uart nodes. >>> soc/qcom/qcom,geni-se.yaml validate those subnodes against respective >>> yaml. The example that is added in YAML file for QUP node will not find >>> sa8255p compatibles if all 4 yaml(qup, i2c, spi, serial nodes) are not >>> included in the same series. >>> >> So where is the dependency? I don't see it. > > Ok, what is your suggestion on dt-schema check failure in that case as I > mentioned above? Shall we remove examples from yaml that we added? I don't understand what sort of failure you want to fix and why examples have any problem here. I said it multiple times already but I think you never confirmed. Do you understand how patches are merged? That they go via different trees but everything must be 100% bisectable? Best regards, Krzysztof
On 05/09/2024 16:15, Nikunj Kela wrote: > > On 9/5/2024 7:09 AM, Krzysztof Kozlowski wrote: >> On 05/09/2024 16:03, Nikunj Kela wrote: >>> On 9/5/2024 1:04 AM, Krzysztof Kozlowski wrote: >>>> On 04/09/2024 23:06, Nikunj Kela wrote: >>>>> On 9/4/2024 9:58 AM, Andrew Lunn wrote: >>>>>>> Sorry, didn't realize SPI uses different subject format than other >>>>>>> subsystems. Will fix in v3. Thanks >>>>>> Each subsystem is free to use its own form. e.g for netdev you will >>>>>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos: >>>>> of course they are! No one is disputing that. >>>>>> This is another reason why you should be splitting these patches per >>>>>> subsystem, and submitting both the DT bindings and the code changes as >>>>>> a two patch patchset. You can then learn how each subsystem names its >>>>>> patches. >>>>> Qualcomm QUPs chips have serial engines that can be configured as >>>>> UART/I2C/SPI so QUPs changes require to be pushed in one series for all >>>>> 3 subsystems as they all are dependent. >>>> No, they are not dependent. They have never been. Look how all other >>>> upstreaming process worked in the past. >>> Top level QUP node(patch#18) includes i2c,spi,uart nodes. >>> soc/qcom/qcom,geni-se.yaml validate those subnodes against respective >>> yaml. The example that is added in YAML file for QUP node will not find >>> sa8255p compatibles if all 4 yaml(qup, i2c, spi, serial nodes) are not >>> included in the same series. >>> >> So where is the dependency? I don't see it. > > Ok, what is your suggestion on dt-schema check failure in that case as I > mentioned above? Shall we remove examples from yaml that we added? > > >> Anyway, if you insist, >> provide reasons why this should be the only one patchset - from all >> SoCs, all companies, all developers - getting an exception from standard >> merging practice and from explicit rule about driver change. See >> submitting bindings. >> >> This was re-iterated over and over, but you keep claiming you need some >> sort of special treatment. If so, please provide arguments WHY this >> requires special treatment and *all* other contributions are fine with it. You did not respond to above about explaining why this patchset needs special treatment, so I assume there is no exception here to be granted so any new version will follow standard process (see submitting bindings / writing bindings). Best regards, Krzysztof
On 9/5/2024 7:39 AM, Krzysztof Kozlowski wrote: > On 05/09/2024 16:15, Nikunj Kela wrote: >> On 9/5/2024 7:09 AM, Krzysztof Kozlowski wrote: >>> On 05/09/2024 16:03, Nikunj Kela wrote: >>>> On 9/5/2024 1:04 AM, Krzysztof Kozlowski wrote: >>>>> On 04/09/2024 23:06, Nikunj Kela wrote: >>>>>> On 9/4/2024 9:58 AM, Andrew Lunn wrote: >>>>>>>> Sorry, didn't realize SPI uses different subject format than other >>>>>>>> subsystems. Will fix in v3. Thanks >>>>>>> Each subsystem is free to use its own form. e.g for netdev you will >>>>>>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos: >>>>>> of course they are! No one is disputing that. >>>>>>> This is another reason why you should be splitting these patches per >>>>>>> subsystem, and submitting both the DT bindings and the code changes as >>>>>>> a two patch patchset. You can then learn how each subsystem names its >>>>>>> patches. >>>>>> Qualcomm QUPs chips have serial engines that can be configured as >>>>>> UART/I2C/SPI so QUPs changes require to be pushed in one series for all >>>>>> 3 subsystems as they all are dependent. >>>>> No, they are not dependent. They have never been. Look how all other >>>>> upstreaming process worked in the past. >>>> Top level QUP node(patch#18) includes i2c,spi,uart nodes. >>>> soc/qcom/qcom,geni-se.yaml validate those subnodes against respective >>>> yaml. The example that is added in YAML file for QUP node will not find >>>> sa8255p compatibles if all 4 yaml(qup, i2c, spi, serial nodes) are not >>>> included in the same series. >>>> >>> So where is the dependency? I don't see it. >> Ok, what is your suggestion on dt-schema check failure in that case as I >> mentioned above? Shall we remove examples from yaml that we added? > I don't understand what sort of failure you want to fix and why examples > have any problem here. If the QUPs yaml changes are not included in the same series with i2c,serial yaml changes, you see these errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: serial@990000:compatible:0: 'qcom,sa8255p-geni-uart' is not one of ['qcom,geni-uart', 'qcom,geni-debug-uart'] /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: i2c@984000:compatible:0: 'qcom,sa8255p-geni-i2c' is not one of ['qcom,geni-i2c', 'qcom,geni-i2c-master-hub'] > I said it multiple times already but I think you > never confirmed. Do you understand how patches are merged? That they go > via different trees but everything must be 100% bisectable? > > Best regards, > Krzysztof >
On 05/09/2024 18:56, Krzysztof Kozlowski wrote: > On 05/09/2024 18:08, Nikunj Kela wrote: >> >> On 9/5/2024 7:39 AM, Krzysztof Kozlowski wrote: >>> On 05/09/2024 16:15, Nikunj Kela wrote: >>>> On 9/5/2024 7:09 AM, Krzysztof Kozlowski wrote: >>>>> On 05/09/2024 16:03, Nikunj Kela wrote: >>>>>> On 9/5/2024 1:04 AM, Krzysztof Kozlowski wrote: >>>>>>> On 04/09/2024 23:06, Nikunj Kela wrote: >>>>>>>> On 9/4/2024 9:58 AM, Andrew Lunn wrote: >>>>>>>>>> Sorry, didn't realize SPI uses different subject format than other >>>>>>>>>> subsystems. Will fix in v3. Thanks >>>>>>>>> Each subsystem is free to use its own form. e.g for netdev you will >>>>>>>>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos: >>>>>>>> of course they are! No one is disputing that. >>>>>>>>> This is another reason why you should be splitting these patches per >>>>>>>>> subsystem, and submitting both the DT bindings and the code changes as >>>>>>>>> a two patch patchset. You can then learn how each subsystem names its >>>>>>>>> patches. >>>>>>>> Qualcomm QUPs chips have serial engines that can be configured as >>>>>>>> UART/I2C/SPI so QUPs changes require to be pushed in one series for all >>>>>>>> 3 subsystems as they all are dependent. >>>>>>> No, they are not dependent. They have never been. Look how all other >>>>>>> upstreaming process worked in the past. >>>>>> Top level QUP node(patch#18) includes i2c,spi,uart nodes. >>>>>> soc/qcom/qcom,geni-se.yaml validate those subnodes against respective >>>>>> yaml. The example that is added in YAML file for QUP node will not find >>>>>> sa8255p compatibles if all 4 yaml(qup, i2c, spi, serial nodes) are not >>>>>> included in the same series. >>>>>> >>>>> So where is the dependency? I don't see it. >>>> Ok, what is your suggestion on dt-schema check failure in that case as I >>>> mentioned above? Shall we remove examples from yaml that we added? >>> I don't understand what sort of failure you want to fix and why examples >>> have any problem here. >> >> If the QUPs yaml changes are not included in the same series with > > They cannot be included in the same series. You just think that > including here solves the problem so go ahead, simulate the merging: > 1. Bjorn applies soc/qcom/qcom,geni-se.yaml patch and tests. His tree > MUST build, so it also must pass dt_binding_check. > Does it pass? No. > > 2. SPI maintainer... ah, no point even going there. > >> i2c,serial yaml changes, you see these errors: >> >> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: serial@990000:compatible:0: 'qcom,sa8255p-geni-uart' is not one of ['qcom,geni-uart', 'qcom,geni-debug-uart'] >> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: i2c@984000:compatible:0: 'qcom,sa8255p-geni-i2c' is not one of ['qcom,geni-i2c', 'qcom,geni-i2c-master-hub'] > > Don't grow examples if not needed. Or create dependencies and ask > maintainers to cross-merge. Or soc/geni-se binding could be also converted to just list compatibles instead of referencing other schema, just like MDSS. Best regards, Krzysztof
On 9/4/2024 6:21 AM, Krzysztof Kozlowski wrote: > On 04/09/2024 14:48, Nikunj Kela wrote: >> On 9/3/2024 11:34 PM, Krzysztof Kozlowski wrote: >>> On Tue, Sep 03, 2024 at 03:02:35PM -0700, Nikunj Kela wrote: >>>> Add compatible representing spi support on SA8255p. >>>> >>>> Clocks and interconnects are being configured in firmware VM >>>> on SA8255p platform, therefore making them optional. >>>> >>> Please use standard email subjects, so with the PATCH keyword in the >>> title. helps here to create proper versioned patches. >> Where did I miss PATCH keyword in the subject here? It says "[PATCH v2 >> 16/21] dt-bindings: spi: document support for SA8255p" > Oh, wrong template. It was about spi prefix, These are the latest 4 commits in linux-next for spi: 12736adc43b7 dt-bindings: spi: nxp-fspi: add imx8ulp support b0cdf9cc0895 spi: dt-bindings: Add rockchip,rk3576-spi compatible d6d0af1b9eff dt-bindings: spi: add PIC64GX SPI/QSPI compatibility to MPFS SPI/QSPI bindings 1c4d834e4e81 spi: dt-bindings: convert spi-sc18is602.txt to yaml format Now I am confused which prefix format shall I use? first spi or first dt-bindings? > should be this one: > > Please use subject prefixes matching the subsystem. You can get them for > example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory > your patch is touching. For bindings, the preferred subjects are > explained here: > https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters > > Best regards, > Krzysztof >
On Mon, Sep 09, 2024 at 01:29:37PM -0700, Nikunj Kela wrote: > Now I am confused which prefix format shall I use? first spi or first > dt-bindings? spi: first.
This series enables the support for SA8255p Qualcomm SoC and Ride platform. This platform uses SCMI power, reset, performance, sensor protocols for resources(e.g. clocks, regulator, interconnect, phy etc.) management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc transport driver. Multiple virtual SCMI instances are being used to achieve the parallelism. SCMI platform stack runs in SMP enabled VM hence allows platform to service multiple resource requests in parallel. Each device is assigned its own dedicated SCMI channel and Tx/Rx doorbells. Resource operations are grouped together to achieve better abstraction and to reduce the number of requests being sent to SCMI platform(server) thus improving boot time KPIs. This design approach was presented during LinaroConnect 2024 conference[1]. Architecture: ------------ +--------------------+ | Shared Memory | | | | +----------------+ | +----------------------------------+ +----------------------------+ +-+-> ufs-shmem <-+---+ | Linux VM | | Firmware VM | | | +----------------+ | | | +----------+ +----------+ | | | | | | | | | UFS | | PCIe | | | +---------+ f +----------+ | | | | | | | Driver | | Driver | | | |Drivers <---+ SCMI | | e | | | | | | +--+----^--+ +----------+ | | | (clks, | g | Server +-+---------------------+ | | | | | | | | | vreg, +---> | | h | | | b|k | a| l| | | | gpio, | +--^-----+-+ | | | | | | | | | | phy, | | | | | | | | | +---v----+----+ +----------+ | | | etc.) | | | | | | +------------+--+ UFS SCMI | | PCIe SCMI| | | +---------+ | | | | | | | INSTANCE | | INSTANCE | | | | | | | +---------------+ | | +-^-----+-----+ +----------+ | | | | | | | pcie-shmem | | | | | | +------------------+-----+---+ | +---------------+ | +----+-----+-----------------------+ | | | | | | | | +--------------------+ | | d|IRQ i|HVC j|IRQ c|HVC | | | | | | | | +-----------------------+-----v----------------------------------------------------------------------+-----v------------------------------+ | | | | | | | HYPERVISOR | | | | | +-----------------------------------------------------------------------------------------------------------------------------------------+ +--------+ +--------+ +----------+ +-----------+ | CLOCK | | PHY | | UFS | | PCIe | +--------+ +--------+ +----------+ +-----------+ This series is based on next-20240828. [1]: https://resources.linaro.org/en/resource/wfnfEwBhRjLV1PEAJoDDte Nikunj Kela (22): dt-bindings: arm: qcom: add the SoC ID for SA8255P soc: qcom: socinfo: add support for SA8255P dt-bindings: arm: qcom: add SA8255p Ride board dt-bindings: firmware: qcom,scm: document support for SA8255p dt-bindings: mailbox: qcom-ipcc: document the support for SA8255p dt-bindings: watchdog: qcom-wdt: document support on SA8255p dt-bindings: crypto: qcom,prng: document support for SA8255p dt-bindings: interrupt-controller: qcom-pdc: document support for SA8255p dt-bindings: soc: qcom: aoss-qmp: document support for SA8255p dt-bindings: pinctrl: document support for SA8255p pinctrl: qcom: sa8775p: Add support for SA8255p SoC dt-bindings: cpufreq: qcom-hw: document support for SA8255p dt-bindings: thermal: tsens: document support on SA8255p dt-bindings: arm-smmu: document the support on SA8255p dt-bindings: mfd: qcom,tcsr: document support for SA8255p dt-bindings: qcom: geni-se: document support for SA8255P dt-bindings: serial: document support for SA8255p dt-bindings: spi: document support for SA8255p dt-bindings: i2c: document support for SA8255p dt-bindings: firmware: arm,scmi: allow multiple virtual instances ARM: dt: GIC: add extended SPI specifier arm64: dts: qcom: Add reduced functional DT for SA8255p Ride platform .../devicetree/bindings/arm/qcom.yaml | 6 + .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 + .../devicetree/bindings/crypto/qcom,prng.yaml | 1 + .../bindings/firmware/arm,scmi.yaml | 2 +- .../bindings/firmware/qcom,scm.yaml | 2 + .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 56 +- .../interrupt-controller/qcom,pdc.yaml | 1 + .../devicetree/bindings/iommu/arm,smmu.yaml | 3 + .../bindings/mailbox/qcom-ipcc.yaml | 1 + .../devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + .../bindings/pinctrl/qcom,sa8775p-tlmm.yaml | 4 +- .../serial/qcom,serial-geni-qcom.yaml | 58 +- .../bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 + .../bindings/soc/qcom/qcom,geni-se.yaml | 47 +- .../bindings/spi/qcom,spi-geni-qcom.yaml | 64 +- .../bindings/thermal/qcom-tsens.yaml | 1 + .../bindings/watchdog/qcom-wdt.yaml | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi | 80 + arch/arm64/boot/dts/qcom/sa8255p-ride.dts | 149 + arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi | 2312 ++++++++++++++++ arch/arm64/boot/dts/qcom/sa8255p.dtsi | 2405 +++++++++++++++++ drivers/pinctrl/qcom/pinctrl-sa8775p.c | 1 + drivers/soc/qcom/socinfo.c | 1 + include/dt-bindings/arm/qcom,ids.h | 1 + .../interrupt-controller/arm-gic.h | 1 + 26 files changed, 5157 insertions(+), 44 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi base-commit: 195a402a75791e6e0d96d9da27ca77671bc656a8