| Message ID | 20240803-qps615-v2-3-9560b7c71369@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: Enable Power and configure the QPS615 PCIe switch | expand |
On 03/08/2024 05:22, Krishna chaitanya chundru wrote: > Add QPS615 PCIe switch node which has 3 downstream ports and in one > downstream port two embedded ethernet devices are present. > > Power to the QPS615 is supplied through two LDO regulators, controlled > by two GPIOs, these are added as fixed regulators. > > Add i2c device node which is used to configure the switch. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 121 +++++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- > 2 files changed, 122 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > index 0d45662b8028..59d209768636 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > @@ -202,6 +202,30 @@ vph_pwr: vph-pwr-regulator { > regulator-min-microvolt = <3700000>; > regulator-max-microvolt = <3700000>; > }; > + > + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { > + compatible = "regulator-fixed"; > + regulator-name = "VDD_NTN_0P9"; > + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; > + regulator-min-microvolt = <899400>; > + regulator-max-microvolt = <899400>; > + enable-active-high; > + pinctrl-0 = <&ntn_0p9_en>; > + pinctrl-names = "default"; > + regulator-enable-ramp-delay = <4300>; > + }; > + > + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { > + compatible = "regulator-fixed"; > + regulator-name = "VDD_NTN_1P8"; > + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + enable-active-high; > + pinctrl-0 = <&ntn_1p8_en>; > + pinctrl-names = "default"; > + regulator-enable-ramp-delay = <10000>; > + }; > }; > > &apps_rsc { > @@ -595,6 +619,12 @@ lt9611_out: endpoint { > }; > }; > }; > + > + qps615_switch: pcie-switch@77 { > + compatible = "qcom,qps615"; > + reg = <0x77>; > + status = "okay"; Where is it disabled? > + }; > }; > > &i2c1 { > @@ -688,6 +718,75 @@ &pmk8350_rtc { > status = "okay"; > }; > > +&pcie1 { Entries are ordered. > + status = "okay"; > +}; > Best regards, Krzysztof
On 8/4/2024 2:24 PM, Krzysztof Kozlowski wrote: > On 03/08/2024 05:22, Krishna chaitanya chundru wrote: >> Add QPS615 PCIe switch node which has 3 downstream ports and in one >> downstream port two embedded ethernet devices are present. >> >> Power to the QPS615 is supplied through two LDO regulators, controlled >> by two GPIOs, these are added as fixed regulators. >> >> Add i2c device node which is used to configure the switch. >> >> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 121 +++++++++++++++++++++++++++ >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- >> 2 files changed, 122 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> index 0d45662b8028..59d209768636 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> @@ -202,6 +202,30 @@ vph_pwr: vph-pwr-regulator { >> regulator-min-microvolt = <3700000>; >> regulator-max-microvolt = <3700000>; >> }; >> + >> + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { >> + compatible = "regulator-fixed"; >> + regulator-name = "VDD_NTN_0P9"; >> + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; >> + regulator-min-microvolt = <899400>; >> + regulator-max-microvolt = <899400>; >> + enable-active-high; >> + pinctrl-0 = <&ntn_0p9_en>; >> + pinctrl-names = "default"; >> + regulator-enable-ramp-delay = <4300>; >> + }; >> + >> + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { >> + compatible = "regulator-fixed"; >> + regulator-name = "VDD_NTN_1P8"; >> + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; >> + regulator-min-microvolt = <1800000>; >> + regulator-max-microvolt = <1800000>; >> + enable-active-high; >> + pinctrl-0 = <&ntn_1p8_en>; >> + pinctrl-names = "default"; >> + regulator-enable-ramp-delay = <10000>; >> + }; >> }; >> >> &apps_rsc { >> @@ -595,6 +619,12 @@ lt9611_out: endpoint { >> }; >> }; >> }; >> + >> + qps615_switch: pcie-switch@77 { >> + compatible = "qcom,qps615"; >> + reg = <0x77>; >> + status = "okay"; > > Where is it disabled? > let me check this, I taught if we are using a phandle it should be enabled, if not the case I will make it as disabled only. >> + }; >> }; >> >> &i2c1 { >> @@ -688,6 +718,75 @@ &pmk8350_rtc { >> status = "okay"; >> }; >> >> +&pcie1 { > > Entries are ordered. > ack. -- Krishna Chaitanya. >> + status = "okay"; >> +}; > > >> > > Best regards, > Krzysztof >
Hi Krishna, On 03/08/2024 05:22, Krishna chaitanya chundru wrote: > Add QPS615 PCIe switch node which has 3 downstream ports and in one > downstream port two embedded ethernet devices are present. > > Power to the QPS615 is supplied through two LDO regulators, controlled > by two GPIOs, these are added as fixed regulators. > > Add i2c device node which is used to configure the switch. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 121 +++++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- > 2 files changed, 122 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > index 0d45662b8028..59d209768636 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > @@ -202,6 +202,30 @@ vph_pwr: vph-pwr-regulator { > regulator-min-microvolt = <3700000>; > regulator-max-microvolt = <3700000>; > }; > + > + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { > + compatible = "regulator-fixed"; > + regulator-name = "VDD_NTN_0P9"; > + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; > + regulator-min-microvolt = <899400>; > + regulator-max-microvolt = <899400>; > + enable-active-high; > + pinctrl-0 = <&ntn_0p9_en>; > + pinctrl-names = "default"; > + regulator-enable-ramp-delay = <4300>; > + }; > + > + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { > + compatible = "regulator-fixed"; > + regulator-name = "VDD_NTN_1P8"; > + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + enable-active-high; > + pinctrl-0 = <&ntn_1p8_en>; > + pinctrl-names = "default"; > + regulator-enable-ramp-delay = <10000>; > + }; > }; > > &apps_rsc { > @@ -595,6 +619,12 @@ lt9611_out: endpoint { > }; > }; > }; > + > + qps615_switch: pcie-switch@77 { > + compatible = "qcom,qps615"; > + reg = <0x77>; > + status = "okay"; > + }; > }; > > &i2c1 { > @@ -688,6 +718,75 @@ &pmk8350_rtc { > status = "okay"; > }; > > +&pcie1 { > + status = "okay"; > +}; Isn't it also necessary to configure the phy as well? It's also default disabled and has two regulators. Kind regards, > + > +&pcieport { > + pcie@0,0 { > + compatible = "pci1179,0623"; > + reg = <0x10000 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + device_type = "pci"; > + ranges; > + > + vddc-supply = <&vdd_ntn_0p9>; > + vdd18-supply = <&vdd_ntn_1p8>; > + vdd09-supply = <&vdd_ntn_0p9>; > + vddio1-supply = <&vdd_ntn_1p8>; > + vddio2-supply = <&vdd_ntn_1p8>; > + vddio18-supply = <&vdd_ntn_1p8>; > + > + qcom,qps615-controller = <&qps615_switch>; > + > + reset-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; > + > + pcie@1,0 { > + reg = <0x20800 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + device_type = "pci"; > + ranges; > + }; > + > + pcie@2,0 { > + reg = <0x21000 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + device_type = "pci"; > + ranges; > + }; > + > + pcie@3,0 { > + reg = <0x21800 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges; > + > + pcie@0,0 { > + reg = <0x50000 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges; > + }; > + > + pcie@0,1 { > + reg = <0x50100 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges; > + }; > + }; > + }; > +}; > + > &qupv3_id_0 { > status = "okay"; > }; > @@ -812,6 +911,28 @@ lt9611_rst_pin: lt9611-rst-state { > }; > }; > > +&pm8350c_gpios { > + ntn_0p9_en: ntn-0p9-en-state { > + pins = "gpio2"; > + function = "normal"; > + > + bias-disable; > + input-disable; > + output-enable; > + power-source = <0>; > + }; > + > + ntn_1p8_en: ntn-1p8-en-state { > + pins = "gpio3"; > + function = "normal"; > + > + bias-disable; > + input-disable; > + output-enable; > + power-source = <0>; > + }; > +}; > + > &tlmm { > lt9611_irq_pin: lt9611-irq-state { > pins = "gpio24"; > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 3d8410683402..3840f056b7f2 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -2279,7 +2279,7 @@ pcie1: pcie@1c08000 { > > status = "disabled"; > > - pcie@0 { > + pcieport: pcie@0 { > device_type = "pci"; > reg = <0x0 0x0 0x0 0x0 0x0>; > bus-range = <0x01 0xff>; >
On 9/9/2024 4:59 PM, Caleb Connolly wrote: > Hi Krishna, > > On 03/08/2024 05:22, Krishna chaitanya chundru wrote: >> Add QPS615 PCIe switch node which has 3 downstream ports and in one >> downstream port two embedded ethernet devices are present. >> >> Power to the QPS615 is supplied through two LDO regulators, controlled >> by two GPIOs, these are added as fixed regulators. >> >> Add i2c device node which is used to configure the switch. >> >> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 121 +++++++++++++++++++++++++++ >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- >> 2 files changed, 122 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> index 0d45662b8028..59d209768636 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> @@ -202,6 +202,30 @@ vph_pwr: vph-pwr-regulator { >> regulator-min-microvolt = <3700000>; >> regulator-max-microvolt = <3700000>; >> }; >> + >> + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { >> + compatible = "regulator-fixed"; >> + regulator-name = "VDD_NTN_0P9"; >> + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; >> + regulator-min-microvolt = <899400>; >> + regulator-max-microvolt = <899400>; >> + enable-active-high; >> + pinctrl-0 = <&ntn_0p9_en>; >> + pinctrl-names = "default"; >> + regulator-enable-ramp-delay = <4300>; >> + }; >> + >> + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { >> + compatible = "regulator-fixed"; >> + regulator-name = "VDD_NTN_1P8"; >> + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; >> + regulator-min-microvolt = <1800000>; >> + regulator-max-microvolt = <1800000>; >> + enable-active-high; >> + pinctrl-0 = <&ntn_1p8_en>; >> + pinctrl-names = "default"; >> + regulator-enable-ramp-delay = <10000>; >> + }; >> }; >> >> &apps_rsc { >> @@ -595,6 +619,12 @@ lt9611_out: endpoint { >> }; >> }; >> }; >> + >> + qps615_switch: pcie-switch@77 { >> + compatible = "qcom,qps615"; >> + reg = <0x77>; >> + status = "okay"; >> + }; >> }; >> >> &i2c1 { >> @@ -688,6 +718,75 @@ &pmk8350_rtc { >> status = "okay"; >> }; >> >> +&pcie1 { >> + status = "okay"; >> +}; > > Isn't it also necessary to configure the phy as well? It's also default > disabled and has two regulators. > There is one more patch series which does this. https://lore.kernel.org/linux-arm-msm/20240207-enable_pcie-v1-1-b684afa6371c@quicinc.com/T/ sorry for this I should have included this in cover letter. I will squash those changes to this series or will update the cover letter. - Krishna Chaitanya. > Kind regards >> + >> +&pcieport { >> + pcie@0,0 { >> + compatible = "pci1179,0623"; >> + reg = <0x10000 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + >> + device_type = "pci"; >> + ranges; >> + >> + vddc-supply = <&vdd_ntn_0p9>; >> + vdd18-supply = <&vdd_ntn_1p8>; >> + vdd09-supply = <&vdd_ntn_0p9>; >> + vddio1-supply = <&vdd_ntn_1p8>; >> + vddio2-supply = <&vdd_ntn_1p8>; >> + vddio18-supply = <&vdd_ntn_1p8>; >> + >> + qcom,qps615-controller = <&qps615_switch>; >> + >> + reset-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; >> + >> + pcie@1,0 { >> + reg = <0x20800 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + >> + device_type = "pci"; >> + ranges; >> + }; >> + >> + pcie@2,0 { >> + reg = <0x21000 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + >> + device_type = "pci"; >> + ranges; >> + }; >> + >> + pcie@3,0 { >> + reg = <0x21800 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; >> + ranges; >> + >> + pcie@0,0 { >> + reg = <0x50000 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; >> + ranges; >> + }; >> + >> + pcie@0,1 { >> + reg = <0x50100 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; >> + ranges; >> + }; >> + }; >> + }; >> +}; >> + >> &qupv3_id_0 { >> status = "okay"; >> }; >> @@ -812,6 +911,28 @@ lt9611_rst_pin: lt9611-rst-state { >> }; >> }; >> >> +&pm8350c_gpios { >> + ntn_0p9_en: ntn-0p9-en-state { >> + pins = "gpio2"; >> + function = "normal"; >> + >> + bias-disable; >> + input-disable; >> + output-enable; >> + power-source = <0>; >> + }; >> + >> + ntn_1p8_en: ntn-1p8-en-state { >> + pins = "gpio3"; >> + function = "normal"; >> + >> + bias-disable; >> + input-disable; >> + output-enable; >> + power-source = <0>; >> + }; >> +}; >> + >> &tlmm { >> lt9611_irq_pin: lt9611-irq-state { >> pins = "gpio24"; >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 3d8410683402..3840f056b7f2 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -2279,7 +2279,7 @@ pcie1: pcie@1c08000 { >> >> status = "disabled"; >> >> - pcie@0 { >> + pcieport: pcie@0 { >> device_type = "pci"; >> reg = <0x0 0x0 0x0 0x0 0x0>; >> bus-range = <0x01 0xff>; >> >
On Mon, Sep 09, 2024 at 05:21:22PM GMT, Krishna Chaitanya Chundru wrote: > > > On 9/9/2024 4:59 PM, Caleb Connolly wrote: > > Hi Krishna, > > > > On 03/08/2024 05:22, Krishna chaitanya chundru wrote: > > > Add QPS615 PCIe switch node which has 3 downstream ports and in one > > > downstream port two embedded ethernet devices are present. > > > > > > Power to the QPS615 is supplied through two LDO regulators, controlled > > > by two GPIOs, these are added as fixed regulators. > > > > > > Add i2c device node which is used to configure the switch. > > > > > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > > > --- > > > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 121 +++++++++++++++++++++++++++ > > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- > > > 2 files changed, 122 insertions(+), 1 deletion(-) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > > > index 0d45662b8028..59d209768636 100644 > > > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > > > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > > > @@ -202,6 +202,30 @@ vph_pwr: vph-pwr-regulator { > > > regulator-min-microvolt = <3700000>; > > > regulator-max-microvolt = <3700000>; > > > }; > > > + > > > + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { > > > + compatible = "regulator-fixed"; > > > + regulator-name = "VDD_NTN_0P9"; > > > + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; > > > + regulator-min-microvolt = <899400>; > > > + regulator-max-microvolt = <899400>; > > > + enable-active-high; > > > + pinctrl-0 = <&ntn_0p9_en>; > > > + pinctrl-names = "default"; > > > + regulator-enable-ramp-delay = <4300>; > > > + }; > > > + > > > + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { > > > + compatible = "regulator-fixed"; > > > + regulator-name = "VDD_NTN_1P8"; > > > + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; > > > + regulator-min-microvolt = <1800000>; > > > + regulator-max-microvolt = <1800000>; > > > + enable-active-high; > > > + pinctrl-0 = <&ntn_1p8_en>; > > > + pinctrl-names = "default"; > > > + regulator-enable-ramp-delay = <10000>; > > > + }; > > > }; > > > &apps_rsc { > > > @@ -595,6 +619,12 @@ lt9611_out: endpoint { > > > }; > > > }; > > > }; > > > + > > > + qps615_switch: pcie-switch@77 { > > > + compatible = "qcom,qps615"; > > > + reg = <0x77>; > > > + status = "okay"; > > > + }; > > > }; > > > &i2c1 { > > > @@ -688,6 +718,75 @@ &pmk8350_rtc { > > > status = "okay"; > > > }; > > > +&pcie1 { > > > + status = "okay"; > > > +}; > > > > Isn't it also necessary to configure the phy as well? It's also default > > disabled and has two regulators. > > > There is one more patch series which does this. > > https://lore.kernel.org/linux-arm-msm/20240207-enable_pcie-v1-1-b684afa6371c@quicinc.com/T/ > > sorry for this I should have included this in cover letter. > > I will squash those changes to this series or will update the cover > letter. It was sent in February, you have received feedback and several suggestions on how to change it. After that you've never reposted it. So, no, it is not possible to depend on that series or to include it in this patchset. Please follow the thread and rework that patch. > - Krishna Chaitanya. >
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 0d45662b8028..59d209768636 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -202,6 +202,30 @@ vph_pwr: vph-pwr-regulator { regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; }; + + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_0P9"; + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <899400>; + regulator-max-microvolt = <899400>; + enable-active-high; + pinctrl-0 = <&ntn_0p9_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <4300>; + }; + + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_1P8"; + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + pinctrl-0 = <&ntn_1p8_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <10000>; + }; }; &apps_rsc { @@ -595,6 +619,12 @@ lt9611_out: endpoint { }; }; }; + + qps615_switch: pcie-switch@77 { + compatible = "qcom,qps615"; + reg = <0x77>; + status = "okay"; + }; }; &i2c1 { @@ -688,6 +718,75 @@ &pmk8350_rtc { status = "okay"; }; +&pcie1 { + status = "okay"; +}; + +&pcieport { + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + + vddc-supply = <&vdd_ntn_0p9>; + vdd18-supply = <&vdd_ntn_1p8>; + vdd09-supply = <&vdd_ntn_0p9>; + vddio1-supply = <&vdd_ntn_1p8>; + vddio2-supply = <&vdd_ntn_1p8>; + vddio18-supply = <&vdd_ntn_1p8>; + + qcom,qps615-controller = <&qps615_switch>; + + reset-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + + pcie@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pcie@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + &qupv3_id_0 { status = "okay"; }; @@ -812,6 +911,28 @@ lt9611_rst_pin: lt9611-rst-state { }; }; +&pm8350c_gpios { + ntn_0p9_en: ntn-0p9-en-state { + pins = "gpio2"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; + + ntn_1p8_en: ntn-1p8-en-state { + pins = "gpio3"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; +}; + &tlmm { lt9611_irq_pin: lt9611-irq-state { pins = "gpio24"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3d8410683402..3840f056b7f2 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2279,7 +2279,7 @@ pcie1: pcie@1c08000 { status = "disabled"; - pcie@0 { + pcieport: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>;
Add QPS615 PCIe switch node which has 3 downstream ports and in one downstream port two embedded ethernet devices are present. Power to the QPS615 is supplied through two LDO regulators, controlled by two GPIOs, these are added as fixed regulators. Add i2c device node which is used to configure the switch. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 121 +++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 2 files changed, 122 insertions(+), 1 deletion(-)