| Message ID | 20240718034614.484018-6-alvinzhou.tw@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add octal DTR support for Macronix flash | expand |
On Thu, Jul 18, 2024 at 11:46:13AM +0800, AlvinZhou wrote: > From: AlvinZhou <alvinzhou@mxic.com.tw> > > Some SPI-NOR flash swap the bytes on a 16-bit boundary when > configured in Octal DTR mode. It means data format D0 D1 D2 D3 > would be swapped to D1 D0 D3 D2. So that whether controller > support swapping bytes should be checked before enable Octal > DTR mode. Add swap byte support on a 16-bit boundary when > configured in Octal DTR mode for Macronix xSPI host controller > dirver. driver Acked-by: Mark Brown <broonie@kernel.org>
Hi, Mark, On 9/24/24 12:38 PM, Mark Brown wrote: > On Thu, Jul 18, 2024 at 11:46:13AM +0800, AlvinZhou wrote: >> From: AlvinZhou <alvinzhou@mxic.com.tw> >> >> Some SPI-NOR flash swap the bytes on a 16-bit boundary when >> configured in Octal DTR mode. It means data format D0 D1 D2 D3 >> would be swapped to D1 D0 D3 D2. So that whether controller >> support swapping bytes should be checked before enable Octal >> DTR mode. Add swap byte support on a 16-bit boundary when >> configured in Octal DTR mode for Macronix xSPI host controller >> dirver. > > driver I can amend that. > > Acked-by: Mark Brown <broonie@kernel.org> I'm fine with the SPI bits as well. Shall I take the SPI/SPIMEM patches through mtd and provide you an immutable tag? I can do that after -rc1 is out. Or you can take them directly through spi/, but I'll need an immutable tag. Thanks, ta
On Tue, Sep 24, 2024 at 03:29:37PM +0100, Tudor Ambarus wrote: > On 9/24/24 12:38 PM, Mark Brown wrote: > > Acked-by: Mark Brown <broonie@kernel.org> > I'm fine with the SPI bits as well. Shall I take the SPI/SPIMEM patches > through mtd and provide you an immutable tag? I can do that after -rc1 > is out. > Or you can take them directly through spi/, but I'll need an immutable tag. If you apply and send me a pull request with the tag that should be good.
On 9/24/24 3:52 PM, Mark Brown wrote: > On Tue, Sep 24, 2024 at 03:29:37PM +0100, Tudor Ambarus wrote: >> On 9/24/24 12:38 PM, Mark Brown wrote: > >>> Acked-by: Mark Brown <broonie@kernel.org> > >> I'm fine with the SPI bits as well. Shall I take the SPI/SPIMEM patches >> through mtd and provide you an immutable tag? I can do that after -rc1 >> is out. > >> Or you can take them directly through spi/, but I'll need an immutable tag. > > If you apply and send me a pull request with the tag that should be > good. okay, will do, after -rc1 is out. Cheers, ta
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 6156d691630a..f4e2f506bb2a 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -294,7 +294,8 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic) mxic->regs + HC_CFG); } -static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags) +static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags, + bool swap16) { int nio = 1; @@ -305,6 +306,11 @@ static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags) else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) nio = 2; + if (swap16) + flags &= ~HC_CFG_DATA_PASS; + else + flags |= HC_CFG_DATA_PASS; + return flags | HC_CFG_NIO(nio) | HC_CFG_TYPE(spi_get_chipselect(spi, 0), HC_CFG_TYPE_SPI_NOR) | HC_CFG_SLV_ACT(spi_get_chipselect(spi, 0)) | HC_CFG_IDLE_SIO_LVL(1); @@ -397,7 +403,8 @@ static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc, if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) return -EINVAL; - writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); + writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16), + mxic->regs + HC_CFG); writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), mxic->regs + LRD_CFG); @@ -441,7 +448,8 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc, if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) return -EINVAL; - writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); + writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16), + mxic->regs + HC_CFG); writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), mxic->regs + LWR_CFG); @@ -518,7 +526,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, if (ret) return ret; - writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN), + writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN, op->data.swap16), mxic->regs + HC_CFG); writel(HC_EN_BIT, mxic->regs + HC_EN); @@ -572,6 +580,7 @@ static const struct spi_controller_mem_ops mxic_spi_mem_ops = { static const struct spi_controller_mem_caps mxic_spi_mem_caps = { .dtr = true, + .swap16 = true, .ecc = true, };