Message ID | 20240822152801.602318-8-claudiu.beznea.uj@bp.renesas.com |
---|---|
State | New |
Headers | show |
Series | Add initial USB support for the Renesas RZ/G3S SoC | expand |
On Thu, Aug 22, 2024 at 5:28 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Before accessing the USB area of the RZ/G3S SoC the PWRRDY bit of the > SYS_USB_PWRRDY register need to be cleared. When USB area is not used the > PWRRDY bit of the SYS_USB_PWRRDY register need to be set. This register is > in the SYSC controller address space and the assert/de-assert of the > signal handled by SYSC_USB_PWRRDY was implemented as a reset signal. > > The USB modules available on the RZ/G3S SoC that need this bit set are: > - USB ch0 (supporting host and peripheral mode) > - USB ch2 (supporting host mode) > - USBPHY control > > As the USBPHY control is the root device for all the other USB channels > (USB ch0, USB ch1) add support to set the PWRRDY for the USB area when > initializing the USBPHY control. As this is done though reset signals > get the reset array in the USBPHY control driver. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c index 1cd157f4f03b..8b64c12f3bec 100644 --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -132,7 +132,7 @@ static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); + priv->rstc = devm_reset_control_array_get_exclusive(&pdev->dev); if (IS_ERR(priv->rstc)) return dev_err_probe(dev, PTR_ERR(priv->rstc), "failed to get reset\n");