| Message ID | 20241009072001.509508-1-rui.zhang@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [V2] x86/apic: Stop the TSC Deadline timer during lapic timer shutdown | expand |
On Fri, Oct 11, 2024 at 2:43 AM Dave Hansen <dave.hansen@intel.com> wrote: > > How about something like the completely untested attached patch? > > IMNHO, it improves on what was posted here because it draws a parallel > with an AMD erratum and also avoids writes to APIC_TMICT that would get > ignored anyway. Please feel free to add Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> to this one when it's ready.
On Fri, 2024-10-11 at 12:25 +0200, Rafael J. Wysocki wrote: > On Fri, Oct 11, 2024 at 2:43 AM Dave Hansen <dave.hansen@intel.com> > wrote: > > > > How about something like the completely untested attached patch? > > > > IMNHO, it improves on what was posted here because it draws a > > parallel > > with an AMD erratum and also avoids writes to APIC_TMICT that would > > get > > ignored anyway. > > Please feel free to add > > Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> > > to this one when it's ready. Tested on Lunar Lake for the new patch Tested-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 6513c53c9459..d1006531729a 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -441,6 +441,10 @@ static int lapic_timer_shutdown(struct clock_event_device *evt) v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); apic_write(APIC_LVTT, v); apic_write(APIC_TMICT, 0); + + if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) + wrmsrl(MSR_IA32_TSC_DEADLINE, 0); + return 0; }
This 12-year-old bug prevents some modern processors from achieving maximum power savings during suspend. For example, Lunar Lake systems gets 0% package C-states during suspend to idle and this causes energy star compliance tests to fail. According to Intel SDM, for the local APIC timer, 1. "The initial-count register is a read-write register. A write of 0 to the initial-count register effectively stops the local APIC timer, in both one-shot and periodic mode." 2. "In TSC deadline mode, writes to the initial-count register are ignored; and current-count register always reads 0. Instead, timer behavior is controlled using the IA32_TSC_DEADLINE MSR." "In TSC-deadline mode, writing 0 to the IA32_TSC_DEADLINE MSR disarms the local-APIC timer." Stop the TSC Deadline timer in lapic_timer_shutdown() by writing 0 to MSR_IA32_TSC_DEADLINE. Cc: stable@vger.kernel.org Fixes: 279f1461432c ("x86: apic: Use tsc deadline for oneshot when available") Signed-off-by: Zhang Rui <rui.zhang@intel.com> --- Changes since V1 - improve changelog --- arch/x86/kernel/apic/apic.c | 4 ++++ 1 file changed, 4 insertions(+)