| Message ID | 20241017030412.265000-6-quic_qianyu@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for PCIe3 on x1e80100 | expand |
On Wed, Oct 16, 2024 at 08:04:10PM -0700, Qiang Yu wrote: > On SC8280X family SoC, PCIe controllers are connected to SMMUv3, hence > they don't need the config_sid() callback in ops_1_9_0 struct. Fix it by > introducing a new ops struct, namely ops_1_21_0 which is same as ops_1_9_0 > without config_sid() callback so that BDF2SID mapping won't be configured > during init. The sc8280xp PCIe devicetree nodes do not specify an 'iommu-map' so the config_sid() callback is effectively a no-op. Please rephrase this so that it becomes obvious that this is a clean up rather than fix. > Fixes: 70574511f3fc ("PCI: qcom: Add support for SC8280XP") And drop the Fixes tag. > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 88a98be930e3..468bd4242e61 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 = { > .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > }; > > +/* Qcom IP rev.: 1.21.0 */ Is this the actual IP revision on sc8280xp (and not just the revision used on x1e80100)? Please also provide the Synopsis IP rev like the other configs do. > +static const struct qcom_pcie_ops ops_1_21_0 = { > + .get_resources = qcom_pcie_get_resources_2_7_0, > + .init = qcom_pcie_init_2_7_0, > + .post_init = qcom_pcie_post_init_2_7_0, > + .host_post_init = qcom_pcie_host_post_init_2_7_0, > + .deinit = qcom_pcie_deinit_2_7_0, > + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > +}; > + > static const struct qcom_pcie_cfg cfg_1_0_0 = { > .ops = &ops_1_0_0, > }; And try to keep these structs sorted by revision. At least put this one after ops_1_9_0. Johan
On 10/18/2024 9:51 PM, Johan Hovold wrote: > On Wed, Oct 16, 2024 at 08:04:10PM -0700, Qiang Yu wrote: >> On SC8280X family SoC, PCIe controllers are connected to SMMUv3, hence >> they don't need the config_sid() callback in ops_1_9_0 struct. Fix it by >> introducing a new ops struct, namely ops_1_21_0 which is same as ops_1_9_0 >> without config_sid() callback so that BDF2SID mapping won't be configured >> during init. > The sc8280xp PCIe devicetree nodes do not specify an 'iommu-map' so the > config_sid() callback is effectively a no-op. Please rephrase this so > that it becomes obvious that this is a clean up rather than fix. > >> Fixes: 70574511f3fc ("PCI: qcom: Add support for SC8280XP") > And drop the Fixes tag. > >> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> >> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 12 +++++++++++- >> 1 file changed, 11 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 88a98be930e3..468bd4242e61 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 = { >> .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, >> }; >> >> +/* Qcom IP rev.: 1.21.0 */ > Is this the actual IP revision on sc8280xp (and not just the revision > used on x1e80100)? Get confirmation from HW team. 1.21.0 is Qcom IP rev of sc8280xp, Synopsis IP rev is 5.60a. Thanks, Qiang > Please also provide the Synopsis IP rev like the other configs do. > >> +static const struct qcom_pcie_ops ops_1_21_0 = { >> + .get_resources = qcom_pcie_get_resources_2_7_0, >> + .init = qcom_pcie_init_2_7_0, >> + .post_init = qcom_pcie_post_init_2_7_0, >> + .host_post_init = qcom_pcie_host_post_init_2_7_0, >> + .deinit = qcom_pcie_deinit_2_7_0, >> + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, >> +}; >> + >> static const struct qcom_pcie_cfg cfg_1_0_0 = { >> .ops = &ops_1_0_0, >> }; > And try to keep these structs sorted by revision. At least put this one > after ops_1_9_0. > > Johan
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 88a98be930e3..468bd4242e61 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 = { .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; +/* Qcom IP rev.: 1.21.0 */ +static const struct qcom_pcie_ops ops_1_21_0 = { + .get_resources = qcom_pcie_get_resources_2_7_0, + .init = qcom_pcie_init_2_7_0, + .post_init = qcom_pcie_post_init_2_7_0, + .host_post_init = qcom_pcie_host_post_init_2_7_0, + .deinit = qcom_pcie_deinit_2_7_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, +}; + static const struct qcom_pcie_cfg cfg_1_0_0 = { .ops = &ops_1_0_0, }; @@ -1405,7 +1415,7 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = { }; static const struct qcom_pcie_cfg cfg_sc8280xp = { - .ops = &ops_1_9_0, + .ops = &ops_1_21_0, .no_l0s = true, };
On SC8280X family SoC, PCIe controllers are connected to SMMUv3, hence they don't need the config_sid() callback in ops_1_9_0 struct. Fix it by introducing a new ops struct, namely ops_1_21_0 which is same as ops_1_9_0 without config_sid() callback so that BDF2SID mapping won't be configured during init. Fixes: 70574511f3fc ("PCI: qcom: Add support for SC8280XP") Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/pci/controller/dwc/pcie-qcom.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)