| Message ID | 20241028-upstream_s32cc_gmac-v4-0-03618f10e3e2@oss.nxp.com |
|---|---|
| Headers | show |
| Series | Add support for Synopsis DWMAC IP on NXP Automotive SoCs S32G2xx/S32G3xx/S32R45 | expand |
On Mon, Oct 28, 2024 at 09:24:47PM +0100, Jan Petrous via B4 Relay wrote: > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com> > > Utilize a new helper function rgmii_clock(). > > Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
On Mon, Oct 28, 2024 at 09:24:51PM +0100, Jan Petrous via B4 Relay wrote: > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com> > > Utilize a new helper function rgmii_clock(). > > Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
On Mon, Oct 28, 2024 at 09:24:53PM +0100, Jan Petrous via B4 Relay wrote: > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com> > > Utilize a new helper function rgmii_clock(). > > Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
> +#define GMAC_TX_RATE_125M 125000000 /* 125MHz */ > +#define GMAC_TX_RATE_25M 25000000 /* 25MHz */ > +#define GMAC_TX_RATE_2M5 2500000 /* 2.5MHz */ With the swap to the new helper, i think 25M and 2M5 are no longer needed. > +static int s32_gmac_init(struct platform_device *pdev, void *priv) > +{ > + struct s32_priv_data *gmac = priv; > + int ret; > + > + ret = clk_set_rate(gmac->tx_clk, GMAC_TX_RATE_125M); > + if (!ret) > + ret = clk_prepare_enable(gmac->tx_clk); > + > + if (ret) { > + dev_err(&pdev->dev, "Can't set tx clock\n"); > + return ret; > + } > + > + ret = clk_prepare_enable(gmac->rx_clk); > + if (ret) > + dev_dbg(&pdev->dev, "Can't set rx, clock source is disabled.\n"); > + else > + gmac->rx_clk_enabled = true; Why would this fail? And if it does fail, why is it not fatal? Maybe a comment here. > +static void s32_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode) > +{ > + struct s32_priv_data *gmac = priv; > + long tx_clk_rate; > + int ret; > + > + if (!gmac->rx_clk_enabled) { > + ret = clk_prepare_enable(gmac->rx_clk); > + if (ret) { > + dev_err(gmac->dev, "Can't set rx clock\n"); dev_err(), so is failing now fatal, but since this is a void function, you cannot report the error up the call stack? Andrew
The SoC series S32G2xx and S32G3xx feature one DWMAC instance, the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII interface over Pinctrl device or the output can be routed to the embedded SerDes for SGMII connectivity. The provided stmmac glue code implements only basic functionality, interface support is restricted to RGMII only. More, including SGMII/SerDes support will come later. This patchset adds stmmac glue driver based on downstream NXP git [0]. [0] https://github.com/nxp-auto-linux/linux v4: - fixed empty commit messages for rgmi_clock() helper patches - fixed yaml path in MAINTAINERS - switched to platform_driver::remove() as suggested Uwe - yaml: returned back all compatibility sting values - added better commit description for rgmii_clock() helper - Link to v3: https://lore.kernel.org/r/20241013-upstream_s32cc_gmac-v3-0-d84b5a67b930@oss.nxp.com v3: - switched to b4 WoW to overcome threading issue with b4 - extracted the hunk with the typo fix from v2 patch#1 to separate patch as Jacob suggested - removed dead code for RMII/MII support, which will be added alter - used new rgmii_clock() helper in other stmmac:dwmac glue drivers - yaml: compatible strings compressed to simple one "nxp,s32-dwmac", removed duplicated required properties, already defined in snps,dwmac, fixed example v2: - send to wider audience as first version missed many maintainers - created rgmi_clk() helper as Russell suggested (see patch#4) - address Andrew's, Russell's, Serge's and Simon's comments Message-ID: <AM9PR04MB85066576AD6848E2402DA354E2832@AM9PR04MB8506.eurprd04.prod.outlook.com> Cc: Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> --- Jan Petrous (OSS) (16): net: driver: stmmac: Fix CSR divider comment net: driver: stmmac: Extend CSR calc support net: stmmac: Fix clock rate variables size net: phy: Add helper for mapping RGMII link speed to clock rate net: dwmac-dwc-qos-eth: Use helper rgmii_clock net: dwmac-imx: Use helper rgmii_clock net: dwmac-intel-plat: Use helper rgmii_clock net: dwmac-rk: Use helper rgmii_clock net: dwmac-starfive: Use helper rgmii_clock net: macb: Use helper rgmii_clock net: xgene_enet: Use helper rgmii_clock net: dwmac-sti: Use helper rgmii_clock dt-bindings: net: Add DT bindings for DWMAC on NXP S32G/R SoCs net: stmmac: dwmac-s32: add basic NXP S32G/S32R glue driver MAINTAINERS: Add Jan Petrous as the NXP S32G/R DWMAC driver maintainer net: stmmac: dwmac-s32: Read PTP clock rate when ready .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 98 +++++++++ .../devicetree/bindings/net/snps,dwmac.yaml | 3 + MAINTAINERS | 7 + drivers/net/ethernet/apm/xgene/xgene_enet_hw.c | 16 +- drivers/net/ethernet/cadence/macb_main.c | 14 +- drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + drivers/net/ethernet/stmicro/stmmac/common.h | 2 + .../ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c | 11 +- drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c | 15 +- .../net/ethernet/stmicro/stmmac/dwmac-intel-plat.c | 20 +- .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 2 +- drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 30 +-- drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 239 +++++++++++++++++++++ .../net/ethernet/stmicro/stmmac/dwmac-starfive.c | 19 +- drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 18 +- drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 2 +- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 2 +- include/linux/phy.h | 23 ++ include/linux/stmmac.h | 10 +- 21 files changed, 431 insertions(+), 119 deletions(-) --- base-commit: 2f87d0916ce0d2925cedbc9e8f5d6291ba2ac7b2 change-id: 20240923-upstream_s32cc_gmac-6891eb75b126 Best regards,