diff mbox series

scsi: qla1280.h

Message ID 20241106225455.2736-1-linmag7@gmail.com
State New
Headers show
Series scsi: qla1280.h | expand

Commit Message

Magnus Lindholm Nov. 6, 2024, 10:49 p.m. UTC
Fix hardware revision numbering for ISP1020/1040. HWMASK
 suggest that the revision number only needs four bits, this is consistent
 with how NetBSD does things in their ISP driver. verified on a IPS1040B which
 is seen as rev 5 not BIT_4. ISP_CFG0_1040A is referenced on line 2187 in qla1280.c
 

Signed-off-by: Magnus Lindholm <linmag7@gmail.com>
---
 drivers/scsi/qla1280.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

'Christoph Hellwig' Nov. 12, 2024, 5:48 a.m. UTC | #1
Please write a useful Subject line, e.g.

qla1280: fix hardware revision numbering for ISP1020/1040

On Wed, Nov 06, 2024 at 11:49:57PM +0100, Magnus Lindholm wrote:
>  Fix hardware revision numbering for ISP1020/1040. HWMASK

and the commit log shold not be indented by whitespaces and wrapped
after 73 characters.
diff mbox series

Patch

diff --git a/drivers/scsi/qla1280.h b/drivers/scsi/qla1280.h
index d309e2ca14de..796cb493a4df 100644
--- a/drivers/scsi/qla1280.h
+++ b/drivers/scsi/qla1280.h
@@ -116,12 +116,12 @@  struct device_reg {
 	uint16_t id_h;		/* ID high */
 	uint16_t cfg_0;		/* Configuration 0 */
 #define ISP_CFG0_HWMSK   0x000f	/* Hardware revision mask */
-#define ISP_CFG0_1020    BIT_0	/* ISP1020 */
-#define ISP_CFG0_1020A	 BIT_1	/* ISP1020A */
-#define ISP_CFG0_1040	 BIT_2	/* ISP1040 */
-#define ISP_CFG0_1040A	 BIT_3	/* ISP1040A */
-#define ISP_CFG0_1040B	 BIT_4	/* ISP1040B */
-#define ISP_CFG0_1040C	 BIT_5	/* ISP1040C */
+#define ISP_CFG0_1020    1	/* ISP1020 */
+#define ISP_CFG0_1020A	 2	/* ISP1020A */
+#define ISP_CFG0_1040	 3	/* ISP1040 */
+#define ISP_CFG0_1040A	 4	/* ISP1040A */
+#define ISP_CFG0_1040B	 5	/* ISP1040B */
+#define ISP_CFG0_1040C	 6	/* ISP1040C */
 	uint16_t cfg_1;		/* Configuration 1 */
 #define ISP_CFG1_F128    BIT_6  /* 128-byte FIFO threshold */
 #define ISP_CFG1_F64     BIT_4|BIT_5 /* 128-byte FIFO threshold */