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[v6,0/7] gpio: siul2-s32g2: add initial GPIO driver

Message ID 20241113101124.1279648-1-andrei.stefanescu@oss.nxp.com
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Series gpio: siul2-s32g2: add initial GPIO driver | expand

Message

Andrei Stefanescu Nov. 13, 2024, 10:10 a.m. UTC
This patch series adds support for basic GPIO
operations(set, get, direction_output/input, set_config).

There are two SIUL2 hardware modules: SIUL2_0 and SIUL2_1.
However, this driver exports both as a single GPIO driver.
This is because the interrupt registers are located only
in SIUL2_1, even for GPIOs that are part of SIUL2_0.

There are two gaps in the GPIO ranges:
- 102-111(inclusive) are invalid
- 123-143(inclusive) are invalid

These will be excluded via the `gpio-reserved-ranges`
property.

Writing and reading GPIO values is done via the PGPDO/PGPDI
registers(Parallel GPIO Pad Data Output/Input) which are
16 bit registers, each bit corresponding to a GPIO.

Note that the PGPDO order is similar to a big-endian grouping
of two registers:
PGPDO1, PGPDO0, PGPDO3, PGPDO2, PGPDO5, PGPDO4, gap, PGPDO6.

I have other patches for this driver:
- interrupt support
- power management callbacks

which I plan to upstream after this series gets merged
in order to simplify the review process.

v6 -> v5
- removed description for reg in the dt-bindings and added
  maxItems
- dropped label for example in the dt-bindings
- simplified the example in the dt-bindings
- changed dt-bindings filename to nxp,s32g2-siul2.yaml
- changed title in the dt-bindings
- dropped minItmes from gpio-ranges/gpio-reserved-ranges
  and added maxItems to gpio-reserved-ranges
- added required block for -grp[0-9]$ nodes
- switch to using "" as quotes
- kernel test robot: fixed frame sizes, added description
  for reg_name, fixed typo in gpio_configs_lock, removed
  uninitialized ret variable usage
- ordered includes in nxp-siul2.c, switched to dev-err-probe
  added a mention that other commits will add nvmem functionality
  to the mfd driver
- switched spin_lock_irqsave to scoped_guard statement
- switched dev_err to dev_err_probe in pinctrl-s32cc in places
  reached during the probing part

v5 -> v4
- fixed di_div error
- fixed dt-bindings error
- added Co-developed-by tags
- added new MFD driver nxp-siul2.c
- made the old pinctrl driver an MFD cell
- added the GPIO driver in the existing SIUL2 pinctrl one
- Switch from "devm_pinctrl_register" to
  "devm_pinctrl_register_and_init"

v4 -> v3
- removed useless parentheses
- added S32G3 fallback compatible
- fixed comment alignment
- fixed dt-bindings license
- fixed modpost: "__udivdi3"
- moved MAINTAINERS entry to have the new GPIO driver
  together with other files related to S32G

v3 -> v2
- fix dt-bindings schema id
- add maxItems to gpio-ranges
- removed gpio label from dt-bindings example
- added changelog for the MAINTAINERS commit and
  added separate entry for the SIUL2 GPIO driver
- added guard(raw_spinlock_irqsave) in
  'siul2_gpio_set_direction'
- updated the description for
  'devm_platform_get_and_ioremap_resource_byname'

v2 -> v1
dt-bindings:
- changed filename to match compatible
- fixed commit messages
- removed dt-bindings unnecessary properties descriptions
- added minItems for the interrupts property
driver:
- added depends on ARCH_S32 || COMPILE_TEST to Kconfig
- added select REGMAP_MMIO to Kconfig
- remove unnecessary include
- add of_node_put after `siul2_get_gpio_pinspec`
- removed inline from function definitions
- removed match data and moved the previous platdata
  definition to the top of the file to be visible
- replace bitmap_set/clear with __clear_bit/set_bit
  and devm_bitmap_zalloc with devm_kzalloc
- switched to gpiochip_generic_request/free/config
- fixed dev_err format for size_t reported by
  kernel test robot
- add platform_get_and_ioremap_resource_byname wrapper

Andrei Stefanescu (7):
  dt-bindings: mfd: add support for the NXP SIUL2 module
  mfd: nxp-siul2: add support for NXP SIUL2
  arm64: dts: s32g: make pinctrl part of mfd node
  pinctrl: s32: convert the driver into an mfd cell
  pinctrl: s32cc: change to "devm_pinctrl_register_and_init"
  pinctrl: s32cc: implement GPIO functionality
  MAINTAINERS: add MAINTAINER for NXP SIUL2 MFD driver

 .../bindings/mfd/nxp,s32g2-siul2.yaml         | 165 +++++
 MAINTAINERS                                   |   2 +
 arch/arm64/boot/dts/freescale/s32g2.dtsi      |  26 +-
 arch/arm64/boot/dts/freescale/s32g3.dtsi      |  26 +-
 drivers/mfd/Kconfig                           |  12 +
 drivers/mfd/Makefile                          |   1 +
 drivers/mfd/nxp-siul2.c                       | 410 +++++++++++++
 drivers/pinctrl/nxp/pinctrl-s32.h             |   3 +-
 drivers/pinctrl/nxp/pinctrl-s32cc.c           | 564 +++++++++++++-----
 drivers/pinctrl/nxp/pinctrl-s32g2.c           |  25 +-
 include/linux/mfd/nxp-siul2.h                 |  55 ++
 11 files changed, 1089 insertions(+), 200 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/nxp,s32g2-siul2.yaml
 create mode 100644 drivers/mfd/nxp-siul2.c
 create mode 100644 include/linux/mfd/nxp-siul2.h

Comments

Krzysztof Kozlowski Nov. 19, 2024, 9:21 a.m. UTC | #1
On 13/11/2024 11:10, Andrei Stefanescu wrote:
> +
> +properties:
> +  compatible:
> +    enum:
> +      - nxp,s32g2-siul2
> +      - nxp,s32g3-siul2

Not much improved. See other NXP bindings how they do this.

> +
> +  reg:
> +    maxItems: 2
> +
> +  reg-names:
> +    items:
> +      - const: siul20
> +      - const: siul21
> +
> +  gpio-controller: true
> +
> +  "#gpio-cells":
> +    const: 2
> +
> +  gpio-ranges:
> +    maxItems: 2
> +
> +  gpio-reserved-ranges:
> +    maxItems: 2

That's odd to always require two reserved ranges. Does this mean all
devices have exactly the same reserved GPIOs? Then the driver should not
export them.

> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  "#interrupt-cells":
> +    const: 2
> +
> +  nvmem-layout:
> +    $ref: /schemas/nvmem/layouts/nvmem-layout.yaml#
> +    description:
> +      This container may reference an NVMEM layout parser.
> +
> +patternProperties:
> +  "-hog(-[0-9]+)?$":
> +    required:
> +      - gpio-hog
> +
> +  "-pins$":
> +    type: object
> +    additionalProperties: false
> +
> +    patternProperties:
> +      "-grp[0-9]$":
> +        type: object
> +        allOf:
> +          - $ref: /schemas/pinctrl/pinmux-node.yaml#
> +          - $ref: /schemas/pinctrl/pincfg-node.yaml#
> +        description:
> +          Pinctrl node's client devices specify pin muxes using subnodes,
> +          which in turn use the standard properties below.
> +
> +        properties:
> +          bias-disable: true
> +          bias-high-impedance: true
> +          bias-pull-up: true
> +          bias-pull-down: true
> +          drive-open-drain: true
> +          input-enable: true
> +          output-enable: true
> +
> +          pinmux:
> +            description: |
> +              An integer array for representing pinmux configurations of
> +              a device. Each integer consists of a PIN_ID and a 4-bit
> +              selected signal source(SSS) as IOMUX setting, which is
> +              calculated as: pinmux = (PIN_ID << 4 | SSS)
> +
> +          slew-rate:
> +            description: Supported slew rate based on Fmax values (MHz)
> +            enum: [83, 133, 150, 166, 208]
> +        required:
> +          - pinmux
> +
> +        additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - gpio-controller
> +  - "#gpio-cells"
> +  - gpio-ranges
> +  - gpio-reserved-ranges
> +  - interrupts
> +  - interrupt-controller
> +  - "#interrupt-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    siul2@4009c000 {

<form letter>
This is a friendly reminder during the review process.

It seems my or other reviewer's previous comments were not fully
addressed. Maybe the feedback got lost between the quotes, maybe you
just forgot to apply it. Please go back to the previous discussion and
either implement all requested changes or keep discussing them.

Thank you.
</form letter>



Best regards,
Krzysztof
Andrei Stefanescu Nov. 19, 2024, 9:44 a.m. UTC | #2
Hi Krzysztof,

Thank you for your review!

On 19/11/2024 11:21, Krzysztof Kozlowski wrote:
> On 13/11/2024 11:10, Andrei Stefanescu wrote:
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - nxp,s32g2-siul2
>> +      - nxp,s32g3-siul2
> 
> Not much improved. See other NXP bindings how they do this.
> 

Do you mean to have the "nxp,s32g3-siul2" compatible fall back to the g2 one?

>> +
>> +  gpio-reserved-ranges:
>> +    maxItems: 2
> 
> That's odd to always require two reserved ranges. Does this mean all
> devices have exactly the same reserved GPIOs? Then the driver should not
> export them.

Yes, the driver exports GPIOs from two hardware modules because they are
tightly coupled. I export two gpio-ranges, each one corresponding to a
hardware module. If I were to export more gpio-ranges, thus avoiding
gpio-reserved-ranges, it would be hard to know to which hardware module
a gpio-range belongs. I would like to keep the current implementation
regarding this problem. Would that be ok?

> 
> <form letter>
> This is a friendly reminder during the review process.
> 
> It seems my or other reviewer's previous comments were not fully
> addressed. Maybe the feedback got lost between the quotes, maybe you
> just forgot to apply it. Please go back to the previous discussion and
> either implement all requested changes or keep discussing them.
> 
> Thank you.
> </form letter>

Yes, sorry for this. I initially thought you were referring to the
label name. I now realize that I misread it. It will be changed
to pinctrl in the next version.
> 
> 
> 
> Best regards,
> Krzysztof
> 

Best regards,
Andrei
Krzysztof Kozlowski Nov. 19, 2024, 1:12 p.m. UTC | #3
On Tue, Nov 19, 2024 at 11:44:23AM +0200, Andrei Stefanescu wrote:
> Hi Krzysztof,
> 
> Thank you for your review!
> 
> On 19/11/2024 11:21, Krzysztof Kozlowski wrote:
> > On 13/11/2024 11:10, Andrei Stefanescu wrote:
> >> +
> >> +properties:
> >> +  compatible:
> >> +    enum:
> >> +      - nxp,s32g2-siul2
> >> +      - nxp,s32g3-siul2
> > 
> > Not much improved. See other NXP bindings how they do this.
> > 
> 
> Do you mean to have the "nxp,s32g3-siul2" compatible fall back to the g2 one?

Yes, compatibility between devices means fallback.

> 
> >> +
> >> +  gpio-reserved-ranges:
> >> +    maxItems: 2
> > 
> > That's odd to always require two reserved ranges. Does this mean all
> > devices have exactly the same reserved GPIOs? Then the driver should not
> > export them.
> 
> Yes, the driver exports GPIOs from two hardware modules because they are
> tightly coupled. I export two gpio-ranges, each one corresponding to a
> hardware module. If I were to export more gpio-ranges, thus avoiding
> gpio-reserved-ranges, it would be hard to know to which hardware module
> a gpio-range belongs. I would like to keep the current implementation
> regarding this problem. Would that be ok?

I don't understand why this is needed then. If you always export same
set of GPIOs, why do you export something which is unusable/reserved?

Best regards,
Krzysztof
Andrei Stefanescu Nov. 20, 2024, 9:21 a.m. UTC | #4
Hi Krzysztof,

>>>> +
>>>> +  gpio-reserved-ranges:
>>>> +    maxItems: 2

Would it be better if I removed the maxItems constraint? Looking at it now,
I think it should rather be minItems: 2 in order to allow the user to
further remove other GPIOs.

>>>
>>> That's odd to always require two reserved ranges. Does this mean all
>>> devices have exactly the same reserved GPIOs? Then the driver should not
>>> export them.
>>
>> Yes, the driver exports GPIOs from two hardware modules because they are
>> tightly coupled. I export two gpio-ranges, each one corresponding to a
>> hardware module. If I were to export more gpio-ranges, thus avoiding
>> gpio-reserved-ranges, it would be hard to know to which hardware module
>> a gpio-range belongs. I would like to keep the current implementation
>> regarding this problem. Would that be ok?
> 
> I don't understand why this is needed then. If you always export same
> set of GPIOs, why do you export something which is unusable/reserved?
>

I will detail a bit about SIUL2 GPIO ranges here:
SIUL2_0 exports GPIOs 0 - 101
SIUL2_1 exports GPIOs 112 - 122 and 144 - 190

Therefore, we have two gaps: 102 - 111 and 123 - 143. This applies for both
S32G2 and S32G3 SoCs.

AFAIK the only ways to exclude GPIOs from being exported are the following:
- split the gpio-ranges property so it doesn't include those GPIOs
  I thought about doing this but I think this would involve other vendor
  specific properties in order to know the memory region to use for each GPIO range.
  Currently, we have two GPIO ranges and each one maps to its respective
  SIUL2 module.
- using gpio-reserved-ranges which is my current approach because, in my opinion,
  it is the simplest approach.
- registering multiple gpio_chips
  I know this approach is used when dealing with multiple banks. However,
  I think GPIO banks would rather apply to SIUL2 modules and not to our
  valid GPIO ranges.

What are your thoughts about this?

Best regards,
Andrei