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[GIT,PULL] mtd: spi-nor: changes for v6.13

Message ID 2d182f21-9766-4c05-8b97-786af69666a0@linaro.org
State New
Headers show
Series [GIT,PULL] mtd: spi-nor: changes for v6.13 | expand

Pull-request

git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git tags/spi-nor/for-6.13

Message

Tudor Ambarus Nov. 12, 2024, 9:32 a.m. UTC 
Hi,

SPI NOR v6.13 PR includes the mtd/spi-mem-swap16-for-6.13 tag that
contains a patch for SPI MEM and one for the SPI MXIC controller. I got
Mark's approval on queuing them.

Thanks,
ta


The following changes since commit 9852d85ec9d492ebef56dc5f229416c925758edc:

  Linux 6.12-rc1 (2024-09-29 15:06:19 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git
tags/spi-nor/for-6.13

for you to fetch changes up to 98d1fb94ce75f39febd456d6d3cbbe58b6678795:

  mtd: spi-nor: core: replace dummy buswidth from addr to data
(2024-11-12 10:31:17 +0200)

----------------------------------------------------------------
SPI NOR introduces byte swap support for 8D-8D-8D mode and a user for
it: macronix. SPI NOR flashes may swap the bytes on a 16-bit boundary
when configured in Octal DTR mode. For such cases the byte order is
propagated through SPI MEM to the SPI controllers so that the controllers
swap the bytes back at runtime. This avoids breaking the boot sequence
because of the endianness problems that appear when the bootloaders use
1-1-1 and the kernel uses 8D-8D-8D with byte swap support. Along with the
SPI MEM byte swap support we queue a patch for the SPI MXIC controller
that swaps the bytes back at runtime.

----------------------------------------------------------------
AlvinZhou (3):
      spi: mxic: Add support for swapping byte
      mtd: spi-nor: add Octal DTR support for Macronix flash
      mtd: spi-nor: add support for Macronix Octal flash

Cheng Ming Lin (1):
      mtd: spi-nor: core: replace dummy buswidth from addr to data

Takahiro Kuwano (1):
      mtd: spi-nor: spansion: Use nor->addr_nbytes in octal DTR mode in
RD_ANY_REG_OP

Tudor Ambarus (4):
      spi: spi-mem: Allow specifying the byte order in Octal DTR mode
      mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode
      mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT
      mtd: spi-nor: winbond: add "w/ and w/o SFDP" comment

 drivers/mtd/spi-nor/core.c     |  5 +++-
 drivers/mtd/spi-nor/core.h     |  1 +
 drivers/mtd/spi-nor/macronix.c | 99
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 drivers/mtd/spi-nor/sfdp.c     |  4 +++
 drivers/mtd/spi-nor/sfdp.h     |  1 +
 drivers/mtd/spi-nor/spansion.c |  1 +
 drivers/mtd/spi-nor/winbond.c  |  1 +
 drivers/spi/spi-mem.c          |  3 ++
 drivers/spi/spi-mxic.c         | 17 ++++++++---
 include/linux/spi/spi-mem.h    |  8 +++++-
 10 files changed, 133 insertions(+), 7 deletions(-)

Comments

Miquel Raynal Nov. 19, 2024, 12:20 p.m. UTC | #1 
On Tue, 12 Nov 2024 11:32:54 +0200, Tudor Ambarus wrote:
> SPI NOR v6.13 PR includes the mtd/spi-mem-swap16-for-6.13 tag that
> contains a patch for SPI MEM and one for the SPI MXIC controller. I got
> Mark's approval on queuing them.
> 
> Thanks,
> ta
> 
> 
> [...]

Merged into mtd/next, thanks!
-> https://git.kernel.org/mtd/c/34267d3c

Kind regards,
Miquèl